Dawit Abdi - Academia.edu (original) (raw)

Papers by Dawit Abdi

Research paper thumbnail of Performance Analysis of Baseflow Separation Methods: The Case of Rift Valley Lakes Basin, Ethiopia

Indonesian Journal of Earth Sciences

Adopting the appropriate method to separate baseflow from stream flow is desirable for future low... more Adopting the appropriate method to separate baseflow from stream flow is desirable for future low flow prediction, planning, management of water resources, and nourishing the environment as well. Thus, comparing the baseflow separation method is inevitable unfortunately not studied within the basin. Therefore, in this study, seven recursive digital filters (RDF) and two digital graphical (DGM) methods were compared in rift valley lakes basins. All the methods were calibrated manually with the help of BFI 3.0 tool; the performance of each method was checked by R2 and RMSE, taking the separation with maximum R2 and minimum RMSE were taken as appropriate separation method and (Baseflow Index) BFI was calculated by using the baseflow from the suitable method for each catchment. The outcomes of baseflow separation indicate that two methods (exponentially weighted moving average (EWMA) and Lynie-Holick) performed better than the other seven methods; unlikely, local minimum and one paramet...

Research paper thumbnail of Suppressing Ambipolar Conduction Using Dual Material Gate In Tunnel-Fets Having Heavily Doped Drain

In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppr... more In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Research paper thumbnail of 2-D Threshold Voltage Model for the Double-Gate p-n-p-n TFET With Localized Charges

IEEE Transactions on Electron Devices, 2016

In this paper, for the first time, we developed an analytical model for the surface potential of ... more In this paper, for the first time, we developed an analytical model for the surface potential of the double-gate p-n-p-n tunneling field-effect transistors (TFETs) considering the effect of localized charges at the Si-SiO2 interface near the source-channel junction. From the surface potential model, the minimum tunneling width is then evaluated and is used to extract the threshold voltage using the constant-current method. The model can be applied to study the effect of localized charges on the threshold voltage of the p-n-p-n TFETs as it captures the shift in the threshold voltage due to the change in the localized charge region length, localized charge density, and polarity. The accuracy of the proposed model is verified using 2-D Technology Computer-Aided Design simulations.

Research paper thumbnail of Dielectric modulated overlapping gate-on-drain tunnel-FET as a label-free biosensor

Superlattices and Microstructures, 2015

ABSTRACT

Research paper thumbnail of PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis

Superlattices and Microstructures, 2015

ABSTRACT A detailed study of a technique to realize a PNPN tunnel field effect transistor (TFET) ... more ABSTRACT A detailed study of a technique to realize a PNPN tunnel field effect transistor (TFET) with a controllable tunnel barrier width on the drain side is reported in this paper. By using the charge plasma concept on a doped N + /P-starting structure, we have demonstrated the possibility of realizing the PNPN TFET without the need for any additional chemically doped junctions. We have showed that using electrostatic doping on the drain side of TFETs provides a new design parameter, the gate-drain electrode gap. This gate-drain electrode gap can be used to control the ambipolar current in TFETs by controlling the tunneling barrier width at the channel-drain junction. Index Terms— Source-pocket (PNPN) TFET, tunneling, pocket implantation, in-built N + pocket, charge plasma, electrostatic doping, 2D TCAD simulation.

Research paper thumbnail of Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain

IEEE Journal of the Electron Devices Society, 2014

In this paper, we have demonstrated that overlapping the gate on the drain can suppress the ambip... more In this paper, we have demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET). Unlike in the conventional TFET where the gate controls the tunneling barrier width at both source-channel and channel-drain interfaces for different polarity of gate voltage, overlapping the gate on the drain limits the gate to control only the tunneling barrier width at the source-channel interface irrespective of the polarity of the gate voltage. As a result, the proposed overlapping gate-on-drain TFET exhibits suppressed ambipolar conduction even when the drain doping is as high as 1 × 10 19 cm −3. INDEX TERMS Ambipolarity, overlapping gate-on-drain, TFET, tunneling barrier width, overlap length.

Research paper thumbnail of In-Built N+ Pocket p-n-p-n Tunnel Field-Effect Transistor

IEEE Electron Device Letters, 2014

ABSTRACT The source-pocket (p-n-p-n) tunnel field effect transistor (TFET) has a narrow and highl... more ABSTRACT The source-pocket (p-n-p-n) tunnel field effect transistor (TFET) has a narrow and highly doped N+ pocket layer between the source and channel to enhance the overall performance of the conventional p-i-n TFET. However, realizing this, N+ pocket increases the fabrication complexity since either an epitaxial growth in vertical TFETs or an implantation in planar TFETs is required to create the N+ pocket. In this letter, using the charge plasma concept, we propose a technique to realize an in-built N+ pocket without the need for a separate implantation. We demonstrate using 2-D simulations that the proposed in-built N+ pocket p-n-p-n TFET exhibits a higher ION (~20 times) and a steeper subthreshold swing (25 mV/decade) as compared with the conventional p-i-n TFET. Our approach overcomes the difficulty of creating a narrow N+ pocket doping and thus makes the p-n-p-n TFET more attractive in carrying on with the scaling trend.

Research paper thumbnail of Regionalization of Low Flow Analysis in Data Scarce Region: The Case of the Lake Abaya-Chamo Sub-basin, Rift Valley Lakes Basin, Ethiopia

Journal of Water Management Modeling

Prediction of low flows in ungauged catchments is desirable for planning and management of water ... more Prediction of low flows in ungauged catchments is desirable for planning and management of water resources development and for sustaining the environment. The main objective of this study was to regionalize low flow indexes (the baseflow index BFI, Q80, Q90, and Q95) in the Lake Abaya–Chamo sub-basin by using multiple linear regression models. To develop the regional equation, nine baseflow separation methods were compared: two digital graphical methods and seven recursive digital filters were compared and applied in eight gauged catchments. The methods were evaluated through the coefficient of determination (R2) and the root mean square error (RMSE) as performance measures. The flow duration analyses were conducted to compute the flow exceedance quantiles Q80, Q90, and Q95. Regionalizing those indexes required the identification of homogeneous regions, which was accomplished through cluster analysis, based on physiographic and climatic data. Three significantly different homogeneou...

Research paper thumbnail of Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis

IEEE Access, 2021

In this paper, using calibrated TCAD simulations, we demonstrate how the performance of a Tunneli... more In this paper, using calibrated TCAD simulations, we demonstrate how the performance of a Tunneling FET (TFET) can be improved by using a new phenomenon called drain induced barrier widening (DIBW) at the source-channel junction. Our results indicate that TFETs in which DIBW dominates exhibit a steep subthreshold swing (≈35 mV/dec) and a low OFF-state current (≈10 −16 A/µm) without affecting the ON-state current. We also show that TFETs exhibit a reverse short channel effect due to an increase in the tunneling width at the source-channel junction. INDEX TERMS Drain induced barrier widening (DIBW), gate-on-drain overlap, OFF-state current, reverse short channel effects, subthreshold swing, TCAD simulation, tunnel field effect transistor (TFET).

Research paper thumbnail of Effect of Drain Induced Barrier Enhancement on Subthreshold Swing and OFF-state Current of Short Channel MOSFETs: A TCAD Study

IEEE Access, 2021

In this paper, with the help of calibrated 2-D simulations, we report a detailed study on the eff... more In this paper, with the help of calibrated 2-D simulations, we report a detailed study on the effect of drain induced barrier enhancement on the subthreshold swing and OFF-state current of a short channel MOSFET. We demonstrate that the presence of gate-on-drain overlap in a short channel MOSFET leads to drain induced barrier enhancement (DIBE). We show that as a result of DIBE, a MOSFET can achieve near ideal subthreshold swing, diminished DIBL, constant threshold voltage and improved I ON /I OFF ratio at room temperature, without being affected by channel length variations. INDEX TERMS Drain induced barrier enhancement (DIBE), Drain induced barrier lowering (DIBL), gate-on-drain overlap, leakage current, MOSFET, scaling, short channel effects (SCE), subthreshold swing, and threshold voltage.

Research paper thumbnail of Performance Investigation of Single Grain Boundary Junctionless Field Effect Transistor

IEEE Journal of the Electron Devices Society, 2016

In this paper, we report a single grain boundary (GB) junctionless thin film transistor (JLFET) o... more In this paper, we report a single grain boundary (GB) junctionless thin film transistor (JLFET) on recrystallized polycrystalline silicon (poly-Si JLFET). Using 2-D simulations, the electrical performance of the poly-Si JLFET is evaluated for different single GB locations in the channel. Without the need for creating the source and the drain regions by implantation, we demonstrate the prospect of achieving thin-film poly-Si JLFETs whose performance is reasonable for silicon film thicknesses less than 10 nm.

Research paper thumbnail of Dopingless tunnel FET with a hetero-material gate: Design and analysis

2014 IEEE 2nd International Conference on Emerging Electronics (ICEE), 2014

Research paper thumbnail of Dopingless PNPN tunnel FET with improved performance: Design and analysis

Superlattices and Microstructures, 2015

In this paper, we present a two-dimensional simulation study of a dopingless PNPN TFET with a het... more In this paper, we present a two-dimensional simulation study of a dopingless PNPN TFET with a hetero-gate dielectric. Using a dual-material-gate in a dopingless TFET, the energy band gap on the source side is modulated to create an N + source pocket. Our technique obviates the need to use ion implantation for the formation of the N + source pocket. The dopingless PNPN TFET with a hetero-gate dielectric is demonstrated to exhibit a superior performance in terms of ON-state current and subthreshold swing when compared to a conventional dopingless TFET. Our results may pave the way for realizing high performance dopingless TFETs using a low thermal budget required for low power and low cost applications.. Index Terms-Tunnel field effect transistor (TFET), PNPN TFET, tunneling, dopingless, hetero-gate-dielectric, N + source pocket.

Research paper thumbnail of Single Grain Boundary Tunnel Field Effect Transistors on Recrystallized Polycrystalline Silicon: Proposal and Investigation

IEEE Electron Device Letters, 2014

A single grain boundary tunnel field effect transistor (TFET) on recrystallized polycrystalline s... more A single grain boundary tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is reported in this letter. By varying the position of the grain boundary (GB) in the channel, the performance of the proposed device is evaluated using calibrated 2-D simulations. Our results show the possibility of realizing low-cost thin-film recrystallized polycrystalline tunnel FETs with low OFF-state current and low subthreshold swing compared with the thin-film transistors. By introducing the source N + pocket doping, it is also shown that the proposed single GB PNPN TFET exhibits enhanced ON-state current, making it suitable for low power display applications, including the driver circuits.

Research paper thumbnail of Performance Analysis of Baseflow Separation Methods: The Case of Rift Valley Lakes Basin, Ethiopia

Indonesian Journal of Earth Sciences

Adopting the appropriate method to separate baseflow from stream flow is desirable for future low... more Adopting the appropriate method to separate baseflow from stream flow is desirable for future low flow prediction, planning, management of water resources, and nourishing the environment as well. Thus, comparing the baseflow separation method is inevitable unfortunately not studied within the basin. Therefore, in this study, seven recursive digital filters (RDF) and two digital graphical (DGM) methods were compared in rift valley lakes basins. All the methods were calibrated manually with the help of BFI 3.0 tool; the performance of each method was checked by R2 and RMSE, taking the separation with maximum R2 and minimum RMSE were taken as appropriate separation method and (Baseflow Index) BFI was calculated by using the baseflow from the suitable method for each catchment. The outcomes of baseflow separation indicate that two methods (exponentially weighted moving average (EWMA) and Lynie-Holick) performed better than the other seven methods; unlikely, local minimum and one paramet...

Research paper thumbnail of Suppressing Ambipolar Conduction Using Dual Material Gate In Tunnel-Fets Having Heavily Doped Drain

In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppr... more In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Research paper thumbnail of 2-D Threshold Voltage Model for the Double-Gate p-n-p-n TFET With Localized Charges

IEEE Transactions on Electron Devices, 2016

In this paper, for the first time, we developed an analytical model for the surface potential of ... more In this paper, for the first time, we developed an analytical model for the surface potential of the double-gate p-n-p-n tunneling field-effect transistors (TFETs) considering the effect of localized charges at the Si-SiO2 interface near the source-channel junction. From the surface potential model, the minimum tunneling width is then evaluated and is used to extract the threshold voltage using the constant-current method. The model can be applied to study the effect of localized charges on the threshold voltage of the p-n-p-n TFETs as it captures the shift in the threshold voltage due to the change in the localized charge region length, localized charge density, and polarity. The accuracy of the proposed model is verified using 2-D Technology Computer-Aided Design simulations.

Research paper thumbnail of Dielectric modulated overlapping gate-on-drain tunnel-FET as a label-free biosensor

Superlattices and Microstructures, 2015

ABSTRACT

Research paper thumbnail of PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis

Superlattices and Microstructures, 2015

ABSTRACT A detailed study of a technique to realize a PNPN tunnel field effect transistor (TFET) ... more ABSTRACT A detailed study of a technique to realize a PNPN tunnel field effect transistor (TFET) with a controllable tunnel barrier width on the drain side is reported in this paper. By using the charge plasma concept on a doped N + /P-starting structure, we have demonstrated the possibility of realizing the PNPN TFET without the need for any additional chemically doped junctions. We have showed that using electrostatic doping on the drain side of TFETs provides a new design parameter, the gate-drain electrode gap. This gate-drain electrode gap can be used to control the ambipolar current in TFETs by controlling the tunneling barrier width at the channel-drain junction. Index Terms— Source-pocket (PNPN) TFET, tunneling, pocket implantation, in-built N + pocket, charge plasma, electrostatic doping, 2D TCAD simulation.

Research paper thumbnail of Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain

IEEE Journal of the Electron Devices Society, 2014

In this paper, we have demonstrated that overlapping the gate on the drain can suppress the ambip... more In this paper, we have demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET). Unlike in the conventional TFET where the gate controls the tunneling barrier width at both source-channel and channel-drain interfaces for different polarity of gate voltage, overlapping the gate on the drain limits the gate to control only the tunneling barrier width at the source-channel interface irrespective of the polarity of the gate voltage. As a result, the proposed overlapping gate-on-drain TFET exhibits suppressed ambipolar conduction even when the drain doping is as high as 1 × 10 19 cm −3. INDEX TERMS Ambipolarity, overlapping gate-on-drain, TFET, tunneling barrier width, overlap length.

Research paper thumbnail of In-Built N+ Pocket p-n-p-n Tunnel Field-Effect Transistor

IEEE Electron Device Letters, 2014

ABSTRACT The source-pocket (p-n-p-n) tunnel field effect transistor (TFET) has a narrow and highl... more ABSTRACT The source-pocket (p-n-p-n) tunnel field effect transistor (TFET) has a narrow and highly doped N+ pocket layer between the source and channel to enhance the overall performance of the conventional p-i-n TFET. However, realizing this, N+ pocket increases the fabrication complexity since either an epitaxial growth in vertical TFETs or an implantation in planar TFETs is required to create the N+ pocket. In this letter, using the charge plasma concept, we propose a technique to realize an in-built N+ pocket without the need for a separate implantation. We demonstrate using 2-D simulations that the proposed in-built N+ pocket p-n-p-n TFET exhibits a higher ION (~20 times) and a steeper subthreshold swing (25 mV/decade) as compared with the conventional p-i-n TFET. Our approach overcomes the difficulty of creating a narrow N+ pocket doping and thus makes the p-n-p-n TFET more attractive in carrying on with the scaling trend.

Research paper thumbnail of Regionalization of Low Flow Analysis in Data Scarce Region: The Case of the Lake Abaya-Chamo Sub-basin, Rift Valley Lakes Basin, Ethiopia

Journal of Water Management Modeling

Prediction of low flows in ungauged catchments is desirable for planning and management of water ... more Prediction of low flows in ungauged catchments is desirable for planning and management of water resources development and for sustaining the environment. The main objective of this study was to regionalize low flow indexes (the baseflow index BFI, Q80, Q90, and Q95) in the Lake Abaya–Chamo sub-basin by using multiple linear regression models. To develop the regional equation, nine baseflow separation methods were compared: two digital graphical methods and seven recursive digital filters were compared and applied in eight gauged catchments. The methods were evaluated through the coefficient of determination (R2) and the root mean square error (RMSE) as performance measures. The flow duration analyses were conducted to compute the flow exceedance quantiles Q80, Q90, and Q95. Regionalizing those indexes required the identification of homogeneous regions, which was accomplished through cluster analysis, based on physiographic and climatic data. Three significantly different homogeneou...

Research paper thumbnail of Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis

IEEE Access, 2021

In this paper, using calibrated TCAD simulations, we demonstrate how the performance of a Tunneli... more In this paper, using calibrated TCAD simulations, we demonstrate how the performance of a Tunneling FET (TFET) can be improved by using a new phenomenon called drain induced barrier widening (DIBW) at the source-channel junction. Our results indicate that TFETs in which DIBW dominates exhibit a steep subthreshold swing (≈35 mV/dec) and a low OFF-state current (≈10 −16 A/µm) without affecting the ON-state current. We also show that TFETs exhibit a reverse short channel effect due to an increase in the tunneling width at the source-channel junction. INDEX TERMS Drain induced barrier widening (DIBW), gate-on-drain overlap, OFF-state current, reverse short channel effects, subthreshold swing, TCAD simulation, tunnel field effect transistor (TFET).

Research paper thumbnail of Effect of Drain Induced Barrier Enhancement on Subthreshold Swing and OFF-state Current of Short Channel MOSFETs: A TCAD Study

IEEE Access, 2021

In this paper, with the help of calibrated 2-D simulations, we report a detailed study on the eff... more In this paper, with the help of calibrated 2-D simulations, we report a detailed study on the effect of drain induced barrier enhancement on the subthreshold swing and OFF-state current of a short channel MOSFET. We demonstrate that the presence of gate-on-drain overlap in a short channel MOSFET leads to drain induced barrier enhancement (DIBE). We show that as a result of DIBE, a MOSFET can achieve near ideal subthreshold swing, diminished DIBL, constant threshold voltage and improved I ON /I OFF ratio at room temperature, without being affected by channel length variations. INDEX TERMS Drain induced barrier enhancement (DIBE), Drain induced barrier lowering (DIBL), gate-on-drain overlap, leakage current, MOSFET, scaling, short channel effects (SCE), subthreshold swing, and threshold voltage.

Research paper thumbnail of Performance Investigation of Single Grain Boundary Junctionless Field Effect Transistor

IEEE Journal of the Electron Devices Society, 2016

In this paper, we report a single grain boundary (GB) junctionless thin film transistor (JLFET) o... more In this paper, we report a single grain boundary (GB) junctionless thin film transistor (JLFET) on recrystallized polycrystalline silicon (poly-Si JLFET). Using 2-D simulations, the electrical performance of the poly-Si JLFET is evaluated for different single GB locations in the channel. Without the need for creating the source and the drain regions by implantation, we demonstrate the prospect of achieving thin-film poly-Si JLFETs whose performance is reasonable for silicon film thicknesses less than 10 nm.

Research paper thumbnail of Dopingless tunnel FET with a hetero-material gate: Design and analysis

2014 IEEE 2nd International Conference on Emerging Electronics (ICEE), 2014

Research paper thumbnail of Dopingless PNPN tunnel FET with improved performance: Design and analysis

Superlattices and Microstructures, 2015

In this paper, we present a two-dimensional simulation study of a dopingless PNPN TFET with a het... more In this paper, we present a two-dimensional simulation study of a dopingless PNPN TFET with a hetero-gate dielectric. Using a dual-material-gate in a dopingless TFET, the energy band gap on the source side is modulated to create an N + source pocket. Our technique obviates the need to use ion implantation for the formation of the N + source pocket. The dopingless PNPN TFET with a hetero-gate dielectric is demonstrated to exhibit a superior performance in terms of ON-state current and subthreshold swing when compared to a conventional dopingless TFET. Our results may pave the way for realizing high performance dopingless TFETs using a low thermal budget required for low power and low cost applications.. Index Terms-Tunnel field effect transistor (TFET), PNPN TFET, tunneling, dopingless, hetero-gate-dielectric, N + source pocket.

Research paper thumbnail of Single Grain Boundary Tunnel Field Effect Transistors on Recrystallized Polycrystalline Silicon: Proposal and Investigation

IEEE Electron Device Letters, 2014

A single grain boundary tunnel field effect transistor (TFET) on recrystallized polycrystalline s... more A single grain boundary tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is reported in this letter. By varying the position of the grain boundary (GB) in the channel, the performance of the proposed device is evaluated using calibrated 2-D simulations. Our results show the possibility of realizing low-cost thin-film recrystallized polycrystalline tunnel FETs with low OFF-state current and low subthreshold swing compared with the thin-film transistors. By introducing the source N + pocket doping, it is also shown that the proposed single GB PNPN TFET exhibits enhanced ON-state current, making it suitable for low power display applications, including the driver circuits.