Deleep Nair - Profile on Academia.edu (original) (raw)

Papers by Deleep Nair

Silicon Photonic Wafer-Scale Yield of Single Mode Resonator with Broadband DBR Mirrors

Springer proceedings in physics, 2024

1D and 2D wide acoustic bandgap Phononic Crystal structures for performance improvement of AlN-on-Si resonators operating in GHz range

Design and simulation of Phononic Crystals (PnCs) with a wide Acoustic Band Gap (ABG) around 1 GH... more Design and simulation of Phononic Crystals (PnCs) with a wide Acoustic Band Gap (ABG) around 1 GHz is presented. A new PnC unit cell topology is designed, which has a very wide ABG of 138 MHz with center frequency around 1 GHz and minimum feature size of 0.6 μm. Wider ABG allows better enhancement of the Quality factor (Q) by reducing the anchor loss. Effect of geometrical variation and the periodicity of PnC are discussed. ABG for 1D and 2D periodicity is simulated and geometrical dimensions to obtain similar ABG in both cases are compared.

Design, fabrication and characterization of RF MEMS shunt switch for wideband operation of 3 GHz to 30 GHz

Journal of Micromechanics and Microengineering, Sep 18, 2019

Journal of microelectromechanical systems, Aug 1, 2017

The design, fabrication, and characterization of Piezoelectric-on-Silicon array resonators with a... more The design, fabrication, and characterization of Piezoelectric-on-Silicon array resonators with asymmetric Phononic crystal (PnC) tethering for applications in high frequency reference oscillators is presented. A hybrid approach of mechanical arraying along with higher mode of operation is used for minimizing the motional resistance. For improving the Q-factor, novel asymmetric PnC tethers are developed that not only exhibit a larger bandgap than their symmetric PnC counterparts, but also have significantly better design optimization capabilities for fine tuning the tether properties. Third order longitudinal mode resonators operating at frequencies of ˜300 MHz with and without PnC tethering and with different number of resonators in the array were fabricated using 2 μm SOI wafers. The measured characteristics of the resonators showed a peak unloaded Q-factor of 4454 and a motional resistance of 200 at 312 MHz for a seven resonator array. These results are comparable with the best reported in literature, in spite of a lesser silicon thickness. [2016-0194]

Wafer-Level Thin Film Encapsulation for RF MEMS Using SiN/SU-8 Membrane

2022 IEEE 9th Electronics System-Integration Technology Conference (ESTC), Sep 13, 2022

arXiv (Cornell University), Dec 11, 2019

We investigated the effect of material choice and orientation in limiting source to drain tunneli... more We investigated the effect of material choice and orientation in limiting source to drain tunneling (SDT) in nanowire (NW) p-MOSFETs. Si, Ge, GaSb, and Ge 0.96 Sn 0.04 nanowire MOSFETs (NWFETs) were simulated using rigorous ballistic quantum transport simulations. To properly account for the non-parabolicity and anisotropy of the valence band the k•p method was used. For each material, a set of six different transport/confinement directions were simulated to identify the direction with the highest ON-current (I ON ). For Ge, GaSb, and GeSn [001]/110/ 110 oriented NWFETs showed the best ON-state performance, compared to other orientations. Our simulation results show that, despite having a higher percentage of SDT in OFF-state than silicon, GaSb [001]/110/ 110 NWFET can outperform Si NWFETs. We further examined the role of doping in limiting SDT and demonstrated that the ON-state performance of Ge and GeSn NWFETs could be improved by reducing the doping in the source/drain (S/D) extension regions. Finally, we analyzed the impact of increased injection velocity in [001]/110/ 110 oriented GaSb and GeSn NWFETs, as a result of the application of uniaxial compressive stress, and showed that when compared at a fixed OFF-current (I OFF ) with unstrained NWFETs, uniaxial compressive stress deteriorates the ON-state performance due to an increase in OFF-state SDT current component.

IEEE Transactions on Device and Materials Reliability, Mar 1, 2004

Drain disturb is studied in NOR flash EEPROM cells under CHE and CHISEL programming operation, be... more Drain disturb is studied in NOR flash EEPROM cells under CHE and CHISEL programming operation, before and after repeated program/erase (P/E) cycling. Drain disturb is shown to originate from band-to-band tunneling under CHISEL operation, unlike under CHE operation where it originates from source-drain leakage. Under identical initial programming time, CHISEL operation always shows slightly lower program/ disturb (P/D) margin before cycling but similar P/D margin after repetitive P/E cycling when compared to CHE operation. The degradation of gate coupling coefficient that affects source/drain leakage and the increase in trap-assisted band-to-band tunneling seems to explain well the behavior of CHE and CHISEL drain disturb after cycling. Index Terms-Band-to-band tunneling, CHE, CHISEL, cycling endurance, drain disturb, flash EEPROM. I. INTRODUCTION N OR FLASH EEPROM cells are programmed either by channel hot electron (CHE) [1] or by CHannel Initiated Secondary ELectron (CHISEL) [2]-[14] injection mechanisms. CHE injection involves injection of lateral field heated channel electrons into the floating gate (FG). Note that the CHE process does not rely on impact ionization. On the other hand, CHISEL injection relies on impact ionization feedback and is activated by the application of a negative substrate bias that results in a high transverse field near the drain junction. This causes high-energy electron injection into the FG over a spatially broad area in the channel. The schematic of CHE and CHISEL injection is shown in Fig. 1. Compared to the CHE process, CHISEL injection provides faster programming time under equivalent programming power and lower voltage and lower power operation for equivalent. CHISEL injection also offers self-convergent programming leading to excellent threshold voltage control and a unique recovery procedure for over erased cells not available under conventional CHE programming [2]-[13]. CHISEL programming also shows better program/erase (P/E) cycling endurance of window and lower degradation compared to CHE operation [14], [15]. Most of the studies done so far were Manuscript

IEEE Transactions on Magnetics, Sep 1, 2019

A scalable, broadband, and physics-based compact model for on-chip spiral inductors with rectangu... more A scalable, broadband, and physics-based compact model for on-chip spiral inductors with rectangular outline shape is demonstrated for the first time in this paper. A simple dc inductance model is developed based on the current sheet approximation. The reduction in inductance due to the flow of eddy current in a back metal plate is considered using the method of images. A threeladder network is shown to be sufficient to accurately model skin effect caused due to the magnetic field setup at high frequencies. Geometry-dependent expression suitable for rectangular cross-sectional metal strips is presented to predict the proximity effect. Physics-based expression for the substrate capacitance is derived. The proposed model is also shown to have a good correlation in the presence of a patterned ground shield. The proposed model is verified across CMOS process parameters that affect the inductor performance, such as metal thickness, substrate resistivity, and substrate thickness. Furthermore, model accuracy is also validated across design parameters such as spiral width, spacing between turns, number of turns, and diameter. The model is shown to have a good agreement with both EM simulations and measurements.

Performance Evaluation of Germanium-Tin Nanowire PFETs: Impact of Mole Fraction, Orientation and Doping

Materials with a light effective mass and high mobility are known to provide better performance f... more Materials with a light effective mass and high mobility are known to provide better performance for long channel transistors. However, with transistor dimensions scaling to sub-10 nm lengths, source to drain tunneling (SDT) becomes a major performance limiting factor for high mobility materials. In this paper, we examine the effect of SDT on the performance of germanium-tin (GeSn) short channel Nanowire (NW) p-MOSEFTs using rigorous ballistic quantum transport simulations. We simulate GeSn NWs in different transport orientations and with Sn mole fraction values of 0.05 and 0.11 to identify the channel direction with optimum effective mass to limit SDT. We also examine the role of reduced source/drain doping in enhancing the on-state performance of GeSn NWs by limiting SDT current in off-state.

IEEE Transactions on Electron Devices, Apr 1, 2005

The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channe... more The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channel hot electron (CHE) and channel-initiated secondary electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and fullband Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in source/drain leakage, reduction in band-to-band tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling. Index Terms-Band-to-band tunneling (BTBT), channel hot electron (CHE), device scaling, drain disturb, channel-initiated secondary electron (CHISEL), Flash EEPROMs, hot carriers.

Impact of Source/Drain Underlap on the Ballistic Performance of Silicon and Germanium-Tin Nanowire p-MOSFETs

We investigate the effectiveness of source/drain (S/D) underlap regions in limiting the source to... more We investigate the effectiveness of source/drain (S/D) underlap regions in limiting the source to drain tunneling (SDT) current in Si and Ge0.96Sn0.04nanowire MOSFETs (NWFETs), using rigorous ballistic quantum transport simulations. Our simulation results indicate that with a carefully chosen length of S/D underlap regions, GeSn p-NWFETs can outperform Si p-NWFETs, despite having a higher component of SDT current in OFF-state.

A novel FinFET with dynamic threshold voltage

Higher on-current (Idsat) and lower off-current (Ioff</sub&g... more Higher on-current (Idsat) and lower off-current (Ioff) can be achieved through dynamic threshold voltage (Vth) in MOSFETs. The change in Vth with gate bias is usually achieved through the body effect by connecting the gate terminal to the substrate in MOSFETs with heavily doped substrates. In this paper, we report the presence of dynamic Vth even in FinFETs with undoped channels. In this case, the change in Vth is due to modulation of the cross-sectional area of current flow. For the same Ioff, more than 10% increase in Idsat can be achieved in the proposed structure.

High-K/Metal Gate MOSFETs における新しいレイアウト依存性

SIAM International Conference on Data Mining, Jan 20, 2012

Analysis of systematic and random variation of gate-induced drain leakage in silicon-germanium channel pFET

Variability in the transistor parameters play a significant role in CMOS scaling to nanometer fea... more Variability in the transistor parameters play a significant role in CMOS scaling to nanometer feature sizes. New channel materials such as silicon-germanium for pFET at 32nm and beyond are useful because of higher mobility and lower threshold voltage. However, gate-induced drain leakage (GIDL) is dominant in the total leakage and the use of germanium (Ge) may introduce additional variability sources. In this work, pre-halo Ge pre-amorphization impant (PAI) effect on systematic and random variability of GIDL and its reduction is investigated. We report that the elimination of Ge PAI from the process flow reduces GIDL and the effect of systematic variations but increases the static random GIDL variations in planar transistors based on high-k metal gate technology. However, the random GIDL variation difference associated with Ge PAI may change for scaled supply voltages.

Characterization and Analysis of Random Telegraph Noise in Scaled SiGe Channel HKMG pMOSFETs

IEEE Transactions on Electron Devices, Feb 1, 2022

Here for the first time, we report on the characterization and analysis of random telegraph noise... more Here for the first time, we report on the characterization and analysis of random telegraph noise (RTN) in silicon-germanium (SiGe) channel pMOSFETs without a silicon-cap layer. A detailed analysis of traps causing two-level RTN is presented. The trap parameters and RTN magnitude are computed. It was observed that the impact of RTN is similar when compared with silicon channel pFETs from a similar process node with a comparable <inline-formula> <tex-math notation="LaTeX">${T}_{\text{inv}}$ </tex-math></inline-formula>.

Extraction of D31 Piezoelectric Coefficient of AlN Thin Film

Piezoelectric materials have the property of electromechanical coupling, which is very useful in ... more Piezoelectric materials have the property of electromechanical coupling, which is very useful in Micro Electro Mechanical Systems (MEMS). Aluminium Nitride (AlN) thin film is an ideal candidate for resonators in on-chip front end circuit. The piezoelectric coupling coefficient d31 is responsible for the excitation in longitudinal mode resonators. Direct measurement of the value of d31 is still an area of research. We propose a method to extract the piezoelectric coefficient d31 from the transmission characteristics of a resonator. The average extracted value of d31 is -0.943 pC/N with standard deviation 0.21 pC/N, which is comparable with reported values.

Modeling of rectangular on-chip spiral inductors

A simple expression for calculating DC inductance of a rectangular spiral inductor is presented. ... more A simple expression for calculating DC inductance of a rectangular spiral inductor is presented. Accuracy of the expression is evaluated using field solver simulations. We have presented a broad-band frequency independent model.

Design of a Piezoresistive MEMS Resonator Operating Beyond 1 GHz

Environmental science and engineering, 2014

This paper focuses on design of Piezoresistive MEMS resonator for operation beyond 1 GHz, using F... more This paper focuses on design of Piezoresistive MEMS resonator for operation beyond 1 GHz, using FEM simulations. A method for simulation of transconductance of MEMS resonator is presented for first time. Lateral bulk acoustic mode of Twin beam resonator is simulated using the proposed method to get transconductance-frequency plot. Dimensions of the structure are optimized for best operation near 1.3 GHz. Design aspects of resonator including biasing effects, damping effects and anchoring variations are studied.

Compact Modeling of Series Stacked Tapered Spiral Inductors

In this paper for the first time, a frequency independent equivalent circuit model is proposed fo... more In this paper for the first time, a frequency independent equivalent circuit model is proposed for series stacked inductors having variable width and space (taper) across their turns. The proposed model accounts for the increase in mutual inductance between the stacked spirals due to taper. Also, the proximity effect losses with tapered top and bottom spirals of the series stack is accurately modeled. Finally, the inter-layer capacitance between the stacked spirals which dictates the self-resonant-frequency of the series inductor is calculated across different values of taper. EM simulations and measurements show excellent correlation with model simulations across different layouts with different values of taper thereby demonstrating the scalability of the proposed model.

Design and fabrication of 1 GHz lateral TPoS MEMS resonator for RF front end applications

This paper reports on design, fabrication and characterization of laterally excited thin film pie... more This paper reports on design, fabrication and characterization of laterally excited thin film piezoelectric on Silicon (TPoS) MEMS resonators of resonance frequency around 1 GHz. Devices were fabricated on 5 μm SOI and 0.5 μm Aluminium Nitride piezoelectric film. We studied the effect of the number of anchors attached to the resonator and the width of the resonator on Q-factor and motional resistance. Measured characteristics of the device with Phononic crystal (PnC) tether showed a resonance peak at 969.22 MHz with motional resistance 2.9 kΩ and Q-factor of 1998. The motional resistance could be reduced to 770 Ω for wider devices.