Dr Kavita Khare - Academia.edu (original) (raw)
Papers by Dr Kavita Khare
2016 6th International Conference - Cloud System and Big Data Engineering (Confluence), 2016
Leakage power consumption is a major contribution of total power dissipation in Deep Sub-Micron (... more Leakage power consumption is a major contribution of total power dissipation in Deep Sub-Micron (DSM) technology for CMOS circuit design. In this paper we have proposed a Novel circuit technique known as “Sleepy LECTOR” which mitigates various type of leakage current in DSM regime. In proposed technique we insert p-type sleep transistor above pull up network, and n-type sleep transistor below pull down network, which rail of from Vdd to GND for reduction of leakage power. Another Leakage controlled transistor (LCTs) PMOS and NMOS inserted between pull up and pull down network, these transistors are always near cut OFF voltage which increases the path resistance from supply to ground reducing leakage power, it is self controlling transistor. Lector transistors produce the stacking effect and producing high resistance path from Vdd to ground. By using Sleep transistors we can turn off the circuit by rail from power supply (Vdd) during standby mode for reduction of leakage power. The proposed circuit technique reduces the Power with respect to basic NAND gate 37.69%, 83.93%, N AND gate with sleep 79.15%, 86.69%, NAND gate with Lector 36.79%, 12.05% respectively in 65nm and 45nm Process Technology.
Rising complexity of VLSI designs & IC process technologies increases mismatch between design and... more Rising complexity of VLSI designs & IC process technologies increases mismatch between design and manufacturing. The resemblance between a circuit fabricated on the wafer and as designed in the layout tool grows weaker. Process variations, fabrication defects, etc. form new cost (turnaround time, productivity) bottlenecks as we enter the era of nanometer-scale VLSI. This motivates research to enhance the predictability and yield of VLSI manufacturing, as well as design technology means of overcoming process variations and lithographic errors. A CMP and other manufacturing steps in deep submicron VLSI have varying effects on the device and interconnect features, depending on local characteristics of the layout. To improve manufacturability and performance predictability & to make a layout uniform with respect to prescribed density criteria, insertion of “dummy fill" geometries into the layout is done. Full chip dummy fill is an iterative process,time-consuming and increases the ...
IEEE Access, 2021
This paper presents a sample rate conversion filter for decimation with flat passband. The propos... more This paper presents a sample rate conversion filter for decimation with flat passband. The proposed linear programming optimization (LPO) technique improves the magnitude response of filter with least computational complexity. Computational complexity has been a major factor in selection of decimation filter. Simulation results indicate that the proposed filter shows passband droop less than 0.007 dB with 50.5% decrease in computational complexity. The proposed filter eliminates the need of compensator. INDEX TERMS Sample rate conversion, FIR filter, optimization, passband.
2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE), 2017
This work exhibits a very less area possessed negative charge pump (NCP) solution for an on-chip ... more This work exhibits a very less area possessed negative charge pump (NCP) solution for an on-chip localized body bias generator (BBG) with very nearly zero settling time for use in critical path replicas clearance in addition process and voltage compensation and dynamic energy optimization. The negative voltage generator is executed with 28nm Ultra Thin Body and Box Fully Depleted Silicon On Insulator (UTBB FDSOI) for 0.85–1.3V inputs. Its area occupancy is 2.94 μm2 and power occupancy is 34μW. It supports the body bias generator to having very less area so body bias generator can be sprinkled with standard cells to enhance performance and robustness of the design.
Next-generation SONET/SDH technologies namely, Generic Framing Procedure (GFP), Virtual Concatena... more Next-generation SONET/SDH technologies namely, Generic Framing Procedure (GFP), Virtual Concatenation (VCAT) and Link Capacity Adjustment Scheme (LCAS) enable network operators to provide integrated data and voice services over their legacy SONET/SDH infrastructure to generate new revenue. Data packets are encapsulated using framing protocols GFP. VCAT is a process of distributing the GFP framed data payload in number of virtual channels of same capacity forming a Virtually Concatenated Group (VCG). LCAS is used for dynamic bandwidth allocation. Individual member of VCG can traverse through any path to reach the destination and all VCs are combined at the destination as per the MFI (Multiframe Indicator) and Sequence Number written in the control packet of the SDH frame. As all the VCG members are routed independently, they do not reach the destination at the same time. These streams thus incur differential delay. Buffers are provided at the receiver to compensate differential delay...
2015 International Conference on Industrial Instrumentation and Control (ICIC), 2015
In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentag... more In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap for Semiconductor (ITRS). Here a wide-ranging survey and analysis has been done for leakage reduction based on active as well as idle mode of operation. This paper proposes a novel approach, based on run time leakage reduction, where a logic gate having Worst Leakage State (WLS) is replaced by some variation of standard logic cell having minimum leakage with the same input vector. For this purpose oxide thickness (Tox) of standard logic cell is increased to 2nm which highly reduces the leakage current and simultaneously increase in the W/L ratio of transistor for zero delay penalties due to gate replacement of the circuit is done. Proposed approach is based on gate replacement technique for reducing leakage without technology modification of IC. The Proposed approach achieves 88.39%...
International Journal of Scientific & Technology Research, 2019
Network-on-Chip is an emerging paradigm for integrating very high number of Intellectual Property... more Network-on-Chip is an emerging paradigm for integrating very high number of Intellectual Property blocks on a single Integrated Chip. Crossbar switch is one of the important parts of NoC. In this paper, 2x1 MUX are used instead of existing crossbar design with 4x1 MUX, to meet the requirement of high speed networks. The proposed design reduces area by 40% and delay by 7.14 % as compared to 2-D cross bar switch as well as conventional crossbar switch. The functional verification and synthesis of proposed cross bar switch design is done by using Xilinx ISE 9.2i
Emerging Research in Computing, Information, Communication and Applications, 2015
In Deep Sub-Micron (DSM) technology, leakage power is becoming the primary consideration, as it d... more In Deep Sub-Micron (DSM) technology, leakage power is becoming the primary consideration, as it decreases battery life for the entire portable battery operated device such as mobile phones, laptop and cam coder etc. Major design constraints are always area, power and delay in Very Large Scale of Integration (VLSI) circuits. To reduce the leakage power losses several techniques has been proposed that proficiently reduces leakage power dissipation. This paper proposes an integrated approach, based on Input Vector Control (IVC) with Auxiliary Logic Switch (ALS) applied on the circuit. Here ALS is the variant of conventional logic gate, which replaces the gates are in their Worst Leakage State (WLS). Firstly IVC is applied on the given circuit for finding the Minimum Leakage Vector (MLV) secondly ALS is applied for the particular MLV and achieves 52.6 % reduction in leakage power on a contrary of 18 % leakage reduction if only IVC is applied. Proposed technique is simulated for static CMOS circuit (i.e. 1 bit Adder) using HSPICE simulator with 65 nm technology file provided by BPTM. Circuit parameters such as dynamic power, leakage power, delay and area form the basis for the evaluation. The result of the analysis clearly shows a tradeoff between leakage power and other circuit performances parameters. Hence a designer or a Computer Aided Design (CAD) tool would be able to select the suitable leakage minimization technique as per their requirement.
Circuit World, 2020
Purpose This paper is an unprecedented effort to resolve the performance issue of very large scal... more Purpose This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 9...
Journal of Nanoelectronics and Optoelectronics, 2018
International Journal of Engineering and Advanced Technology, 2019
Video compression is a very complex and time consuming task which generally pursuit high performa... more Video compression is a very complex and time consuming task which generally pursuit high performance. Motion Estimation (ME) process in any video encoder is responsible to primarily achieve the colossal performance which contributes to significant compression gain. Summation of Absolute Difference (SAD) is widely applied as distortion metric for ME process. With the increase in block size to 64×64 for real time applications along with the introduction of asymmetric mode motion partitioning(AMP) in High Efficiency Video Encoding (HEVC)causes variable block size motion estimation very convoluted. This results in increase in computational time and demands for significant requirement of hardware resources. In this paper parallel SAD hardware circuit for ME process in HEVC is propound where parallelism is used at various levels. The propound circuit has been implemented using Xilinx Virtex-5 FPGA for XC5VLX20T family. Synthesis results shows that the propound circuit provides significant...
International Journal of VLSI Design & Communication Systems, 2014
A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gat... more A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI circuit has become a major constrain in a battery operated device for technology node below 90nm, as it drains the battery even when a circuit is in standby mode. Major concern is the leakage even in run time condition, here aim is to focus on run time leakage reduction technique of integrated Circuit. It is inherited by stacking effect when the series transistors are maximized in OFF state condition. This method is independent of process technology and does not require any additional power supply. This paper gives an optimized solution of input pattern determination of some small circuit to find minimum leakage vector considering promising and non-promising node which helps to reduce the time complexity of the algorithm. Proposed algorithm is simulated using HSPICE simulator for 2 input NAND gate and different standard logic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell and different logics respectively.
A power efficient flip flop dissipates very less power as compared to normal flip flops. In this ... more A power efficient flip flop dissipates very less power as compared to normal flip flops. In this paper different power efficient flip-flops with different specific features are compared. A specified category of power efficient flip-flops known as the Dual Edge Triggered flip-flops are also considered in this comparison. The Dual Edge Triggered flip-flops responses to both positive and negative edge of clock. Hence this flip-flop can significantly reduce the clock related power. In this article, we compare several published implementations of power efficient flip-flops for performance & power consumption.
International Journal of Computer Applications, 2015
Data security is the major point of concern in today's internet communication system for which cr... more Data security is the major point of concern in today's internet communication system for which cryptography plays a vital role. Modular multiplier plays a key role in modern cryptography system. Galois field arithmetic is being popularly used in such applications. Montgomery multiplication is the method for boosting up the speed of modular multiplication. Montgomery modular multiplier is implemented for larger operand size to design encryption and decryption algorithm for RSA security system. This paper contributes to the implementation of modular multiplier using Montgomery algorithm for RSA encryption and decryption ,where existing architecture is implemented using carry select adder and modified carry select adder and it is concluded that later uses 23% less area and approximate 4.5% less output delay as compared to former, in VHDL using Xilinx ISE 9.2i and has been simulated on FPGA device spartan3, xc3s200-5ft256.
International Journal of Computer Applications, 2013
A wideband patch loaded dielectric resonator antenna (DRA) is discussed here. The rectangular rin... more A wideband patch loaded dielectric resonator antenna (DRA) is discussed here. The rectangular ring shaped slot coupling is used to excite the proposed antenna. In this paper, rectangular ring shaped slot coupled DRA and patch loaded DRA is studied and compared. The combined effect of patch radiator with rectangular ring shaped slot coupled DRA, on the return loss is observed. Simulation is done using Ansoft HFSS which is based on finite element method. Simple DRA resonates at two frequencies centered at 2.25 GHz having return loss of-14.41 db and 4.61GHz with a return loss of-19.29db; The patch loaded DRA shows resonance at frequencies centered around 2.19GHz having return loss of-32.3db and 4.4GHz with a return loss of-29.18db.The patch loaded DRA is based on the multi resonance technique that combines the resonance of slot coupled dielectric resonator and micro strip patch antenna. The bandwidth achieved for simple DRA is 26.8 % while patch loaded DRA offers 44.1 %.As the patch loaded DRA has larger bandwidth, may be used for wideband WLAN applications like WiFi, Bluetooth, Wimax etc.
International Journal of Recent Technology and Engineering (IJRTE), 2019
Motion Estimation(ME) operationinvolves predicting the frames and identifying motion vectors soth... more Motion Estimation(ME) operationinvolves predicting the frames and identifying motion vectors sothat redundancy can be exploited by eliminating the transfer ofsimilar information between successive frames.The most efficientand simple technique to estimate the motion vectors is Summation ofAbsolute Difference(SAD) where comparator forms one of an elemental component in SAD computation.This paper proposes two different comparator designs where propoundcircuit I is based on efficient look ahead comparator andpropound circuit II uses alteredone’s complement and conditional sum adder method. Results shows that propound circuit I reduces delay by 23%but with 16% increase in number of slice LUTs whereas the propoundcircuit II reduces delay by 11% and gives 33% reduction in number of slice LUTsas compared to traditional circuit. The propound hardwarecircuits are implemented on Virtex 7 FPGA and synthesized using Verilog as HDL language on Xilinx ISE 14.2.
2022 5th International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT)
Journal of Nanoelectronics and Optoelectronics, 2018
This paper presents a novel Neural Classifier using FGMOS (Floating Gate MOSFET). Basic reason fo... more This paper presents a novel Neural Classifier using FGMOS (Floating Gate MOSFET). Basic reason for using FGMOS in Neural Classifier instead of classical MOSFET based Neural Classifier is to get significant reduction in area and power. Additional advantage of FGMOS based Neural Classifier is the simple circuitry as compared to classical MOSFET based Neural Classifier. 51.037% reduction in area is achieved in FGMOS based Neural Classifier (in .12µm technology). Along with this Neural classifier, 100 synapse and 10 Neurons reconfigurable network also implemented.
2016 6th International Conference - Cloud System and Big Data Engineering (Confluence), 2016
Leakage power consumption is a major contribution of total power dissipation in Deep Sub-Micron (... more Leakage power consumption is a major contribution of total power dissipation in Deep Sub-Micron (DSM) technology for CMOS circuit design. In this paper we have proposed a Novel circuit technique known as “Sleepy LECTOR” which mitigates various type of leakage current in DSM regime. In proposed technique we insert p-type sleep transistor above pull up network, and n-type sleep transistor below pull down network, which rail of from Vdd to GND for reduction of leakage power. Another Leakage controlled transistor (LCTs) PMOS and NMOS inserted between pull up and pull down network, these transistors are always near cut OFF voltage which increases the path resistance from supply to ground reducing leakage power, it is self controlling transistor. Lector transistors produce the stacking effect and producing high resistance path from Vdd to ground. By using Sleep transistors we can turn off the circuit by rail from power supply (Vdd) during standby mode for reduction of leakage power. The proposed circuit technique reduces the Power with respect to basic NAND gate 37.69%, 83.93%, N AND gate with sleep 79.15%, 86.69%, NAND gate with Lector 36.79%, 12.05% respectively in 65nm and 45nm Process Technology.
Rising complexity of VLSI designs & IC process technologies increases mismatch between design and... more Rising complexity of VLSI designs & IC process technologies increases mismatch between design and manufacturing. The resemblance between a circuit fabricated on the wafer and as designed in the layout tool grows weaker. Process variations, fabrication defects, etc. form new cost (turnaround time, productivity) bottlenecks as we enter the era of nanometer-scale VLSI. This motivates research to enhance the predictability and yield of VLSI manufacturing, as well as design technology means of overcoming process variations and lithographic errors. A CMP and other manufacturing steps in deep submicron VLSI have varying effects on the device and interconnect features, depending on local characteristics of the layout. To improve manufacturability and performance predictability & to make a layout uniform with respect to prescribed density criteria, insertion of “dummy fill" geometries into the layout is done. Full chip dummy fill is an iterative process,time-consuming and increases the ...
IEEE Access, 2021
This paper presents a sample rate conversion filter for decimation with flat passband. The propos... more This paper presents a sample rate conversion filter for decimation with flat passband. The proposed linear programming optimization (LPO) technique improves the magnitude response of filter with least computational complexity. Computational complexity has been a major factor in selection of decimation filter. Simulation results indicate that the proposed filter shows passband droop less than 0.007 dB with 50.5% decrease in computational complexity. The proposed filter eliminates the need of compensator. INDEX TERMS Sample rate conversion, FIR filter, optimization, passband.
2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE), 2017
This work exhibits a very less area possessed negative charge pump (NCP) solution for an on-chip ... more This work exhibits a very less area possessed negative charge pump (NCP) solution for an on-chip localized body bias generator (BBG) with very nearly zero settling time for use in critical path replicas clearance in addition process and voltage compensation and dynamic energy optimization. The negative voltage generator is executed with 28nm Ultra Thin Body and Box Fully Depleted Silicon On Insulator (UTBB FDSOI) for 0.85–1.3V inputs. Its area occupancy is 2.94 μm2 and power occupancy is 34μW. It supports the body bias generator to having very less area so body bias generator can be sprinkled with standard cells to enhance performance and robustness of the design.
Next-generation SONET/SDH technologies namely, Generic Framing Procedure (GFP), Virtual Concatena... more Next-generation SONET/SDH technologies namely, Generic Framing Procedure (GFP), Virtual Concatenation (VCAT) and Link Capacity Adjustment Scheme (LCAS) enable network operators to provide integrated data and voice services over their legacy SONET/SDH infrastructure to generate new revenue. Data packets are encapsulated using framing protocols GFP. VCAT is a process of distributing the GFP framed data payload in number of virtual channels of same capacity forming a Virtually Concatenated Group (VCG). LCAS is used for dynamic bandwidth allocation. Individual member of VCG can traverse through any path to reach the destination and all VCs are combined at the destination as per the MFI (Multiframe Indicator) and Sequence Number written in the control packet of the SDH frame. As all the VCG members are routed independently, they do not reach the destination at the same time. These streams thus incur differential delay. Buffers are provided at the receiver to compensate differential delay...
2015 International Conference on Industrial Instrumentation and Control (ICIC), 2015
In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentag... more In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap for Semiconductor (ITRS). Here a wide-ranging survey and analysis has been done for leakage reduction based on active as well as idle mode of operation. This paper proposes a novel approach, based on run time leakage reduction, where a logic gate having Worst Leakage State (WLS) is replaced by some variation of standard logic cell having minimum leakage with the same input vector. For this purpose oxide thickness (Tox) of standard logic cell is increased to 2nm which highly reduces the leakage current and simultaneously increase in the W/L ratio of transistor for zero delay penalties due to gate replacement of the circuit is done. Proposed approach is based on gate replacement technique for reducing leakage without technology modification of IC. The Proposed approach achieves 88.39%...
International Journal of Scientific & Technology Research, 2019
Network-on-Chip is an emerging paradigm for integrating very high number of Intellectual Property... more Network-on-Chip is an emerging paradigm for integrating very high number of Intellectual Property blocks on a single Integrated Chip. Crossbar switch is one of the important parts of NoC. In this paper, 2x1 MUX are used instead of existing crossbar design with 4x1 MUX, to meet the requirement of high speed networks. The proposed design reduces area by 40% and delay by 7.14 % as compared to 2-D cross bar switch as well as conventional crossbar switch. The functional verification and synthesis of proposed cross bar switch design is done by using Xilinx ISE 9.2i
Emerging Research in Computing, Information, Communication and Applications, 2015
In Deep Sub-Micron (DSM) technology, leakage power is becoming the primary consideration, as it d... more In Deep Sub-Micron (DSM) technology, leakage power is becoming the primary consideration, as it decreases battery life for the entire portable battery operated device such as mobile phones, laptop and cam coder etc. Major design constraints are always area, power and delay in Very Large Scale of Integration (VLSI) circuits. To reduce the leakage power losses several techniques has been proposed that proficiently reduces leakage power dissipation. This paper proposes an integrated approach, based on Input Vector Control (IVC) with Auxiliary Logic Switch (ALS) applied on the circuit. Here ALS is the variant of conventional logic gate, which replaces the gates are in their Worst Leakage State (WLS). Firstly IVC is applied on the given circuit for finding the Minimum Leakage Vector (MLV) secondly ALS is applied for the particular MLV and achieves 52.6 % reduction in leakage power on a contrary of 18 % leakage reduction if only IVC is applied. Proposed technique is simulated for static CMOS circuit (i.e. 1 bit Adder) using HSPICE simulator with 65 nm technology file provided by BPTM. Circuit parameters such as dynamic power, leakage power, delay and area form the basis for the evaluation. The result of the analysis clearly shows a tradeoff between leakage power and other circuit performances parameters. Hence a designer or a Computer Aided Design (CAD) tool would be able to select the suitable leakage minimization technique as per their requirement.
Circuit World, 2020
Purpose This paper is an unprecedented effort to resolve the performance issue of very large scal... more Purpose This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 9...
Journal of Nanoelectronics and Optoelectronics, 2018
International Journal of Engineering and Advanced Technology, 2019
Video compression is a very complex and time consuming task which generally pursuit high performa... more Video compression is a very complex and time consuming task which generally pursuit high performance. Motion Estimation (ME) process in any video encoder is responsible to primarily achieve the colossal performance which contributes to significant compression gain. Summation of Absolute Difference (SAD) is widely applied as distortion metric for ME process. With the increase in block size to 64×64 for real time applications along with the introduction of asymmetric mode motion partitioning(AMP) in High Efficiency Video Encoding (HEVC)causes variable block size motion estimation very convoluted. This results in increase in computational time and demands for significant requirement of hardware resources. In this paper parallel SAD hardware circuit for ME process in HEVC is propound where parallelism is used at various levels. The propound circuit has been implemented using Xilinx Virtex-5 FPGA for XC5VLX20T family. Synthesis results shows that the propound circuit provides significant...
International Journal of VLSI Design & Communication Systems, 2014
A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gat... more A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI circuit has become a major constrain in a battery operated device for technology node below 90nm, as it drains the battery even when a circuit is in standby mode. Major concern is the leakage even in run time condition, here aim is to focus on run time leakage reduction technique of integrated Circuit. It is inherited by stacking effect when the series transistors are maximized in OFF state condition. This method is independent of process technology and does not require any additional power supply. This paper gives an optimized solution of input pattern determination of some small circuit to find minimum leakage vector considering promising and non-promising node which helps to reduce the time complexity of the algorithm. Proposed algorithm is simulated using HSPICE simulator for 2 input NAND gate and different standard logic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell and different logics respectively.
A power efficient flip flop dissipates very less power as compared to normal flip flops. In this ... more A power efficient flip flop dissipates very less power as compared to normal flip flops. In this paper different power efficient flip-flops with different specific features are compared. A specified category of power efficient flip-flops known as the Dual Edge Triggered flip-flops are also considered in this comparison. The Dual Edge Triggered flip-flops responses to both positive and negative edge of clock. Hence this flip-flop can significantly reduce the clock related power. In this article, we compare several published implementations of power efficient flip-flops for performance & power consumption.
International Journal of Computer Applications, 2015
Data security is the major point of concern in today's internet communication system for which cr... more Data security is the major point of concern in today's internet communication system for which cryptography plays a vital role. Modular multiplier plays a key role in modern cryptography system. Galois field arithmetic is being popularly used in such applications. Montgomery multiplication is the method for boosting up the speed of modular multiplication. Montgomery modular multiplier is implemented for larger operand size to design encryption and decryption algorithm for RSA security system. This paper contributes to the implementation of modular multiplier using Montgomery algorithm for RSA encryption and decryption ,where existing architecture is implemented using carry select adder and modified carry select adder and it is concluded that later uses 23% less area and approximate 4.5% less output delay as compared to former, in VHDL using Xilinx ISE 9.2i and has been simulated on FPGA device spartan3, xc3s200-5ft256.
International Journal of Computer Applications, 2013
A wideband patch loaded dielectric resonator antenna (DRA) is discussed here. The rectangular rin... more A wideband patch loaded dielectric resonator antenna (DRA) is discussed here. The rectangular ring shaped slot coupling is used to excite the proposed antenna. In this paper, rectangular ring shaped slot coupled DRA and patch loaded DRA is studied and compared. The combined effect of patch radiator with rectangular ring shaped slot coupled DRA, on the return loss is observed. Simulation is done using Ansoft HFSS which is based on finite element method. Simple DRA resonates at two frequencies centered at 2.25 GHz having return loss of-14.41 db and 4.61GHz with a return loss of-19.29db; The patch loaded DRA shows resonance at frequencies centered around 2.19GHz having return loss of-32.3db and 4.4GHz with a return loss of-29.18db.The patch loaded DRA is based on the multi resonance technique that combines the resonance of slot coupled dielectric resonator and micro strip patch antenna. The bandwidth achieved for simple DRA is 26.8 % while patch loaded DRA offers 44.1 %.As the patch loaded DRA has larger bandwidth, may be used for wideband WLAN applications like WiFi, Bluetooth, Wimax etc.
International Journal of Recent Technology and Engineering (IJRTE), 2019
Motion Estimation(ME) operationinvolves predicting the frames and identifying motion vectors soth... more Motion Estimation(ME) operationinvolves predicting the frames and identifying motion vectors sothat redundancy can be exploited by eliminating the transfer ofsimilar information between successive frames.The most efficientand simple technique to estimate the motion vectors is Summation ofAbsolute Difference(SAD) where comparator forms one of an elemental component in SAD computation.This paper proposes two different comparator designs where propoundcircuit I is based on efficient look ahead comparator andpropound circuit II uses alteredone’s complement and conditional sum adder method. Results shows that propound circuit I reduces delay by 23%but with 16% increase in number of slice LUTs whereas the propoundcircuit II reduces delay by 11% and gives 33% reduction in number of slice LUTsas compared to traditional circuit. The propound hardwarecircuits are implemented on Virtex 7 FPGA and synthesized using Verilog as HDL language on Xilinx ISE 14.2.
2022 5th International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT)
Journal of Nanoelectronics and Optoelectronics, 2018
This paper presents a novel Neural Classifier using FGMOS (Floating Gate MOSFET). Basic reason fo... more This paper presents a novel Neural Classifier using FGMOS (Floating Gate MOSFET). Basic reason for using FGMOS in Neural Classifier instead of classical MOSFET based Neural Classifier is to get significant reduction in area and power. Additional advantage of FGMOS based Neural Classifier is the simple circuitry as compared to classical MOSFET based Neural Classifier. 51.037% reduction in area is achieved in FGMOS based Neural Classifier (in .12µm technology). Along with this Neural classifier, 100 synapse and 10 Neurons reconfigurable network also implemented.