El-bay Bourennane - Academia.edu (original) (raw)

Papers by El-bay Bourennane

Engineering, Technology & Applied Science Research, Apr 2, 2023

An Unmanned Aerial Vehicle (UAV) network specifies a novel type of Mobile Ad hoc Network (MANET) ... more An Unmanned Aerial Vehicle (UAV) network specifies a novel type of Mobile Ad hoc Network (MANET) in which drones serve as nodes and facilitate the retransmission of messages to their final destinations. Aside from its military application, it has recently begun to seep into the civilian sector. Similar to MANET and vehicular ad hoc networks, Flying Ad hoc Networks (FANET) are a subset of ad hoc networks. An FANET is different because it is founded on UAVs. Due to the characteristics of this sort of network, which is defined by a highly changing topology in a 3D environment, we must employ an adjusted configuration method to ensure good routing performance. Therefore, to deal with this problem, a technique that responds to any change in topology by always finding the best route is required. In this work, we propose a new protocol based on the hybrid optimization of the 2-opt heuristic and Honey Badger Algorithm (HBA), called HB-AODV. In order to locate its prey, a badger must move slowly and continuously while using scent markers and mouse-digging skills to catch it. In other words, the most efficient routes in terms of the number of hops are identified. Several simulations were conducted via the 3D version of Network Simulator (NS-2) on different deployment strategies. In comparison to AODV, DSDV, and AntHocNet, the obtained results demonstrated the proposed scheme's good performance in terms of quality of service metrics.

HAL (Le Centre pour la Communication Scientifique Directe), 2018

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering)

Introduction: The 3D integrated circuit technology, which smooths out the massive increase in tra... more Introduction: The 3D integrated circuit technology, which smooths out the massive increase in transistors on a chip by stacking numerous silicon layers vertically, is quickly becoming a revolutionary technology. Thermal issues are more relevant for 3D Network-on-Chip (NoC) systems than their 2D counterparts. Methods: This paper presents a novel Vertically-Partially-Connected 3D-Network on-chip architecture that reduces the total length of interconnects and reduces the number of 3D routers. We also present an efficient XYZ routing technique for thermal management. The proposed algorithm distributes traffic based on the number of layers and congestion to achieve chip heat balancing, avoid high peak temperatures, improve average packet latency, and extend chip service life. Results: Simulation results showed that the routing technique reduces the peak temperature of the chip by an average of 17 °C compared to the exiting routing algorithms, with minimized negative impact on performance...

2020 IEEE 23rd International Multitopic Conference (INMIC), 2020

Integration of FPGAs in datacenters might have different motivations from acceleration to energy ... more Integration of FPGAs in datacenters might have different motivations from acceleration to energy efficiency, but the goal of better performance tops all. FPGAs are being utilized in a variety of ways today, tightly coupled with heterogenous computing resources, and as a standalone network of homogenous resources. Open source software stacks, propriety tool chain, and programming languages with advanced methodologies are hitting hard on the programmability wall of the FPGAs. The deployment of FPGAs in datacenters will neither be sustainable nor economical, without realizing the multi-tenancy in multiple FPGAs. Inter-FPGA communication among multiple FPGAs remained relatively less addressed problem this area. In this proposed study, we made a theoretical case as a potential solution for this bottleneck problem to realize multi-tenant multi-FPGAs in datacenters. The proposed scheme poses a challenge as well as an opportunity for the scientific community to contribute.

020 1st International Conference on Communications, Control Systems and Signal Processing (CCSSP), 2020

Hardware implementation is necessary and important for several applications and in the case of vi... more Hardware implementation is necessary and important for several applications and in the case of video encoders and that in order to ensure real time processing. The integration of these applications into a SoC, based on one or more processor, is one of proposed solutions. The use of a SoC implies the utilization of adequate communication system. The Network-on-Chip is the new communication system proposed for new applications. In addition to the technical characteristics of NoC, the mapping problem is one of important problems that influence on the global characteristics of the application. This work presents a mapping methodology based on genetic algorithms proposed especially for mapping IP cores of the H264 encoder onto mesh-NoC tiles. The main objective is to minimize the total network power of the implemented application. Simulation results confirm that the proposed model is very efficient and optimized the video encoder application in both of the time and energy side.

The research work described here is partial work which is done with ESRG TEAM of the ALGORITHMI C... more The research work described here is partial work which is done with ESRG TEAM of the ALGORITHMI CENTRO in the University of Minho under the guidance of Pr. Jorge CABRAL in collaboration with Tiago Gomes and DR. Reza Abrishambaf at The University of Minho, Guimaraes. I am very thankful for them support.

Journal of Parallel and Distributed Computing, 2018

In this paper, we present a Model Driven Engineering (MDE) methodology for facilitating the model... more In this paper, we present a Model Driven Engineering (MDE) methodology for facilitating the modeling of the partial reconfiguration process, and for implementing Dynamic Reconfigurable System-on-Chip (DRSoC). The rationale for this approach is to provide a modeling front-end that enables to visually compose a hardware platform, containing heterogeneous components, using both static and context-management hardware wrappers. A model transformations engine (MTE) processes the high-level models to obtain the inputs for the Xilinx dynamic partial reconfiguration (DPR) design flow, with the benefit of better exploiting and reusing the designer intentions regarding the allocation of tasks into reconfigurable areas. Furthermore, the automatic synthesis of a reconfiguration controller (RecOS) with context-management and task relocation capabilities is supported in this version of our tool. The latter feature is possible due to the integration of relocation tool OORBIT into the design chain, but we point out at other avenues of research. We present a case study in which we assess the benefits of the methodology and present a thorough analysis of the reconfiguration costs associated with the context and relocation management, showing speedups of 1.5x over other solutions.

Microprocessors and Microsystems, 2017

With the increasing complexity of algorithms and new applications, the design of efficient embedd... more With the increasing complexity of algorithms and new applications, the design of efficient embedded systems has to integrate efficient communication structures such as Network-on-Chip. Multi-FPGA platforms are considered to be the most appropriate experimental way to emulate and evaluate these large System-on-Chips. The deployment often goes through the Network-on-Chip partitioning on all FPGAs requiring the use of inter-FPGA communication links between routers. The number of external links and their performance restrict the communication bandwidth. Currently, the number of inter-FPGA signals is considered to be a major problem in the Network-on-Chip deployed on multi-FPGAs. As there are more signals to be connected than IOs, inter-FPGA links must be shared between routers leading to significant bottlenecks. As the ratio of the logic capacity to the number of IOs rises slowly for each FPGA generation, this technological bottleneck will be remaining for future system designs. In this paper, we propose a novel architecture for inter-FPGA collision management in the Networkon-Chip partitioned on multi-FPGAs. The structure ensures to efficiently share the external link between several routers with a minimum number of collisions and inter-FPGA bottlenecks. The proposed architecture is easily placed between the Network-on-Chip and the external protocol. The collision management architecture is based on the BackOff algorithm used in Wi-Fi communications and adapted to FPGA platforms. This algorithm balances accesses among all the routers connected with the inter-board interfacing, thereby avoiding collisions. We compare this structure with traditional techniques using experimental and theoretical results. The novel inter-FPGA architecture for the Network-on-Chip based on the BackOff algorithm achieves lower latency with fewer resources compared to other solutions.

Wireless Networks, 2017

Mobile ad hoc networks (MANETs) are becoming an emerging technology that offer several advantages... more Mobile ad hoc networks (MANETs) are becoming an emerging technology that offer several advantages to users in terms of cost and ease of use. A MANET is a collection of mobile nodes connected by wireless links that form a temporary network topology that operates without a base station and centralized administration. Routing is a method through which information is forwarded from a transmitter to a specific recipient. Routing is a strategy that guarantees, at any time, the connection between any two nodes in a network. In this work, we propose a novel routing protocol inspired by the cuckoo search method. Our routing protocol is implemented using Network simulator 2. We chose Random WayPoint model as our mobility model. To validate our work, we opted for the comparison with the routing protocol ad hoc on-demand distance vector, destination sequence distance vector and the bio-inspired routing protocol AntHocNet in terms of the quality of service parameters: packet delivery ratio and end-to-end delay (E2ED).

AIP Conference Proceedings, 2008

In this study we have presented a proposal architectural hardware/software for the implementation... more In this study we have presented a proposal architectural hardware/software for the implementation of the H.264 standard, which means a processor-specific for H.264 standard use of it a hard part and a configurable embedded processor, which is LEON2 in our case. The motion estimation and compensation, the integer numbers transformation, the quantification, the algorithm of entropy encoding uses in the coder H.264 are optimized in material form; the other parts over the operating system are implemented by LEON2 processor.

International Journal of Systems, Control and Communications, 2016

Supervisory control and data acquisition and distributed control systems named (SCADA/DCS) have p... more Supervisory control and data acquisition and distributed control systems named (SCADA/DCS) have played a key role in the design of modern power smart applications, particularly in the automatic management of real-time energetic platforms. In this work, we present a semantic cyber security vulnerabilities add to classic one, with the use of semantic embedded application in smart devices in semantic wireless (SCADA/DCS) systems, focusing on the semantic attacks. In this work, we present a new security semantic wireless protocol as a secure communication support for these modern semantic wireless systems named (ZIGBEE/SOAP/SECURITY), obtained by the combination between wireless ZIGBEE protocol, SOAP protocol and the integration of our security mechanism, in the global message header obtained by the fusion between ZIGBEE message and SOAP message.

2015 27th International Conference on Microelectronics (ICM), 2015

As communication on-chip evolves toward the global multi-service network, applications with diffe... more As communication on-chip evolves toward the global multi-service network, applications with different service requirements have emerged. A key factor is guaranteeing the quality of support services. Differentiated service with double physical planes is seen as the key technology to achieve this goal. It focuses on the control of traffic and on recognizing the need for aspects for the management plan achieved by the bandwidth broker. In this paper, a novel QoS architecture for multimedia application via NoC is proposed. The gains in latency and in resource are possible due to the simplicity of the NoC architecture.

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair

We present the design of a real time image processing circuit based on an optimized Canny Deriche... more We present the design of a real time image processing circuit based on an optimized Canny Deriche filter for ramp edge detection. This filter is implemented in a recursive form. A retiming method is used to achieve very high speed filtering. The edge calculation function has been implemented using a CMOS 1 μm process (area 29 mm2). This ASIC is

Proceedings 1998 International Conference on Image Processing. ICIP98 (Cat. No.98CB36269)

The aim of our work is to realize the implementation of a real-time high-quality image rotation o... more The aim of our work is to realize the implementation of a real-time high-quality image rotation on FPGA's board. The method we used is based on M. Unser's work (1993) and consists in applying a B-spline interpolator. The difficulty of this problem is due to the relatively weak integration capacity of FPGAs. To solve this problem, we have searched for

la contribution de ce travail est la proposition d'une structure de gestion de collision perm... more la contribution de ce travail est la proposition d'une structure de gestion de collision permettant à plusieurs routeurs d’un NoC (Network-on-Chip) de partager un lien inter-FPGA. Cette structure intégrée entre le NoC et le point d’accès permet d’équilibrer les charges sur le lien partagé et ainsi de réduire les latences de communication entre les routeurs. Cette réduction est obtenue sur des trafics synthétiques et des trafics basés sur des applications réelles.

Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase... more Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on MDE and UML MARTE standard have emerged which aim to simplify the design of complex SoCs. Moreover, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. In particular, our goal is the creation of the top level description of the system and to exploit IP reuse in order to generate the netlists used by the Xilinx DPR design flow. The methodology is demonstrated by the integration of Deblocking filter IP used in H.264 CODECs into a MicroBlaze based DPR SoC.

Real-Time Imaging, 2003

A real-time implementation of an approximation of the support vector machine decision rule is pro... more A real-time implementation of an approximation of the support vector machine decision rule is proposed. This method is based on an improvement of a supervised classification method using hyperrectangles, which is useful for real-time image segmentation. The final decision combines the accuracy of the SVM learning algorithm and the speed of a hyperrectanglesbased method. We review the principles of the classification methods and we evaluate the hardware implementation cost of each method. We present the combination algorithm which consists of rejecting ambiguities in the learning set using SVM decision, before using the learning step of the hyperrectangles-based method. We present results obtained using Gaussian distribution and give an example of image segmentation from an industrial inspection problem. The results are evaluated regarding hardware cost as well as classification performances.

Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, 1998

The aim of our work is to realize the implementation of a real-time image rotation on FPGA's boar... more The aim of our work is to realize the implementation of a real-time image rotation on FPGA's board. The method we used is based on a B-spline interpolator. The integration capicity of FPGAs is relatively weak, so the diculty in this problem is to determine the right c o ding of the rotation lter while keeping a good accuracy on ltering outpût. In this article, we remind a few denitions about B-spline functions and we present h o w w e use B-spline interpolation for the image rotation problem. Then, we describe the way w e calculate probability density function of the output error in order to determine the lter data coding.

2010 2nd International Conference on Image Processing Theory, Tools and Applications, 2010

In this paper, we propose a real-time platform for the H.264 CODEC with a memory management metho... more In this paper, we propose a real-time platform for the H.264 CODEC with a memory management method, in which we use a preloading mechanism in order to reduce access to external memory. The platform uses an external DDR2 memory (to record the sequence images) and an intelligent memory controller to read the external memory periodically to load another local memory

Engineering, Technology & Applied Science Research, Apr 2, 2023

An Unmanned Aerial Vehicle (UAV) network specifies a novel type of Mobile Ad hoc Network (MANET) ... more An Unmanned Aerial Vehicle (UAV) network specifies a novel type of Mobile Ad hoc Network (MANET) in which drones serve as nodes and facilitate the retransmission of messages to their final destinations. Aside from its military application, it has recently begun to seep into the civilian sector. Similar to MANET and vehicular ad hoc networks, Flying Ad hoc Networks (FANET) are a subset of ad hoc networks. An FANET is different because it is founded on UAVs. Due to the characteristics of this sort of network, which is defined by a highly changing topology in a 3D environment, we must employ an adjusted configuration method to ensure good routing performance. Therefore, to deal with this problem, a technique that responds to any change in topology by always finding the best route is required. In this work, we propose a new protocol based on the hybrid optimization of the 2-opt heuristic and Honey Badger Algorithm (HBA), called HB-AODV. In order to locate its prey, a badger must move slowly and continuously while using scent markers and mouse-digging skills to catch it. In other words, the most efficient routes in terms of the number of hops are identified. Several simulations were conducted via the 3D version of Network Simulator (NS-2) on different deployment strategies. In comparison to AODV, DSDV, and AntHocNet, the obtained results demonstrated the proposed scheme's good performance in terms of quality of service metrics.

HAL (Le Centre pour la Communication Scientifique Directe), 2018

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering)

Introduction: The 3D integrated circuit technology, which smooths out the massive increase in tra... more Introduction: The 3D integrated circuit technology, which smooths out the massive increase in transistors on a chip by stacking numerous silicon layers vertically, is quickly becoming a revolutionary technology. Thermal issues are more relevant for 3D Network-on-Chip (NoC) systems than their 2D counterparts. Methods: This paper presents a novel Vertically-Partially-Connected 3D-Network on-chip architecture that reduces the total length of interconnects and reduces the number of 3D routers. We also present an efficient XYZ routing technique for thermal management. The proposed algorithm distributes traffic based on the number of layers and congestion to achieve chip heat balancing, avoid high peak temperatures, improve average packet latency, and extend chip service life. Results: Simulation results showed that the routing technique reduces the peak temperature of the chip by an average of 17 °C compared to the exiting routing algorithms, with minimized negative impact on performance...

2020 IEEE 23rd International Multitopic Conference (INMIC), 2020

Integration of FPGAs in datacenters might have different motivations from acceleration to energy ... more Integration of FPGAs in datacenters might have different motivations from acceleration to energy efficiency, but the goal of better performance tops all. FPGAs are being utilized in a variety of ways today, tightly coupled with heterogenous computing resources, and as a standalone network of homogenous resources. Open source software stacks, propriety tool chain, and programming languages with advanced methodologies are hitting hard on the programmability wall of the FPGAs. The deployment of FPGAs in datacenters will neither be sustainable nor economical, without realizing the multi-tenancy in multiple FPGAs. Inter-FPGA communication among multiple FPGAs remained relatively less addressed problem this area. In this proposed study, we made a theoretical case as a potential solution for this bottleneck problem to realize multi-tenant multi-FPGAs in datacenters. The proposed scheme poses a challenge as well as an opportunity for the scientific community to contribute.

020 1st International Conference on Communications, Control Systems and Signal Processing (CCSSP), 2020

Hardware implementation is necessary and important for several applications and in the case of vi... more Hardware implementation is necessary and important for several applications and in the case of video encoders and that in order to ensure real time processing. The integration of these applications into a SoC, based on one or more processor, is one of proposed solutions. The use of a SoC implies the utilization of adequate communication system. The Network-on-Chip is the new communication system proposed for new applications. In addition to the technical characteristics of NoC, the mapping problem is one of important problems that influence on the global characteristics of the application. This work presents a mapping methodology based on genetic algorithms proposed especially for mapping IP cores of the H264 encoder onto mesh-NoC tiles. The main objective is to minimize the total network power of the implemented application. Simulation results confirm that the proposed model is very efficient and optimized the video encoder application in both of the time and energy side.

The research work described here is partial work which is done with ESRG TEAM of the ALGORITHMI C... more The research work described here is partial work which is done with ESRG TEAM of the ALGORITHMI CENTRO in the University of Minho under the guidance of Pr. Jorge CABRAL in collaboration with Tiago Gomes and DR. Reza Abrishambaf at The University of Minho, Guimaraes. I am very thankful for them support.

Journal of Parallel and Distributed Computing, 2018

In this paper, we present a Model Driven Engineering (MDE) methodology for facilitating the model... more In this paper, we present a Model Driven Engineering (MDE) methodology for facilitating the modeling of the partial reconfiguration process, and for implementing Dynamic Reconfigurable System-on-Chip (DRSoC). The rationale for this approach is to provide a modeling front-end that enables to visually compose a hardware platform, containing heterogeneous components, using both static and context-management hardware wrappers. A model transformations engine (MTE) processes the high-level models to obtain the inputs for the Xilinx dynamic partial reconfiguration (DPR) design flow, with the benefit of better exploiting and reusing the designer intentions regarding the allocation of tasks into reconfigurable areas. Furthermore, the automatic synthesis of a reconfiguration controller (RecOS) with context-management and task relocation capabilities is supported in this version of our tool. The latter feature is possible due to the integration of relocation tool OORBIT into the design chain, but we point out at other avenues of research. We present a case study in which we assess the benefits of the methodology and present a thorough analysis of the reconfiguration costs associated with the context and relocation management, showing speedups of 1.5x over other solutions.

Microprocessors and Microsystems, 2017

With the increasing complexity of algorithms and new applications, the design of efficient embedd... more With the increasing complexity of algorithms and new applications, the design of efficient embedded systems has to integrate efficient communication structures such as Network-on-Chip. Multi-FPGA platforms are considered to be the most appropriate experimental way to emulate and evaluate these large System-on-Chips. The deployment often goes through the Network-on-Chip partitioning on all FPGAs requiring the use of inter-FPGA communication links between routers. The number of external links and their performance restrict the communication bandwidth. Currently, the number of inter-FPGA signals is considered to be a major problem in the Network-on-Chip deployed on multi-FPGAs. As there are more signals to be connected than IOs, inter-FPGA links must be shared between routers leading to significant bottlenecks. As the ratio of the logic capacity to the number of IOs rises slowly for each FPGA generation, this technological bottleneck will be remaining for future system designs. In this paper, we propose a novel architecture for inter-FPGA collision management in the Networkon-Chip partitioned on multi-FPGAs. The structure ensures to efficiently share the external link between several routers with a minimum number of collisions and inter-FPGA bottlenecks. The proposed architecture is easily placed between the Network-on-Chip and the external protocol. The collision management architecture is based on the BackOff algorithm used in Wi-Fi communications and adapted to FPGA platforms. This algorithm balances accesses among all the routers connected with the inter-board interfacing, thereby avoiding collisions. We compare this structure with traditional techniques using experimental and theoretical results. The novel inter-FPGA architecture for the Network-on-Chip based on the BackOff algorithm achieves lower latency with fewer resources compared to other solutions.

Wireless Networks, 2017

Mobile ad hoc networks (MANETs) are becoming an emerging technology that offer several advantages... more Mobile ad hoc networks (MANETs) are becoming an emerging technology that offer several advantages to users in terms of cost and ease of use. A MANET is a collection of mobile nodes connected by wireless links that form a temporary network topology that operates without a base station and centralized administration. Routing is a method through which information is forwarded from a transmitter to a specific recipient. Routing is a strategy that guarantees, at any time, the connection between any two nodes in a network. In this work, we propose a novel routing protocol inspired by the cuckoo search method. Our routing protocol is implemented using Network simulator 2. We chose Random WayPoint model as our mobility model. To validate our work, we opted for the comparison with the routing protocol ad hoc on-demand distance vector, destination sequence distance vector and the bio-inspired routing protocol AntHocNet in terms of the quality of service parameters: packet delivery ratio and end-to-end delay (E2ED).

AIP Conference Proceedings, 2008

In this study we have presented a proposal architectural hardware/software for the implementation... more In this study we have presented a proposal architectural hardware/software for the implementation of the H.264 standard, which means a processor-specific for H.264 standard use of it a hard part and a configurable embedded processor, which is LEON2 in our case. The motion estimation and compensation, the integer numbers transformation, the quantification, the algorithm of entropy encoding uses in the coder H.264 are optimized in material form; the other parts over the operating system are implemented by LEON2 processor.

International Journal of Systems, Control and Communications, 2016

Supervisory control and data acquisition and distributed control systems named (SCADA/DCS) have p... more Supervisory control and data acquisition and distributed control systems named (SCADA/DCS) have played a key role in the design of modern power smart applications, particularly in the automatic management of real-time energetic platforms. In this work, we present a semantic cyber security vulnerabilities add to classic one, with the use of semantic embedded application in smart devices in semantic wireless (SCADA/DCS) systems, focusing on the semantic attacks. In this work, we present a new security semantic wireless protocol as a secure communication support for these modern semantic wireless systems named (ZIGBEE/SOAP/SECURITY), obtained by the combination between wireless ZIGBEE protocol, SOAP protocol and the integration of our security mechanism, in the global message header obtained by the fusion between ZIGBEE message and SOAP message.

2015 27th International Conference on Microelectronics (ICM), 2015

As communication on-chip evolves toward the global multi-service network, applications with diffe... more As communication on-chip evolves toward the global multi-service network, applications with different service requirements have emerged. A key factor is guaranteeing the quality of support services. Differentiated service with double physical planes is seen as the key technology to achieve this goal. It focuses on the control of traffic and on recognizing the need for aspects for the management plan achieved by the bandwidth broker. In this paper, a novel QoS architecture for multimedia application via NoC is proposed. The gains in latency and in resource are possible due to the simplicity of the NoC architecture.

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair

We present the design of a real time image processing circuit based on an optimized Canny Deriche... more We present the design of a real time image processing circuit based on an optimized Canny Deriche filter for ramp edge detection. This filter is implemented in a recursive form. A retiming method is used to achieve very high speed filtering. The edge calculation function has been implemented using a CMOS 1 μm process (area 29 mm2). This ASIC is

Proceedings 1998 International Conference on Image Processing. ICIP98 (Cat. No.98CB36269)

The aim of our work is to realize the implementation of a real-time high-quality image rotation o... more The aim of our work is to realize the implementation of a real-time high-quality image rotation on FPGA's board. The method we used is based on M. Unser's work (1993) and consists in applying a B-spline interpolator. The difficulty of this problem is due to the relatively weak integration capacity of FPGAs. To solve this problem, we have searched for

la contribution de ce travail est la proposition d'une structure de gestion de collision perm... more la contribution de ce travail est la proposition d'une structure de gestion de collision permettant à plusieurs routeurs d’un NoC (Network-on-Chip) de partager un lien inter-FPGA. Cette structure intégrée entre le NoC et le point d’accès permet d’équilibrer les charges sur le lien partagé et ainsi de réduire les latences de communication entre les routeurs. Cette réduction est obtenue sur des trafics synthétiques et des trafics basés sur des applications réelles.

Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase... more Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on MDE and UML MARTE standard have emerged which aim to simplify the design of complex SoCs. Moreover, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. In particular, our goal is the creation of the top level description of the system and to exploit IP reuse in order to generate the netlists used by the Xilinx DPR design flow. The methodology is demonstrated by the integration of Deblocking filter IP used in H.264 CODECs into a MicroBlaze based DPR SoC.

Real-Time Imaging, 2003

A real-time implementation of an approximation of the support vector machine decision rule is pro... more A real-time implementation of an approximation of the support vector machine decision rule is proposed. This method is based on an improvement of a supervised classification method using hyperrectangles, which is useful for real-time image segmentation. The final decision combines the accuracy of the SVM learning algorithm and the speed of a hyperrectanglesbased method. We review the principles of the classification methods and we evaluate the hardware implementation cost of each method. We present the combination algorithm which consists of rejecting ambiguities in the learning set using SVM decision, before using the learning step of the hyperrectangles-based method. We present results obtained using Gaussian distribution and give an example of image segmentation from an industrial inspection problem. The results are evaluated regarding hardware cost as well as classification performances.

Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, 1998

The aim of our work is to realize the implementation of a real-time image rotation on FPGA's boar... more The aim of our work is to realize the implementation of a real-time image rotation on FPGA's board. The method we used is based on a B-spline interpolator. The integration capicity of FPGAs is relatively weak, so the diculty in this problem is to determine the right c o ding of the rotation lter while keeping a good accuracy on ltering outpût. In this article, we remind a few denitions about B-spline functions and we present h o w w e use B-spline interpolation for the image rotation problem. Then, we describe the way w e calculate probability density function of the output error in order to determine the lter data coding.

2010 2nd International Conference on Image Processing Theory, Tools and Applications, 2010

In this paper, we propose a real-time platform for the H.264 CODEC with a memory management metho... more In this paper, we propose a real-time platform for the H.264 CODEC with a memory management method, in which we use a preloading mechanism in order to reduce access to external memory. The platform uses an external DDR2 memory (to record the sequence images) and an intelligent memory controller to read the external memory periodically to load another local memory