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Papers by Eleftherios Ioannidis

Research paper thumbnail of Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

IEEE Transactions on Electron Devices, 2015

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Research paper thumbnail of Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

A new full gate voltage range methodology using a Lambert W function based inversion charge model... more A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental Id–Vg measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel length...

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Research paper thumbnail of Evolution of low frequency noise and noise variability through CMOS bulk technology nodes

In this paper, we present a thorough investigation of low frequency noise (LFN) and statistical n... more In this paper, we present a thorough investigation of low frequency noise (LFN) and statistical noise variability through CMOS bulk technologies manufactured in STMicroelectronics along the past 12 years. The experimental results are well interpreted by the carrier number (CNF) with correlated mobility (CMF) fluctuation model. This enabled us to plot the evolution with time and technology generation of the oxide trap density N t as a function of equivalent oxide thickness EOT. It appears that, with the device miniaturization, N t has increased from 2x10 16 /eV/cm 3 up to 5-7x10 17 /eV/cm 3 when passing from EOT=12nm for 250nm node to EOT=1.4nm for 28nm node for n-MOS. Despite this increase of the mean trap density N t , the LFN statistical variability has surprisingly been well controlled and even improved in 28nm node, emphasizing the progress in process control in such advanced technologies.

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Research paper thumbnail of Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs

Solid-State Electronics, 2012

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Research paper thumbnail of Dynamic variability in 14nm FD-SOI MOSFETs and transient simulation methodology

Solid-State Electronics, 2015

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Research paper thumbnail of Low frequency noise statistical characterization of 14nm FDSOI technology node

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Research paper thumbnail of Impact of Source–Drain Series Resistance on Drain Current Mismatch in Advanced Fully Depleted SOI n-MOSFETs

IEEE Electron Device Letters

In this letter, we demonstrate the existence of the source–drain series resistance mismatch and i... more In this letter, we demonstrate the existence of the source–drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on YYY -function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices.

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Research paper thumbnail of Front-back gate coupling effect on 1/f noise in ultra-thin Si film FDSOI MOSFETs

Low-frequency (LF) noise was studied on 28 nm CMOS technology FDSOI devices with ultra-thin silic... more Low-frequency (LF) noise was studied on 28 nm CMOS technology FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). The noise level was observed to be strongly dependent on the combination of the front and back gate biasing voltages. This was explained by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), in combination with the variation of the Remote Coulomb scattering coefficient α. From comparison of the experimental and simulation results, it is illustrated that the main reason of this dependence is the distance between the charge distribution centroid and the interfaces, which is also controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient α. A new LF noise model approach is suggested to include the impact of all these parameters, and also allows us to extract the oxide trap density values for bot...

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Research paper thumbnail of New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

2015 IEEE International Reliability Physics Symposium, 2015

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Research paper thumbnail of Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

IEEE Transactions on Electron Devices, 2015

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Research paper thumbnail of Impact of low-frequency noise variability on statistical parameter extraction in ultra-scaled CMOS devices

Electronics Letters

The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in ... more The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed.

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Research paper thumbnail of Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012

ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon... more ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

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Research paper thumbnail of Low-frequency noise behavior of n-channel UTBB FD-SOI MOSFETs

2013 22nd International Conference on Noise and Fluctuations (ICNF), 2013

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Research paper thumbnail of Evolution of low frequency noise and noise variability through CMOS bulk technology nodes from 0.5μm down to 20nm

Solid-State Electronics, 2014

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Research paper thumbnail of Characterization and modeling of low frequency noise in CMOS inverters

Solid-State Electronics, 2013

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Research paper thumbnail of Characterization of traps in the gate dielectric of amorphous and nanocrystalline silicon thin-film transistors by 1/f noise

Journal of Applied Physics, 2010

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Research paper thumbnail of Analytical low-frequency noise model in the linear region of lightly doped nanoscale double-gate metal-oxide-semiconductor field-effect transistors

Journal of Applied Physics, 2010

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Research paper thumbnail of Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs

IEEE Transactions on Electron Devices, 2000

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Research paper thumbnail of Effect of Localized Interface Charge on the Threshold Voltage of Short-Channel Undoped Symmetrical Double-Gate MOSFETs

IEEE Transactions on Electron Devices, 2000

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Research paper thumbnail of Impact of dynamic variability on the operation of CMOS inverter

Electronics Letters, 2013

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Research paper thumbnail of Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

IEEE Transactions on Electron Devices, 2015

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

A new full gate voltage range methodology using a Lambert W function based inversion charge model... more A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental Id–Vg measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel length...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Evolution of low frequency noise and noise variability through CMOS bulk technology nodes

In this paper, we present a thorough investigation of low frequency noise (LFN) and statistical n... more In this paper, we present a thorough investigation of low frequency noise (LFN) and statistical noise variability through CMOS bulk technologies manufactured in STMicroelectronics along the past 12 years. The experimental results are well interpreted by the carrier number (CNF) with correlated mobility (CMF) fluctuation model. This enabled us to plot the evolution with time and technology generation of the oxide trap density N t as a function of equivalent oxide thickness EOT. It appears that, with the device miniaturization, N t has increased from 2x10 16 /eV/cm 3 up to 5-7x10 17 /eV/cm 3 when passing from EOT=12nm for 250nm node to EOT=1.4nm for 28nm node for n-MOS. Despite this increase of the mean trap density N t , the LFN statistical variability has surprisingly been well controlled and even improved in 28nm node, emphasizing the progress in process control in such advanced technologies.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs

Solid-State Electronics, 2012

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Dynamic variability in 14nm FD-SOI MOSFETs and transient simulation methodology

Solid-State Electronics, 2015

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Low frequency noise statistical characterization of 14nm FDSOI technology node

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Impact of Source–Drain Series Resistance on Drain Current Mismatch in Advanced Fully Depleted SOI n-MOSFETs

IEEE Electron Device Letters

In this letter, we demonstrate the existence of the source–drain series resistance mismatch and i... more In this letter, we demonstrate the existence of the source–drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on YYY -function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Front-back gate coupling effect on 1/f noise in ultra-thin Si film FDSOI MOSFETs

Low-frequency (LF) noise was studied on 28 nm CMOS technology FDSOI devices with ultra-thin silic... more Low-frequency (LF) noise was studied on 28 nm CMOS technology FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). The noise level was observed to be strongly dependent on the combination of the front and back gate biasing voltages. This was explained by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), in combination with the variation of the Remote Coulomb scattering coefficient α. From comparison of the experimental and simulation results, it is illustrated that the main reason of this dependence is the distance between the charge distribution centroid and the interfaces, which is also controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient α. A new LF noise model approach is suggested to include the impact of all these parameters, and also allows us to extract the oxide trap density values for bot...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

2015 IEEE International Reliability Physics Symposium, 2015

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

IEEE Transactions on Electron Devices, 2015

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Impact of low-frequency noise variability on statistical parameter extraction in ultra-scaled CMOS devices

Electronics Letters

The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in ... more The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012

ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon... more ABSTRACT Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Low-frequency noise behavior of n-channel UTBB FD-SOI MOSFETs

2013 22nd International Conference on Noise and Fluctuations (ICNF), 2013

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Evolution of low frequency noise and noise variability through CMOS bulk technology nodes from 0.5μm down to 20nm

Solid-State Electronics, 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Characterization and modeling of low frequency noise in CMOS inverters

Solid-State Electronics, 2013

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Characterization of traps in the gate dielectric of amorphous and nanocrystalline silicon thin-film transistors by 1/f noise

Journal of Applied Physics, 2010

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Analytical low-frequency noise model in the linear region of lightly doped nanoscale double-gate metal-oxide-semiconductor field-effect transistors

Journal of Applied Physics, 2010

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs

IEEE Transactions on Electron Devices, 2000

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Effect of Localized Interface Charge on the Threshold Voltage of Short-Channel Undoped Symmetrical Double-Gate MOSFETs

IEEE Transactions on Electron Devices, 2000

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Impact of dynamic variability on the operation of CMOS inverter

Electronics Letters, 2013

Bookmarks Related papers MentionsView impact