Enrico Schiattarella - Academia.edu (original) (raw)

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Papers by Enrico Schiattarella

2007 Ieee International Conference on Communications, 2007

Dealing with RTTs (Round Trip Time) in IQ switches has been recently recognized as a challenging ... more Dealing with RTTs (Round Trip Time) in IQ switches has been recently recognized as a challenging problem, especially if considering distributed (multi-chip) scheduler implementation which are suited to reduce the hardware complexity in very large, high-speed, switches. Traditional iterative three-or two-phase scheduling algorithms are based on a monolithic implementation, thus allowing instantaneous information exchange among input and output selectors to determine a matching. Multichip implementation imply that information exchange among inputs and outputs is delayed by an inter-chip latency. This delay requires non-trivial modifications to scheduling algorithms to allow a fully distributed implementation while keeping good performance. We propose a new scheduling algorithm, named SRR (Synchronous Round Robin), which is suited to a fully distributed implementation and provides good performance if compared with more complex, non fully distributed, previously proposed scheduling algorithms.

Modeling and Simulation Tools for Emerging Telecommunication Networks, 2006

Fluid models of IP networks have been recently proposed, to break the scalability barrier of trad... more Fluid models of IP networks have been recently proposed, to break the scalability barrier of traditional performance evaluation approaches, both simulative (e.g., ns-2) and analytical (e.g., queues and Markov chains). Fluid models adopt a deterministic description of the average source and network dynamics through a set of (coupled) ordinary differential equations that are solved numerically, obtaining estimates of the time-dependent

2006 Workshop on High Performance Switching and Routing, 2006

The goal of this work is to enable distributed (multi-chip) implementations of iterative matching... more The goal of this work is to enable distributed (multi-chip) implementations of iterative matching algorithms for crossbar-based packet switches, as opposed to the traditional monolithic (single-chip) ones. The practical motivation for this effort is the design and implementation in FPGAs of a scheduler for a 64-port optical crossbar switch. Sizing experiments show that the scheduler logic must be distributed over multiple devices, which introduces a number of new challenges. Most importantly, the physical distances introduce latencies that exceed the timing requirements, and the separation of logical units prevents shared access to status information. We consider three levels of distribution, and present techniques to mitigate the consequences of specific distribution levels. The performance results obtained via simulation show that, using these methods, a distributed scheduler can achieve a performance close to that of a monolithic scheduler, even with large internal latencies.

IEEE International Conference on Communications, 2007

HPSR. 2005 Workshop on High Performance Switching and Routing, 2005., 2005

This paper focuses on a switching architecture designed for Storage Area Network (SAN) applicatio... more This paper focuses on a switching architecture designed for Storage Area Network (SAN) applications, with a crossbar switching fabric and an aggregate bandwidth of hundreds of Gbps. We describe the architecture and adopt an abstract model of the flow-controlled, credit-based, packet transfer around the switching fabric. The major effects on performance of the credit-based flow control are investigated under different system parameters. 0-7803-8924-7/05/$20.00 (C) 2005 IEEE

IEEE Globecom 2006, 2006

Efficient support of multicast traffic in Storage Area Networks (SANs) enables applications such ... more Efficient support of multicast traffic in Storage Area Networks (SANs) enables applications such as remote data replication and distributed multimedia systems, in which a server must access concurrently multiple storage devices or, conversely, multiple servers must access data on a single device. In this paper we extend an innovative switching architecture, proposed in a previous paper, to support multicast traffic. We describe the most important aspects, focusing in particular on the mechanisms that permit to achieve lossless behavior. We then use simulation to analyze system performance and the impact of such mechanisms under various traffic patterns. Although the work is inspired by a specific switch architecture, results have a more general flavor and permit to highlight interesting trends in flow controlled architectures.

Fluid models of IP networks have been recently proposed as a way to break the scalability barrier... more Fluid models of IP networks have been recently proposed as a way to break the scalability barrier of traditional discrete state-space models, both simulative (e.g., ns-2) and analytical (e.g., queues and Markov chains).

2006 IEEE International Conference on Communications, 2006

We present a scheme to concurrently schedule unicast and multicast traffic in an input-queued swi... more We present a scheme to concurrently schedule unicast and multicast traffic in an input-queued switch. It aims at providing high performance under any mix of the two traffic types as well as at avoiding starvation of any connection. The key idea is to schedule the two traffic types independently and in parallel, and then arbitrate among them for access to the switching fabric. The unicast and multicast matchings are combined into a single integrated matching. Edges that are excluded from the integrated matching are guaranteed to receive service at a later time, thus preventing starvation. We use simulation to evaluate the performance of a system employing the proposed scheme and show that, despite its simplicity, the scheme achieves the intended goals. We also design an enhanced remainder-service policy to achieve better integration and further improve performance.

IEEE Micro, 2006

A crucial part of any high-performance computing (HPC) system is its interconnection network. Cor... more A crucial part of any high-performance computing (HPC) system is its interconnection network. Corning and IBM are jointly developing a demonstration interconnect based on optical cell switching with electronic control. The Corning-IBM joint optical shared memory supercomputer interconnect system (Osmosis) project explores the opportunity to advance the role of optical-switching technologies in such systems. Key innovations in the scheduler architecture directly address the main HPC requirements: low latency, high throughput, efficient multicast support, and high reliability

Quality of Service in Multiservice IP Networks, 2005

Modeling mice in an effective and scalable manner is one of the main challenges in the performanc... more Modeling mice in an effective and scalable manner is one of the main challenges in the performance evaluation of IP networks. Mice is the name that has become customary to identify short-lived TCP connections, that form the vast majority of packet flows over the Internet. On the contrary, long-lived TCP flows, that are far less numerous, but comprise many more packets, are often called elephants. Fluid models were recently proved to be a promising effective and scalable approach to investigate the dynamics of IP networks loaded by elephants. In this paper we extend fluid models in such a way that IP networks loaded by traffic mixes comprising both mice and elephants can be studied. We then show that the newly proposed class of fluid models is quite effective in the analysis of networks loaded by mice only, since this traffic is much more critical than a mix of mice and elephants.

Lecture Notes in Computer Science, 2005