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Papers by Erik Seligman
Formal Verification, 2015
Now that the reader is familiar with the general concepts of FPV, we use this chapter to describe... more Now that the reader is familiar with the general concepts of FPV, we use this chapter to describe FPV usage for the specific goal of providing “instant testbenches” for early exercise and testing of RTL designs. Using the motivating example of a small traffic light controller implemented with a set of interacting state machines, we walk through the typical steps of design exercise FPV. First we create a design exercise plan, a lightweight collection of goals, properties, complexity staging ideas, and exit criteria. Then we develop the design exercise FPV environment, which includes building the model, creating suitable properties, and other details such as clocks and resets. Once this preparation is done, we demonstrate the “wiggling” process for early debug, followed by more interesting exercise cases. We then conclude by showing how we can evolve this FPV environment to demonstrate more complex model behaviors.
Math Mutation Classics, 2016
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches fo... more Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Learn formal verification algorithms to gain full coverage without exhaustive simulation Understand formal ...
Formal Verification, 2015
Now that the reader is familiar with the general concepts of FPV, we use this chapter to describe... more Now that the reader is familiar with the general concepts of FPV, we use this chapter to describe FPV usage for the specific goal of providing “instant testbenches” for early exercise and testing of RTL designs. Using the motivating example of a small traffic light controller implemented with a set of interacting state machines, we walk through the typical steps of design exercise FPV. First we create a design exercise plan, a lightweight collection of goals, properties, complexity staging ideas, and exit criteria. Then we develop the design exercise FPV environment, which includes building the model, creating suitable properties, and other details such as clocks and resets. Once this preparation is done, we demonstrate the “wiggling” process for early debug, followed by more interesting exercise cases. We then conclude by showing how we can evolve this FPV environment to demonstrate more complex model behaviors.
Math Mutation Classics, 2016
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches fo... more Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Learn formal verification algorithms to gain full coverage without exhaustive simulation Understand formal ...