Ernesto Romero - Academia.edu (original) (raw)

Papers by Ernesto Romero

International Journal of Computer Applications, 2021

Reversible computing is of great interest due to the fact that the next generation of high perfor... more Reversible computing is of great interest due to the fact that the next generation of high performance computers must decrease heat dissipation in order to be practical, and irreversible gates dissipate energy into the environment because of the loss of information. This paper takes advantage of Multiple Valued Logic (MVL) quaternary universal set, that reduces integrated circuits (IC) interconnections, decreasing IC area, and with reversible gates that minimizes IC dissipation. The reversible computation permits both forward and backward computations, keeping the information entropy constant and decreasing heat dissipation, according to Landauer principle. The reversible gates are designed as an extension of the set of gates: Extended AND (eANDi: eAND1, eAND2, eAND3), Maximum (MAX) and Successor (SUC) already proposed in the literature. The voltage mode gates are implemented by means of three cascaded subsystems: the first subsystem discriminates 0,1,2,3 logical levels; the second subsystem performs the logic to implement each operator functionality; and the third subsystem set the right voltage output corresponding to 0,1,2,3 logical levels. Simulations with only 25, 18,

Ingeniare. Revista chilena de ingeniería, 2020

The scale of integration of processors has increased in recent decades, new challenges have emerg... more The scale of integration of processors has increased in recent decades, new challenges have emerged and chip area has become an important issue. Designers have been motivated to seek new techniques and technologies, among them, the multi-value logic (MVL). The quaternary representation, domain D: {0, 1, 2, 3} reduces the number of connections due to the fact that, approximately, 70% of the circuit area is being used for interconnections and pads. This work proposes the design of a four stages pipelined quaternary processor (eCPU) with sixteen instructions and the handling of hazards utilizing hybrid (static and dynamic) techniques with the scope to demonstrate the correct functionality with respect to the design specification, based on a universal set of quaternary logic gates already proposed in the literature. The eCPU has been designed via hardware description in Quartus environment written in VHSIC Hardware Description Language (VHDL) and simulations performed in ModelSim  , demonstrating the correct behavior with respect to the specifications. The simulations are performed by executing several programs written in the chosen quaternary assembly language with the support of a two phase's compiler written in Java to generate quaternary machine code.

International Journal of Computer Applications, 2021

Reversible computing is of great interest due to the fact that the next generation of high perfor... more Reversible computing is of great interest due to the fact that the next generation of high performance computers must decrease heat dissipation in order to be practical, and irreversible gates dissipate energy into the environment because of the loss of information. This paper takes advantage of Multiple Valued Logic (MVL) quaternary universal set, that reduces integrated circuits (IC) interconnections, decreasing IC area, and with reversible gates that minimizes IC dissipation. The reversible computation permits both forward and backward computations, keeping the information entropy constant and decreasing heat dissipation, according to Landauer principle. The reversible gates are designed as an extension of the set of gates: Extended AND (eANDi: eAND1, eAND2, eAND3), Maximum (MAX) and Successor (SUC) already proposed in the literature. The voltage mode gates are implemented by means of three cascaded subsystems: the first subsystem discriminates 0,1,2,3 logical levels; the second subsystem performs the logic to implement each operator functionality; and the third subsystem set the right voltage output corresponding to 0,1,2,3 logical levels. Simulations with only 25, 18,

Ingeniare. Revista chilena de ingeniería, 2020

The scale of integration of processors has increased in recent decades, new challenges have emerg... more The scale of integration of processors has increased in recent decades, new challenges have emerged and chip area has become an important issue. Designers have been motivated to seek new techniques and technologies, among them, the multi-value logic (MVL). The quaternary representation, domain D: {0, 1, 2, 3} reduces the number of connections due to the fact that, approximately, 70% of the circuit area is being used for interconnections and pads. This work proposes the design of a four stages pipelined quaternary processor (eCPU) with sixteen instructions and the handling of hazards utilizing hybrid (static and dynamic) techniques with the scope to demonstrate the correct functionality with respect to the design specification, based on a universal set of quaternary logic gates already proposed in the literature. The eCPU has been designed via hardware description in Quartus environment written in VHSIC Hardware Description Language (VHDL) and simulations performed in ModelSim  , demonstrating the correct behavior with respect to the specifications. The simulations are performed by executing several programs written in the chosen quaternary assembly language with the support of a two phase's compiler written in Java to generate quaternary machine code.

IEEE Latin America Transactions, 2018

Most of the digital processing is performed in the binary domain. With the increasing integration... more Most of the digital processing is performed in the binary domain. With the increasing integration, chip area became an important resource to improve transistor density and energy efficiency. An alternative to reduce chip area is to increase the representation up to base B, domain D: (0, 1, 2,…, B-1) known as Multiple-Valued Logic (MVL) to decrease chip wirings due to the fact that approximately 70% chip area is devoted to the interconnections. For the digital processing of analog signals an Analog to Digital Mapping is needed. This proposal is a mapping and not a complete analog to digital converter (ADC) due to the fact that there are not any circuits to correct errors, for example: linearity, bits synchronization, etc. This work presents a voltage mode multiple valued analog to quaternary mapping architecture for two digits utilizing the chosen universal set of MVL operators presented in the literature for quaternary base B=4:eAND1, eAND2, eAND3, Successor, and Maximum that allows to design any MVL digital circuit. Simulations on Cadence Tools for the AMS CMOS 0,35 µm technology will be presented to demonstrate concepts and circuit feasibility and functionality, showing correct behavior with respect to the specification and compatibility with the chosen universal set of gates.

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS), 2011

This paper presents a parallel architecture for an N-digit and B multiple-valued logic analog to ... more This paper presents a parallel architecture for an N-digit and B multiple-valued logic analog to digital converter (B-MVL-ADC), where B stands for the number of levels of the multiple-valued logic. The B-MVL-ADC is based on the modulo (MOD) operator and is built by making N replicas of 1-digit converter. Simulations and discrete imple- mentation results, for the binary ADC (2-MVL-ADC)

IEEE Latin America Transactions, 2018

Most of the digital processing is performed in the binary domain. With the increasing integration... more Most of the digital processing is performed in the binary domain. With the increasing integration, chip area became an important resource to improve transistor density and energy efficiency. An alternative to reduce chip area is to increase the representation up to base B, domain D: (0, 1, 2,…, B-1) known as Multiple-Valued Logic (MVL) to decrease chip wirings due to the fact that approximately 70% chip area is devoted to the interconnections. For the digital processing of analog signals an Analog to Digital Mapping is needed. This proposal is a mapping and not a complete analog to digital converter (ADC) due to the fact that there are not any circuits to correct errors, for example: linearity, bits synchronization, etc. This work presents a voltage mode multiple valued analog to quaternary mapping architecture for two digits utilizing the chosen universal set of MVL operators presented in the literature for quaternary base B=4:eAND1, eAND2, eAND3, Successor, and Maximum that allows to design any MVL digital circuit. Simulations on Cadence Tools for the AMS CMOS 0,35 µm technology will be presented to demonstrate concepts and circuit feasibility and functionality, showing correct behavior with respect to the specification and compatibility with the chosen universal set of gates.

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS), 2011

This paper presents a parallel architecture for an N-digit and B multiple-valued logic analog to ... more This paper presents a parallel architecture for an N-digit and B multiple-valued logic analog to digital converter (B-MVL-ADC), where B stands for the number of levels of the multiple-valued logic. The B-MVL-ADC is based on the modulo (MOD) operator and is built by making N replicas of 1-digit converter. Simulations and discrete imple- mentation results, for the binary ADC (2-MVL-ADC)

2012 10th IEEE/IAS International Conference on Industry Applications, 2012

This paper presents an integrated system for automatic diagnostic on power transformers (SIDAT) o... more This paper presents an integrated system for automatic diagnostic on power transformers (SIDAT) of substations. SIDAT performs diagnosis based on several kinds of tests such as thermography images, chromatography, physical-chemical, and electrical. SIDAT also performs prognostic indicating the time life of the equipment. The inference engine for diagnostic is based on rules of the maintenance department of the company and it has been designed as a set Mealy Finite State Machines (FSMs). The system has been tested and evaluated with data coming from a production environment and stores data of 157 power transformers (13.8kVA and 34.5kVA) located in 94 different substations.

2012 10th IEEE/IAS International Conference on Industry Applications, 2012

2009 39th International Symposium on Multiple-Valued Logic, 2009

The synthesis and simplification of digital circuits are performed in the well known two level lo... more The synthesis and simplification of digital circuits are performed in the well known two level logic switching algebra. By increasing the representation domain to B levels it is possible to design multiple-valued logic (MV Logic) digital circuits. This work proposes an algebra based on a universal set of gates which carry out operators to allow synthesis and simplification of MV

Ingeniare. Revista chilena de ingeniería, 2013

Extensões do Quad-tree para a estimação do mapa denso de disparidade utilizando a luminância no d... more Extensões do Quad-tree para a estimação do mapa denso de disparidade utilizando a luminância no domínio real foram propostas na literatura. A contribuição deste trabalho é a comparação do processamento de imagens estéreo entre o algoritmo que é uma extensão do Quad-tree para processar imagens no domínio real utilizando a luminância, com o algoritmo, aqui proposto, que é a extensão do Quad-tree para processar imagens codificadas no domínio da álgebra de Clifford utilizando imagens coloridas do modelo YUV. O mapa denso de disparidade é obtido resolvendo o problema da correspondência para cada pixel entre o par estereoscópico. O problema da correspondência é fundamental e apresenta dificuldades devido à presença de áreas oclusas, ruídos e variações na iluminação, etc. A álgebra de Clifford é utilizada para mapear os valores do modelo YUV de cada pixel nos vetores de base, compondo um número de Clifford. Neste domínio, geram-se resultados melhores para imagens que têm muitos objetos na cena, aqui definidas como complexas, se comparados com os obtidos sobre as imagens utilizando o domínio real sobre a luminância. Processando os pares estereoscópicos utilizados no algoritmo proposto no domínio real e no domínio de Clifford se demonstra, experimentalmente, a melhora obtida para imagens em cenas reais.

IEEE Transactions on Circuits and Systems I: Regular Papers, 2014

ABSTRACT The design of Multiple Valued Logic (MVL) digital circuits is performed by increasing th... more ABSTRACT The design of Multiple Valued Logic (MVL) digital circuits is performed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. Universal sets of MVL CMOS gates allow the synthesis and implementation of any MVL digital circuit. The main drawback of this approach is the lack of existing integrated circuits that implement the universal set of MVL gates. This paper deals with: 1) the design and implementation of a universal set of IC gates, CMOS 0.35 µm technology, that carry out extended AND operators: eAND1, eAND2, eAND3, Successor (SUC), and Maximum (MAX) operators to perform synthesis of any MVL digital circuits; and 2) the synthesis of an MVL multiplexer and latch memory circuits, based on the IC MVL gates, to illustrate the utilization of the proposed IC MVL gates for quaternary MVL. Implemented circuits demonstrate correct functionality of the implemented gates and feasibility of the MVL combinatorial and memory circuit design. The proposed gates allow designing MVL digital circuit taking advantage of the knowledge coming from the binary circuits. By using a methodology based on the boolean algebra, digital circuits designers can take advantage of it to decrease the design learn curve.

Estudio descriptivo transversal, usando con este fin, encuestas, entrevistas a agentes externos, ... more Estudio descriptivo transversal, usando con este fin, encuestas, entrevistas a agentes externos, muestra tomada de forma aleatoria por conglomerados, que para este estudio fueron directivos de centros de salud, enfermeras, medicos graduados y pacientes. Basadas en tres indicadores calificados segun estandares definidos por el CONEA. Resultados: al indicador 186: opinion de la comunidad respecto a la contribucion recibida de la institucion para el desarrollo socioeconomico, el valor es de 4.3 que corresponde a 61.7es decir una calificacion de buena. Al indicador 187, Grado de reconocimiento de la sociedad sobre la contribucion de la institucion en la formacion de principios y valores en la comunidad, el valor obtenido corresponde a 4,3 (62.4) es decir una calificacion de buena, expresando avances significativos. Al indicador 188: Apreciacion de la colectividad sobre la vitalodad institucional para su mejoramiento y desarrollo, la calificacion es de 4.6 que equivale a un 65.9. Finalme...

International Journal of Computer Applications, 2021

Reversible computing is of great interest due to the fact that the next generation of high perfor... more Reversible computing is of great interest due to the fact that the next generation of high performance computers must decrease heat dissipation in order to be practical, and irreversible gates dissipate energy into the environment because of the loss of information. This paper takes advantage of Multiple Valued Logic (MVL) quaternary universal set, that reduces integrated circuits (IC) interconnections, decreasing IC area, and with reversible gates that minimizes IC dissipation. The reversible computation permits both forward and backward computations, keeping the information entropy constant and decreasing heat dissipation, according to Landauer principle. The reversible gates are designed as an extension of the set of gates: Extended AND (eANDi: eAND1, eAND2, eAND3), Maximum (MAX) and Successor (SUC) already proposed in the literature. The voltage mode gates are implemented by means of three cascaded subsystems: the first subsystem discriminates 0,1,2,3 logical levels; the second subsystem performs the logic to implement each operator functionality; and the third subsystem set the right voltage output corresponding to 0,1,2,3 logical levels. Simulations with only 25, 18,

Ingeniare. Revista chilena de ingeniería, 2020

The scale of integration of processors has increased in recent decades, new challenges have emerg... more The scale of integration of processors has increased in recent decades, new challenges have emerged and chip area has become an important issue. Designers have been motivated to seek new techniques and technologies, among them, the multi-value logic (MVL). The quaternary representation, domain D: {0, 1, 2, 3} reduces the number of connections due to the fact that, approximately, 70% of the circuit area is being used for interconnections and pads. This work proposes the design of a four stages pipelined quaternary processor (eCPU) with sixteen instructions and the handling of hazards utilizing hybrid (static and dynamic) techniques with the scope to demonstrate the correct functionality with respect to the design specification, based on a universal set of quaternary logic gates already proposed in the literature. The eCPU has been designed via hardware description in Quartus environment written in VHSIC Hardware Description Language (VHDL) and simulations performed in ModelSim  , demonstrating the correct behavior with respect to the specifications. The simulations are performed by executing several programs written in the chosen quaternary assembly language with the support of a two phase's compiler written in Java to generate quaternary machine code.

International Journal of Computer Applications, 2021

Reversible computing is of great interest due to the fact that the next generation of high perfor... more Reversible computing is of great interest due to the fact that the next generation of high performance computers must decrease heat dissipation in order to be practical, and irreversible gates dissipate energy into the environment because of the loss of information. This paper takes advantage of Multiple Valued Logic (MVL) quaternary universal set, that reduces integrated circuits (IC) interconnections, decreasing IC area, and with reversible gates that minimizes IC dissipation. The reversible computation permits both forward and backward computations, keeping the information entropy constant and decreasing heat dissipation, according to Landauer principle. The reversible gates are designed as an extension of the set of gates: Extended AND (eANDi: eAND1, eAND2, eAND3), Maximum (MAX) and Successor (SUC) already proposed in the literature. The voltage mode gates are implemented by means of three cascaded subsystems: the first subsystem discriminates 0,1,2,3 logical levels; the second subsystem performs the logic to implement each operator functionality; and the third subsystem set the right voltage output corresponding to 0,1,2,3 logical levels. Simulations with only 25, 18,

Ingeniare. Revista chilena de ingeniería, 2020

The scale of integration of processors has increased in recent decades, new challenges have emerg... more The scale of integration of processors has increased in recent decades, new challenges have emerged and chip area has become an important issue. Designers have been motivated to seek new techniques and technologies, among them, the multi-value logic (MVL). The quaternary representation, domain D: {0, 1, 2, 3} reduces the number of connections due to the fact that, approximately, 70% of the circuit area is being used for interconnections and pads. This work proposes the design of a four stages pipelined quaternary processor (eCPU) with sixteen instructions and the handling of hazards utilizing hybrid (static and dynamic) techniques with the scope to demonstrate the correct functionality with respect to the design specification, based on a universal set of quaternary logic gates already proposed in the literature. The eCPU has been designed via hardware description in Quartus environment written in VHSIC Hardware Description Language (VHDL) and simulations performed in ModelSim  , demonstrating the correct behavior with respect to the specifications. The simulations are performed by executing several programs written in the chosen quaternary assembly language with the support of a two phase's compiler written in Java to generate quaternary machine code.

IEEE Latin America Transactions, 2018

Most of the digital processing is performed in the binary domain. With the increasing integration... more Most of the digital processing is performed in the binary domain. With the increasing integration, chip area became an important resource to improve transistor density and energy efficiency. An alternative to reduce chip area is to increase the representation up to base B, domain D: (0, 1, 2,…, B-1) known as Multiple-Valued Logic (MVL) to decrease chip wirings due to the fact that approximately 70% chip area is devoted to the interconnections. For the digital processing of analog signals an Analog to Digital Mapping is needed. This proposal is a mapping and not a complete analog to digital converter (ADC) due to the fact that there are not any circuits to correct errors, for example: linearity, bits synchronization, etc. This work presents a voltage mode multiple valued analog to quaternary mapping architecture for two digits utilizing the chosen universal set of MVL operators presented in the literature for quaternary base B=4:eAND1, eAND2, eAND3, Successor, and Maximum that allows to design any MVL digital circuit. Simulations on Cadence Tools for the AMS CMOS 0,35 µm technology will be presented to demonstrate concepts and circuit feasibility and functionality, showing correct behavior with respect to the specification and compatibility with the chosen universal set of gates.

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS), 2011

This paper presents a parallel architecture for an N-digit and B multiple-valued logic analog to ... more This paper presents a parallel architecture for an N-digit and B multiple-valued logic analog to digital converter (B-MVL-ADC), where B stands for the number of levels of the multiple-valued logic. The B-MVL-ADC is based on the modulo (MOD) operator and is built by making N replicas of 1-digit converter. Simulations and discrete imple- mentation results, for the binary ADC (2-MVL-ADC)

IEEE Latin America Transactions, 2018

Most of the digital processing is performed in the binary domain. With the increasing integration... more Most of the digital processing is performed in the binary domain. With the increasing integration, chip area became an important resource to improve transistor density and energy efficiency. An alternative to reduce chip area is to increase the representation up to base B, domain D: (0, 1, 2,…, B-1) known as Multiple-Valued Logic (MVL) to decrease chip wirings due to the fact that approximately 70% chip area is devoted to the interconnections. For the digital processing of analog signals an Analog to Digital Mapping is needed. This proposal is a mapping and not a complete analog to digital converter (ADC) due to the fact that there are not any circuits to correct errors, for example: linearity, bits synchronization, etc. This work presents a voltage mode multiple valued analog to quaternary mapping architecture for two digits utilizing the chosen universal set of MVL operators presented in the literature for quaternary base B=4:eAND1, eAND2, eAND3, Successor, and Maximum that allows to design any MVL digital circuit. Simulations on Cadence Tools for the AMS CMOS 0,35 µm technology will be presented to demonstrate concepts and circuit feasibility and functionality, showing correct behavior with respect to the specification and compatibility with the chosen universal set of gates.

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS), 2011

This paper presents a parallel architecture for an N-digit and B multiple-valued logic analog to ... more This paper presents a parallel architecture for an N-digit and B multiple-valued logic analog to digital converter (B-MVL-ADC), where B stands for the number of levels of the multiple-valued logic. The B-MVL-ADC is based on the modulo (MOD) operator and is built by making N replicas of 1-digit converter. Simulations and discrete imple- mentation results, for the binary ADC (2-MVL-ADC)

2012 10th IEEE/IAS International Conference on Industry Applications, 2012

This paper presents an integrated system for automatic diagnostic on power transformers (SIDAT) o... more This paper presents an integrated system for automatic diagnostic on power transformers (SIDAT) of substations. SIDAT performs diagnosis based on several kinds of tests such as thermography images, chromatography, physical-chemical, and electrical. SIDAT also performs prognostic indicating the time life of the equipment. The inference engine for diagnostic is based on rules of the maintenance department of the company and it has been designed as a set Mealy Finite State Machines (FSMs). The system has been tested and evaluated with data coming from a production environment and stores data of 157 power transformers (13.8kVA and 34.5kVA) located in 94 different substations.

2012 10th IEEE/IAS International Conference on Industry Applications, 2012

2009 39th International Symposium on Multiple-Valued Logic, 2009

The synthesis and simplification of digital circuits are performed in the well known two level lo... more The synthesis and simplification of digital circuits are performed in the well known two level logic switching algebra. By increasing the representation domain to B levels it is possible to design multiple-valued logic (MV Logic) digital circuits. This work proposes an algebra based on a universal set of gates which carry out operators to allow synthesis and simplification of MV

Ingeniare. Revista chilena de ingeniería, 2013

Extensões do Quad-tree para a estimação do mapa denso de disparidade utilizando a luminância no d... more Extensões do Quad-tree para a estimação do mapa denso de disparidade utilizando a luminância no domínio real foram propostas na literatura. A contribuição deste trabalho é a comparação do processamento de imagens estéreo entre o algoritmo que é uma extensão do Quad-tree para processar imagens no domínio real utilizando a luminância, com o algoritmo, aqui proposto, que é a extensão do Quad-tree para processar imagens codificadas no domínio da álgebra de Clifford utilizando imagens coloridas do modelo YUV. O mapa denso de disparidade é obtido resolvendo o problema da correspondência para cada pixel entre o par estereoscópico. O problema da correspondência é fundamental e apresenta dificuldades devido à presença de áreas oclusas, ruídos e variações na iluminação, etc. A álgebra de Clifford é utilizada para mapear os valores do modelo YUV de cada pixel nos vetores de base, compondo um número de Clifford. Neste domínio, geram-se resultados melhores para imagens que têm muitos objetos na cena, aqui definidas como complexas, se comparados com os obtidos sobre as imagens utilizando o domínio real sobre a luminância. Processando os pares estereoscópicos utilizados no algoritmo proposto no domínio real e no domínio de Clifford se demonstra, experimentalmente, a melhora obtida para imagens em cenas reais.

IEEE Transactions on Circuits and Systems I: Regular Papers, 2014

ABSTRACT The design of Multiple Valued Logic (MVL) digital circuits is performed by increasing th... more ABSTRACT The design of Multiple Valued Logic (MVL) digital circuits is performed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. Universal sets of MVL CMOS gates allow the synthesis and implementation of any MVL digital circuit. The main drawback of this approach is the lack of existing integrated circuits that implement the universal set of MVL gates. This paper deals with: 1) the design and implementation of a universal set of IC gates, CMOS 0.35 µm technology, that carry out extended AND operators: eAND1, eAND2, eAND3, Successor (SUC), and Maximum (MAX) operators to perform synthesis of any MVL digital circuits; and 2) the synthesis of an MVL multiplexer and latch memory circuits, based on the IC MVL gates, to illustrate the utilization of the proposed IC MVL gates for quaternary MVL. Implemented circuits demonstrate correct functionality of the implemented gates and feasibility of the MVL combinatorial and memory circuit design. The proposed gates allow designing MVL digital circuit taking advantage of the knowledge coming from the binary circuits. By using a methodology based on the boolean algebra, digital circuits designers can take advantage of it to decrease the design learn curve.

Estudio descriptivo transversal, usando con este fin, encuestas, entrevistas a agentes externos, ... more Estudio descriptivo transversal, usando con este fin, encuestas, entrevistas a agentes externos, muestra tomada de forma aleatoria por conglomerados, que para este estudio fueron directivos de centros de salud, enfermeras, medicos graduados y pacientes. Basadas en tres indicadores calificados segun estandares definidos por el CONEA. Resultados: al indicador 186: opinion de la comunidad respecto a la contribucion recibida de la institucion para el desarrollo socioeconomico, el valor es de 4.3 que corresponde a 61.7es decir una calificacion de buena. Al indicador 187, Grado de reconocimiento de la sociedad sobre la contribucion de la institucion en la formacion de principios y valores en la comunidad, el valor obtenido corresponde a 4,3 (62.4) es decir una calificacion de buena, expresando avances significativos. Al indicador 188: Apreciacion de la colectividad sobre la vitalodad institucional para su mejoramiento y desarrollo, la calificacion es de 4.6 que equivale a un 65.9. Finalme...