F. Hameau - Academia.edu (original) (raw)

Papers by F. Hameau

2021 51st European Microwave Conference (EuMC)

This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CM... more This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several g m -enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic g m of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP 3 is ―12 dBm for an input compression point of —21 dBm.

2021 51st European Microwave Conference (EuMC)

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020

This paper presents a sample & hold pulse envelope synthesis method and shows that only 5 (re... more This paper presents a sample & hold pulse envelope synthesis method and shows that only 5 (resp. 7) samples are necessary to respect the sidelobes rejection in adjacent channels of 18dB (resp. 20dB) required by the IEEE 802.15.4 (resp. 802.15.6) standard if a sample & hold Gaussian envelope is used. These required numbers of samples, which enable complexity reduction of IR-UWB emitters for IEEE standards, are validated using measurement results of a pulse synthesizer presented in this paper since a sidelobes rejection in adjacent channels of 21.8dB (resp. 21.4dB) is obtained when transmitting in the mandatory low band of the IEEE 802.15.4 (resp. 802.15.6) standard.

2017 11th European Conference on Antennas and Propagation (EUCAP), 2017

V-band integrated transceiver modules based on a multi-layer organic interposer technology are de... more V-band integrated transceiver modules based on a multi-layer organic interposer technology are developed for user terminal and access point applications in future 5G mobile networks with the objective to have an efficient, scalable and cost-effective architecture. The main design constraints and issues are discussed. A 10×10-mm2 transceiver module, designed for user-terminal applications, with separate Rx and Tx antennas is presented and exhibits more than 8.6 dBi antenna gain over the 60 GHz band. A 18.8×18.5-mm2 module integrating a transceiver IC, 4 phase shifter ICs and 2×4 antenna elements enables higher gain levels and beam-steering in Rx and Tx modes. This module offers 17.6 dBi antenna gain at 61 GHz and can be used as a sub-array to reach 26.6 dBi in a multi-module phased-array architecture composed of 2×4 sub-arrays.

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2016

For about a decade, Ultra-WideBand applications demonstrated its interest for radio and imaging a... more For about a decade, Ultra-WideBand applications demonstrated its interest for radio and imaging applications in the [3.1–4.9 GHz] frequency band. In order to carry out such applications in other frequency domains, the instantaneous frequency of the impulse signal is commonly used. This paper describes the design of an Instantaneous Frequency Measurement system in order to show its feasibility for Ultra-WideBand impulse radio radar and imaging applications. The integrated part of the system is constituted of a full-wave rectifier, a delay cell and an analog multiplier. These devices were designed in CMOS 130 nm technology and consumes 95.6 mW for a supply voltage of 1.2V. The post-layout simulations are shown in comparison to theoretical Matlab simulations in order to validate the proposed technique.

2015 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB), 2015

Current consumption of an IR-UWB receiver is reduced thanks to duty-cycling techniques applied to... more Current consumption of an IR-UWB receiver is reduced thanks to duty-cycling techniques applied to the full analog chain, thus benefiting from the impulsive nature of the signal. The coherent architecture performs down conversion by mixing the incoming pulse with a locally generated 2.75ns pulse template and needs only a 1GHz frequency synthesis instead of a power hungry 4 or 8 GHz LO. Duty cycling with sub-ns settling time enables up to 82% current savings for the front-end at a 15.6MHz pulse repetition frequency. To operate in a strong interference environment, an optional 4th order Gm-C filter may be switched on. The receiver for IR-UWB communications and ranging is implemented in CMOS 130nm and measurement results confirm the expectations.

2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 2016

This paper presents some techniques to synthesize pulses in the context of IR-UWB. Pulse synthesi... more This paper presents some techniques to synthesize pulses in the context of IR-UWB. Pulse synthesizers are good candidates when different kinds of pulses are needed to comply with different standards or when the shape of the pulses needs to be modified. Two different approaches are described here. Voltage Controlled Delay Line (VCDL) based pulses are first described. For this family, two kinds of combiners are presented: differential pairs based and H-bridge based. The second one achieves a larger output dynamic but is limited by the use of the VCDL. A second type of H-bridge based synthesizer using VCO is presented. Using both a VCO and a H-Bridge offers the largest synthesis capabilities since it allows large voltage pulses to be synthesized and the pulse duration is not limited. All proposed architectures have been implemented and their measured performances are given for comparison.

IEEE Access, 2021

This work presents and analyses the design of a multi-mode Low Noise Amplifier (LNA) dedicated to... more This work presents and analyses the design of a multi-mode Low Noise Amplifier (LNA) dedicated to 2.4 GHz Wireless Sensor Network (WSN) applications. The proposed inductorless LNA, implemented in a 28 nm FDSOI CMOS technology, is based on a common-gate configuration imbedded with a common-source stage to boost the overall transconductance of the circuit. The LNA is specifically designed, and optimized, to address three modes of operation. The reconfiguration is performed through current tuning, combined with switching the back gate of the amplification transistors. The proposed implementation allows the figure of merit (FOM) to be maintained constant in the different modes of operation. In the low power mode, the LNA only consumes 350 uW. It achieves a voltage gain (G v) of 16.8 dB and a noise figure (NF) of 6.6 dB. In the medium performance mode, the gain and the NF are respectively improved to 19.4 dB and 5.4 dB, the power consumption is 0.9 mW. In the high-performance mode, the gain is maximum, 22.9 dB, and the noise figure is minimum, 3.6 dB, for a power consumption of 2 mW. The linearity represented by the input referred third-order intercept point (IIP3) is constant, close to −16 dBm. The reported LNA occupies only 0.0015 mm 2. INDEX TERMS RF low power, low noise amplifier, inversion coefficient.

Interest in SOI technology has been increased due to recent progress in modeling parasitic effect... more Interest in SOI technology has been increased due to recent progress in modeling parasitic effects needed for analog IC design. In this paper a brief overview of the SOI technology is done. A user compiled model built for ADS is then described before the analysis of 2 RF designs: a wideband Low Noise Amplifier (300MHz-900MHz with more than 10dB gain and 5dBm IIP3) and an antenna switch (with 0.5dB insertion loss and more than 50dB isolation) on the same bandwidth.

2010 IEEE International Conference on Integrated Circuit Design and Technology, 2010

ABSTRACT In this paper we present a new method for controlling the performance of a Differential ... more ABSTRACT In this paper we present a new method for controlling the performance of a Differential Active Inductor (DAI) used as resonating output load of an RF amplifier and working at Ultra Low Power (ULP) consumption. A new solution is proposed for linearity improvement without extra power consumption and without SNR degradation. For a given impedance value at the resonance frequency of the DAI (corresponding to a given amplifier gain), tradeoff between quality factor Q and IIP3 is highlighted. Then, an optimization method is proposed which takes into account the power consumption. A simulated DAI presents -2.7 dBm IIP3, 40 nV/Hz noise voltage density and almost 3.0 kΩ load at the resonance frequency of 2.45 GHz. The total power consumption is 0.8 mW under 1 V power supply of a 65 nm CMOS technology, and the circuit occupies 0.0012 mm2 of silicon area.

2005 IEEE International Conference on Ultra-Wideband

ABSTRACT New architectures, dedicated to UWB low data rate systems, such as for instance, peak de... more ABSTRACT New architectures, dedicated to UWB low data rate systems, such as for instance, peak detection or energy detection focus on power saving. In this context, a LNA with ideal flat gain response over the whole bandwidth [3 GHz-5 GHz] is no more mandatory. This paper proposes a new approach, which relies on a matched amplification to the input pulse. This technique enables to increase gain up to 7.7 dB for a given consumption. A simulated CMOS design based on common source amplifier with inductive degeneration is presented for illustration. Energetic gain is close to 15 dB with a minimum noise figure of 2.3 dB and an input IP1 of 11.4 dBm. Core of the LNA dissipates less than 2.6 mW.

2006 IEEE International Symposium on Circuits and Systems

ABSTRACT In this paper, the problematic of co-design between LNA and antenna is addressed. The ta... more ABSTRACT In this paper, the problematic of co-design between LNA and antenna is addressed. The targeted application is ultra wide band where this part of front end is a main interest in RF design. A comparison is drawn out between a 50 Ohm and a co-designed version, with same LNA architecture and power consumption. Simulation results show a 7 dB power gain enhancement in the latter version. Noise factor is improved by more than 1.5 dB over the whole bandwidth

2009 IEEE International Symposium on Circuits and Systems, 2009

We present a method to automatically match a system to the load variation accurately with a very ... more We present a method to automatically match a system to the load variation accurately with a very short matching time for ultra low power medical applications. A demonstrator was fabricated and an experimental set-up in the medical implant communication system (MICS) frequency band of 402-405 MHz was realized including a pacemaker antenna prototype immersed on a homogeneous lossy liquid. The

2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, 2009

... The design of an automatic matching system has been proposed and simulated on the 2.4GHzISM f... more ... The design of an automatic matching system has been proposed and simulated on the 2.4GHzISM frequency band. ... REFERENCES [1] A. van bezooijen, M. de Jongh, C. Chanlo, LCH Ruijis, F. Mahmoudi, AHM Van Roermund, “A GSM/EDGE/WCDMA adaptative series-LC ...

2011 IEEE Radio Frequency Integrated Circuits Symposium, 2011

ABSTRACT This paper presents an inductorless low power (LP) low noise amplifier (LNA) based on a ... more ABSTRACT This paper presents an inductorless low power (LP) low noise amplifier (LNA) based on a Common Gate (CG) topology. The circuit combines gain boosting techniques to enable high gain LP LNA. The circuit is integrated in a 130nm CMOS technology and shows 20dB gain with 4dB Noise Figure and -12dBm IIP3. The power consumption is 1.32mW from a 1.2V supply.

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006

ABSTRACT This paper presents on overview of the two chip integration of a digital radio receiver ... more ABSTRACT This paper presents on overview of the two chip integration of a digital radio receiver for wireless communication systems based on ultra wideband (UWB) impulse radio technology. The chips have been integrated in a 130 nm CMOS technology. The front-end performs 1-bit direct sampling of the RF signal. The baseband processing is implemented in a FPGA. The UWB link demonstration runs at 78.125Mpulse/s using polarity and a coding rate of 1/2 which gives a maximum information data rate of 39.1Mb/s (limited by the highest FPGA demodulation rate).

2008 IEEE Radio Frequency Integrated Circuits Symposium, 2008

A fully integrated 2.4GHz transceiver based on the IEEE802.15.4 specification has been designed u... more A fully integrated 2.4GHz transceiver based on the IEEE802.15.4 specification has been designed using a 130nm CMOS technology. Concurrent system and design optimizations were required to reach an energy efficiency of 21.5nJ/bit in RX mode and 32.5nJ/bit in TX modes, respectively, at a data rate of 250kbit/s. The circuit includes a-5dBm transmitter, a-81dBm sensitivity receiver, an integer N PLL with 5MHz reference, a dual I/Q 3-bit ADC at 4MS/s, an analog RSSI with 8-bit ADC at 8kS/s and an integrated SPDT TX/RX switch to a 100 Ω differential antenna port. The chip consumes 5.4mW in RX mode and 8.1mW in TX mode under 1.2V.

ESSCIRC 2008 - 34th European Solid-State Circuits Conference, 2008

An ultra-low power (ULP) SoC including an IEEE802.15.4 2.4 GHz transceiver designed in 130 nm CMO... more An ultra-low power (ULP) SoC including an IEEE802.15.4 2.4 GHz transceiver designed in 130 nm CMOS technology is presented. Power consumption was minimized by using a concurrent system and design optimization to avoid the over-specification of blocks. A novel minimum complexity partial correlation algorithm is used in the digital baseband receiver and drains an average of 4802 A (packet PSDU=20

IEEE Journal of Solid-State Circuits, 2012

ABSTRACT This paper presents the design of a low power differential Low Noise Amplifier (LNA) in ... more ABSTRACT This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several rmgrmm{\rm g} _{\rm m}rmgrmm-enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic rmgrmm{\rm g} _{\rm m}rmgrmm of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The rmIIP3{\rm IIP}_{3}rmIIP3 is −12rmdBm˜-12 ~{\rm dBm}−12rmdBm˜ for an input compression point of −21rmdBm˜-21 ~{\rm dBm}−21rmdBm˜.

2021 51st European Microwave Conference (EuMC)

This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CM... more This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several g m -enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic g m of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP 3 is ―12 dBm for an input compression point of —21 dBm.

2021 51st European Microwave Conference (EuMC)

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020

This paper presents a sample & hold pulse envelope synthesis method and shows that only 5 (re... more This paper presents a sample & hold pulse envelope synthesis method and shows that only 5 (resp. 7) samples are necessary to respect the sidelobes rejection in adjacent channels of 18dB (resp. 20dB) required by the IEEE 802.15.4 (resp. 802.15.6) standard if a sample & hold Gaussian envelope is used. These required numbers of samples, which enable complexity reduction of IR-UWB emitters for IEEE standards, are validated using measurement results of a pulse synthesizer presented in this paper since a sidelobes rejection in adjacent channels of 21.8dB (resp. 21.4dB) is obtained when transmitting in the mandatory low band of the IEEE 802.15.4 (resp. 802.15.6) standard.

2017 11th European Conference on Antennas and Propagation (EUCAP), 2017

V-band integrated transceiver modules based on a multi-layer organic interposer technology are de... more V-band integrated transceiver modules based on a multi-layer organic interposer technology are developed for user terminal and access point applications in future 5G mobile networks with the objective to have an efficient, scalable and cost-effective architecture. The main design constraints and issues are discussed. A 10×10-mm2 transceiver module, designed for user-terminal applications, with separate Rx and Tx antennas is presented and exhibits more than 8.6 dBi antenna gain over the 60 GHz band. A 18.8×18.5-mm2 module integrating a transceiver IC, 4 phase shifter ICs and 2×4 antenna elements enables higher gain levels and beam-steering in Rx and Tx modes. This module offers 17.6 dBi antenna gain at 61 GHz and can be used as a sub-array to reach 26.6 dBi in a multi-module phased-array architecture composed of 2×4 sub-arrays.

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2016

For about a decade, Ultra-WideBand applications demonstrated its interest for radio and imaging a... more For about a decade, Ultra-WideBand applications demonstrated its interest for radio and imaging applications in the [3.1–4.9 GHz] frequency band. In order to carry out such applications in other frequency domains, the instantaneous frequency of the impulse signal is commonly used. This paper describes the design of an Instantaneous Frequency Measurement system in order to show its feasibility for Ultra-WideBand impulse radio radar and imaging applications. The integrated part of the system is constituted of a full-wave rectifier, a delay cell and an analog multiplier. These devices were designed in CMOS 130 nm technology and consumes 95.6 mW for a supply voltage of 1.2V. The post-layout simulations are shown in comparison to theoretical Matlab simulations in order to validate the proposed technique.

2015 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB), 2015

Current consumption of an IR-UWB receiver is reduced thanks to duty-cycling techniques applied to... more Current consumption of an IR-UWB receiver is reduced thanks to duty-cycling techniques applied to the full analog chain, thus benefiting from the impulsive nature of the signal. The coherent architecture performs down conversion by mixing the incoming pulse with a locally generated 2.75ns pulse template and needs only a 1GHz frequency synthesis instead of a power hungry 4 or 8 GHz LO. Duty cycling with sub-ns settling time enables up to 82% current savings for the front-end at a 15.6MHz pulse repetition frequency. To operate in a strong interference environment, an optional 4th order Gm-C filter may be switched on. The receiver for IR-UWB communications and ranging is implemented in CMOS 130nm and measurement results confirm the expectations.

2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 2016

This paper presents some techniques to synthesize pulses in the context of IR-UWB. Pulse synthesi... more This paper presents some techniques to synthesize pulses in the context of IR-UWB. Pulse synthesizers are good candidates when different kinds of pulses are needed to comply with different standards or when the shape of the pulses needs to be modified. Two different approaches are described here. Voltage Controlled Delay Line (VCDL) based pulses are first described. For this family, two kinds of combiners are presented: differential pairs based and H-bridge based. The second one achieves a larger output dynamic but is limited by the use of the VCDL. A second type of H-bridge based synthesizer using VCO is presented. Using both a VCO and a H-Bridge offers the largest synthesis capabilities since it allows large voltage pulses to be synthesized and the pulse duration is not limited. All proposed architectures have been implemented and their measured performances are given for comparison.

IEEE Access, 2021

This work presents and analyses the design of a multi-mode Low Noise Amplifier (LNA) dedicated to... more This work presents and analyses the design of a multi-mode Low Noise Amplifier (LNA) dedicated to 2.4 GHz Wireless Sensor Network (WSN) applications. The proposed inductorless LNA, implemented in a 28 nm FDSOI CMOS technology, is based on a common-gate configuration imbedded with a common-source stage to boost the overall transconductance of the circuit. The LNA is specifically designed, and optimized, to address three modes of operation. The reconfiguration is performed through current tuning, combined with switching the back gate of the amplification transistors. The proposed implementation allows the figure of merit (FOM) to be maintained constant in the different modes of operation. In the low power mode, the LNA only consumes 350 uW. It achieves a voltage gain (G v) of 16.8 dB and a noise figure (NF) of 6.6 dB. In the medium performance mode, the gain and the NF are respectively improved to 19.4 dB and 5.4 dB, the power consumption is 0.9 mW. In the high-performance mode, the gain is maximum, 22.9 dB, and the noise figure is minimum, 3.6 dB, for a power consumption of 2 mW. The linearity represented by the input referred third-order intercept point (IIP3) is constant, close to −16 dBm. The reported LNA occupies only 0.0015 mm 2. INDEX TERMS RF low power, low noise amplifier, inversion coefficient.

Interest in SOI technology has been increased due to recent progress in modeling parasitic effect... more Interest in SOI technology has been increased due to recent progress in modeling parasitic effects needed for analog IC design. In this paper a brief overview of the SOI technology is done. A user compiled model built for ADS is then described before the analysis of 2 RF designs: a wideband Low Noise Amplifier (300MHz-900MHz with more than 10dB gain and 5dBm IIP3) and an antenna switch (with 0.5dB insertion loss and more than 50dB isolation) on the same bandwidth.

2010 IEEE International Conference on Integrated Circuit Design and Technology, 2010

ABSTRACT In this paper we present a new method for controlling the performance of a Differential ... more ABSTRACT In this paper we present a new method for controlling the performance of a Differential Active Inductor (DAI) used as resonating output load of an RF amplifier and working at Ultra Low Power (ULP) consumption. A new solution is proposed for linearity improvement without extra power consumption and without SNR degradation. For a given impedance value at the resonance frequency of the DAI (corresponding to a given amplifier gain), tradeoff between quality factor Q and IIP3 is highlighted. Then, an optimization method is proposed which takes into account the power consumption. A simulated DAI presents -2.7 dBm IIP3, 40 nV/Hz noise voltage density and almost 3.0 kΩ load at the resonance frequency of 2.45 GHz. The total power consumption is 0.8 mW under 1 V power supply of a 65 nm CMOS technology, and the circuit occupies 0.0012 mm2 of silicon area.

2005 IEEE International Conference on Ultra-Wideband

ABSTRACT New architectures, dedicated to UWB low data rate systems, such as for instance, peak de... more ABSTRACT New architectures, dedicated to UWB low data rate systems, such as for instance, peak detection or energy detection focus on power saving. In this context, a LNA with ideal flat gain response over the whole bandwidth [3 GHz-5 GHz] is no more mandatory. This paper proposes a new approach, which relies on a matched amplification to the input pulse. This technique enables to increase gain up to 7.7 dB for a given consumption. A simulated CMOS design based on common source amplifier with inductive degeneration is presented for illustration. Energetic gain is close to 15 dB with a minimum noise figure of 2.3 dB and an input IP1 of 11.4 dBm. Core of the LNA dissipates less than 2.6 mW.

2006 IEEE International Symposium on Circuits and Systems

ABSTRACT In this paper, the problematic of co-design between LNA and antenna is addressed. The ta... more ABSTRACT In this paper, the problematic of co-design between LNA and antenna is addressed. The targeted application is ultra wide band where this part of front end is a main interest in RF design. A comparison is drawn out between a 50 Ohm and a co-designed version, with same LNA architecture and power consumption. Simulation results show a 7 dB power gain enhancement in the latter version. Noise factor is improved by more than 1.5 dB over the whole bandwidth

2009 IEEE International Symposium on Circuits and Systems, 2009

We present a method to automatically match a system to the load variation accurately with a very ... more We present a method to automatically match a system to the load variation accurately with a very short matching time for ultra low power medical applications. A demonstrator was fabricated and an experimental set-up in the medical implant communication system (MICS) frequency band of 402-405 MHz was realized including a pacemaker antenna prototype immersed on a homogeneous lossy liquid. The

2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, 2009

... The design of an automatic matching system has been proposed and simulated on the 2.4GHzISM f... more ... The design of an automatic matching system has been proposed and simulated on the 2.4GHzISM frequency band. ... REFERENCES [1] A. van bezooijen, M. de Jongh, C. Chanlo, LCH Ruijis, F. Mahmoudi, AHM Van Roermund, “A GSM/EDGE/WCDMA adaptative series-LC ...

2011 IEEE Radio Frequency Integrated Circuits Symposium, 2011

ABSTRACT This paper presents an inductorless low power (LP) low noise amplifier (LNA) based on a ... more ABSTRACT This paper presents an inductorless low power (LP) low noise amplifier (LNA) based on a Common Gate (CG) topology. The circuit combines gain boosting techniques to enable high gain LP LNA. The circuit is integrated in a 130nm CMOS technology and shows 20dB gain with 4dB Noise Figure and -12dBm IIP3. The power consumption is 1.32mW from a 1.2V supply.

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006

ABSTRACT This paper presents on overview of the two chip integration of a digital radio receiver ... more ABSTRACT This paper presents on overview of the two chip integration of a digital radio receiver for wireless communication systems based on ultra wideband (UWB) impulse radio technology. The chips have been integrated in a 130 nm CMOS technology. The front-end performs 1-bit direct sampling of the RF signal. The baseband processing is implemented in a FPGA. The UWB link demonstration runs at 78.125Mpulse/s using polarity and a coding rate of 1/2 which gives a maximum information data rate of 39.1Mb/s (limited by the highest FPGA demodulation rate).

2008 IEEE Radio Frequency Integrated Circuits Symposium, 2008

A fully integrated 2.4GHz transceiver based on the IEEE802.15.4 specification has been designed u... more A fully integrated 2.4GHz transceiver based on the IEEE802.15.4 specification has been designed using a 130nm CMOS technology. Concurrent system and design optimizations were required to reach an energy efficiency of 21.5nJ/bit in RX mode and 32.5nJ/bit in TX modes, respectively, at a data rate of 250kbit/s. The circuit includes a-5dBm transmitter, a-81dBm sensitivity receiver, an integer N PLL with 5MHz reference, a dual I/Q 3-bit ADC at 4MS/s, an analog RSSI with 8-bit ADC at 8kS/s and an integrated SPDT TX/RX switch to a 100 Ω differential antenna port. The chip consumes 5.4mW in RX mode and 8.1mW in TX mode under 1.2V.

ESSCIRC 2008 - 34th European Solid-State Circuits Conference, 2008

An ultra-low power (ULP) SoC including an IEEE802.15.4 2.4 GHz transceiver designed in 130 nm CMO... more An ultra-low power (ULP) SoC including an IEEE802.15.4 2.4 GHz transceiver designed in 130 nm CMOS technology is presented. Power consumption was minimized by using a concurrent system and design optimization to avoid the over-specification of blocks. A novel minimum complexity partial correlation algorithm is used in the digital baseband receiver and drains an average of 4802 A (packet PSDU=20

IEEE Journal of Solid-State Circuits, 2012

ABSTRACT This paper presents the design of a low power differential Low Noise Amplifier (LNA) in ... more ABSTRACT This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several rmgrmm{\rm g} _{\rm m}rmgrmm-enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic rmgrmm{\rm g} _{\rm m}rmgrmm of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The rmIIP3{\rm IIP}_{3}rmIIP3 is −12rmdBm˜-12 ~{\rm dBm}−12rmdBm˜ for an input compression point of −21rmdBm˜-21 ~{\rm dBm}−21rmdBm˜.