Fabrice Seguin - Academia.edu (original) (raw)

Papers by Fabrice Seguin

15th International Conference on Microwaves, Radar and Wireless Communications (IEEE Cat. No.04EX824)

Abstract - A novel current-mode BiCMOS Low-Noise Amplifier is compared to conventional voltage-mo... more Abstract - A novel current-mode BiCMOS Low-Noise Amplifier is compared to conventional voltage-mode topologies, emphasising on performance at 900MHz. Rivalling classical designs in performance, this new design has the added advantage of controllable gain. ...

IEEE Sensors Journal, 2021

Most current eye-trackers are camera-based and rely on image processing. To improve gaze tracking... more Most current eye-trackers are camera-based and rely on image processing. To improve gaze tracking accuracy, this paper presents a new approach based on a camera-less gaze tracking system using a smart contact lens. A scleral lens is fitted with photodetectors illuminated by specific spectacles. Photo-currents vary with eye movements as the light photodetectors received varies. The gaze direction is obtained then by computing a barycenter from the photocurrents by means of an integrated circuit implemented on the lens and powered using an inductive link. Experimental measurements with a prototype lens fitted with four infrared photodiodes and mounted on an artificial eyeball validate the method. Designed for the AMS 0.35-µm CMOS process, a 170 µW integrated circuit is proposed, including a subthreshold analog barycenter computation unit and an analog-todigital converter. Monte Carlo analysis based on the circuit layout and measured photo-currents shows an accuracy of 0.2 • can be achieved. This is 2.5 times better than current camera-based eye-trackers.

2018 IEEE SENSORS, 2018

This paper presents a cost effective electronic nose prototype for the detection of 1.6 ppm of di... more This paper presents a cost effective electronic nose prototype for the detection of 1.6 ppm of dimethyl methylphosphonate (DMMP) in a complex background. The device comprises of seven cross-sensitive carbon nanotube mat (CNT-mat) type sensors, an impedance measurement circuit and a microcomputer for data pre-treatment and classification stages. This study focused on the detection of DMMP in a gas mixture, using the responses of the sensors before they reach a stable and repeatable behavior. Even with this major constraint, the support vector machine used for classification reached 98% precision for the recognition of the samples.

Optics Express, 2020

Most eye trackers nowadays are video-based, which allows for a relatively simple and non-invasive... more Most eye trackers nowadays are video-based, which allows for a relatively simple and non-invasive approach but also imposes several constraints in terms of necessary computing power and conditions of use (e.g., lighting, spectacles, etc.). We introduce a new eye tracker using a scleral lens equipped with photodiodes and an eyewear with active illumination. The direction of gaze is obtained from the weighted average of photocurrents (centroid) and communicated through an optical link. After discussing the optimum photodiodes configuration (number, layout) and associated lighting (collimated, Lambertian), we present prototypes demonstrating the high performances possibilities (0.11° accuracy when placed on an artificial eye) and wireless optical communication.

IEEE Transactions on Circuits and Systems I: Regular Papers, 2018

Clique-based neural networks implement lowcomplexity functions working with a reduced connectivit... more Clique-based neural networks implement lowcomplexity functions working with a reduced connectivity between neurons. Thus, they address very specific applications operating with a very low-energy budget. However, the implementation in the state of the art is not flexible and a fabricated circuit is only usable in a unique use case. Besides, the silicon area of hardwired circuits grows exponentially with the number of implemented neurons that is prohibitive for embedded applications. This paper proposes a flexible and iterative neural architecture capable of implementing multiple types of clique-based neural networks of up to 3968 neurons. The circuit has been integrated in an ST 65-nm CMOS ASIC and occupies a 0.21-mm 2 silicon surface area. The proper functioning of the circuit is illustrated using two application cases: a keyword recovery application and an electrocardiogram classification. The neurons outputs are updated 83 ns after a stimulation, and a neuron needs an energy of 115 fJ to propagate a change at the input to its output.

2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 2016

Body Area Sensor Networks (BASN) are expected to provide a way to improve medical care while redu... more Body Area Sensor Networks (BASN) are expected to provide a way to improve medical care while reducing its costs. Reducing their energy consumption is a critical step before building reliable and durable systems. Acquisition and classification of Electrocardiogram (ECG) signals is a central task in medical BASNs. This paper introduces a method to perform the classification between three abnormal types of heart beats at ultra-low power using Sparse Neural Associative Memories (SNAM). Based on recent analog implementation of a SNAM node using the ST CMOS 65 nm design kit, the proposed SNAM uses only 864 fJ per classification. Compared to a digital ultra-low power multi-core architecture, this SNAM consumes several orders of magnitude less energy while achieving classification accuracy of 93.5 %.

IEEE transactions on neural networks and learning systems, Jan 26, 2015

Associative memories are data structures that allow retrieval of previously stored messages given... more Associative memories are data structures that allow retrieval of previously stored messages given part of their content. They, thus, behave similarly to the human brain's memory that is capable, for instance, of retrieving the end of a song, given its beginning. Among different families of associative memories, sparse ones are known to provide the best efficiency (ratio of the number of bits stored to that of the bits used). Recently, a new family of sparse associative memories achieving almost optimal efficiency has been proposed. Their structure, relying on binary connections and neurons, induces a direct mapping between input messages and stored patterns. Nevertheless, it is well known that nonuniformity of the stored messages can lead to a dramatic decrease in performance. In this paper, we show the impact of nonuniformity on the performance of this recent model, and we exploit the structure of the model to improve its performance in practical applications, where data are no...

IEEE Transactions on Circuits and Systems II: Express Briefs, 2016

Traditional memories use an address to index the stored data. Associative memories rely on a diff... more Traditional memories use an address to index the stored data. Associative memories rely on a different principle: Part of previously stored data are used to retrieve the remaining part. They are widely used, for instance, in network routers for packet forwarding. A classical way to implement such memories is content-addressable memory (CAM). Since its operation is fully parallel, the response is obtained in a single clock cycle. However, this comes at the cost of energy consumption. This brief proposes to use a recent type of neural networks as a novel way to implement associative memories. Owing to an efficient retrieval algorithm guided by the information being searched, they are a good candidate for low-power associative memory. Compared to the CAM-based system, the analog implementation of 12-kb neuro-inspired memory designed for 65-nm CMOS technology offers 48% energy savings.

IEEE Transactions on Microwave Theory and Techniques, 2015

The aim of this paper is to show the possibility to harvest RF energy to supply wireless sensor n... more The aim of this paper is to show the possibility to harvest RF energy to supply wireless sensor networks in an outdoor environment. In those conditions, the number of existing RF bands is unpredictable. The RF circuit has to harvest all the potential RF energy present and cannot be designed for a single RF tone. In this paper, the designed RF harvester adds powers coming from an unlimited number of sub-frequency bands. The harvester's output voltage ratios increase with the number of RF bands. As an application example, a 4-RF band rectenna is designed. The system harvests energy from GSM900 (Global System for Mobile Communications), GSM1800, UMTS (Universal Mobile Telecommunications System) and WiFi bands simultaneously. RF-to-dc conversion efficiency is measured at 62% for a cumulative 10-dBm input power homogeneously widespread over the four RF bands and reaches 84% at 5.8 dBm. The relative error between the measured dc output power with all four RF bands ON and the ideal sum of each of the four RF bands power contribution is less than 3%. It is shown that the RF-to-dc conversion efficiency is more than doubled compared to that measured with a single RF source, thanks to the proposed rectifier architecture.

2013 Loughborough Antennas & Propagation Conference (LAPC), 2013

ABSTRACT

2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 2008

This paper analyses the effect of inherent bipolar transistor parasitic elements over the computi... more This paper analyses the effect of inherent bipolar transistor parasitic elements over the computing nodes performance used in BJT analog decoders. It is shown that these undesirable effects significantly degrade, up to 85%, the conversion of Log-Likelihood Ratios into probabilities. This can lead to a wrong decoding outcome when complex computing nodes are designed. Simulation results are shown for a 0.25-µm BiCMOS process from NXP. I.

2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, 2009

ABSTRACT

2010 6th International Symposium on Turbo Codes & Iterative Information Processing, 2010

ABSTRACT This paper presents an analog decoder computing cell less sensitive to bipolar junction ... more ABSTRACT This paper presents an analog decoder computing cell less sensitive to bipolar junction transistor (BJT) parasitic elements. Unlike customary cells, the proposed cell does not invert the output probabilities ranking, hence limiting the wrong decoding outcome. This is achieved with a slight complexity increase as only two diodes are added to the basic computing cell. It is also shown that the proposed cell can improve the decoding performance even for large biasing current, opening the way to improve the decoding convergence of an analog BiCMOS decoder. Simulation results are shown for a 0.25-μm BiCMOS process from NXP with minimal size transistors.

Une réalisation de décodeur analogique de codes convolutifs duo-binaires est proposée pour une ap... more Une réalisation de décodeur analogique de codes convolutifs duo-binaires est proposée pour une application industrielle (la norme DVB-RCS). L'utilisation des caractéristiques exponentielles des transistors bipolaires a permis d'implanter l'algorithme MAP dans une technologie Philips BiCMOS SiGe 0,25µm. Des simulationsélectriques ont validé le décodage d'une trame de 24 symboles duo-binaires. L'utilisation de ce décodeurélémentaire dans une structure "turbo" est ensuite envisagée afin de fournir un décodeur complet. Des simulations comportementales montrent une amélioration des performances de décodage allant jusqu'à 0,1dB (pour un taux d'erreur binaire de 10 −4) par rapportà une structure numériqueéquivalente.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2014

Higher density of integration and lower power technologies are becoming more sensitive to soft er... more Higher density of integration and lower power technologies are becoming more sensitive to soft errors caused by radiations. Not only memories and latches are being affected but also combinatorial circuits. Hardening by design techniques based on increasing the amount of charge representing the bit and redundancy techniques have been used over the years. However, what happens if the hardening is affected? Who guards the guardians? This brief proposes a system that acts as a single-event transient (SET) filter and as a checkpoint with self-healing properties to prevent SET propagation. This is achieved due to feedback using bulk built-in current sensors.

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013

This paper presents a sensitivity study to ionizing particles, which are caused by cosmic rays, o... more This paper presents a sensitivity study to ionizing particles, which are caused by cosmic rays, on a particular combinatorial function of an ST 65nm CMOS technology SAR ADC. A methodology for this study is exposed along with the simulation results. A geometrical visualization of the impacts shows the influence of the impact location effects on the function during operation. An ADC operating cycle analysis is made related to the impact effects showing combinatorial and memorization errors.

Analog Integrated Circuits and Signal Processing, 2014

Encoded neural networks (ENN) combine the principles of associative memories and error correcting... more Encoded neural networks (ENN) combine the principles of associative memories and error correcting decoders. Thus, they are good candidates to solve problems where decisions have to be made based on partial input information. This paper introduces an analog implementation of this new type of network to manage the power distribution in a Multiprocessor System-on-Chip (MPSoC). The proposed circuit has been designed for the 1 V supply ST CMOS 65 nm process, with a low complexity and low power consumption (less than 1 % of the MPSoC power). Compared to a digital counterpart based on game theory (GT), this analog solution consumes 6,800 times less energy and reacts 4,500 times faster. Thus, this analog circuit allows fully exploiting dynamic voltage and frequency scaling circuits switching capabilities to continuously adapt the power distribution of an MPSoC. From a given energy budget, GT saves 38 % while the analog ENN saves 60 %.

2005 IEEE International Symposium on Circuits and Systems

This paper presents the design of an analog turbo decoder for the DVB-RCS standard. It uses a sli... more This paper presents the design of an analog turbo decoder for the DVB-RCS standard. It uses a slice architecture which enhances the design in terms of simplicity, robustness, testability and reusability. Transistor-level simulations show potential throughput up to 1.2Gb/s for a 2.8mW power consumption per information bit and per state in a 0.25µm BiCMOS process.

15th International Conference on Microwaves, Radar and Wireless Communications (IEEE Cat. No.04EX824)

Abstract - A novel current-mode BiCMOS Low-Noise Amplifier is compared to conventional voltage-mo... more Abstract - A novel current-mode BiCMOS Low-Noise Amplifier is compared to conventional voltage-mode topologies, emphasising on performance at 900MHz. Rivalling classical designs in performance, this new design has the added advantage of controllable gain. ...

IEEE Sensors Journal, 2021

Most current eye-trackers are camera-based and rely on image processing. To improve gaze tracking... more Most current eye-trackers are camera-based and rely on image processing. To improve gaze tracking accuracy, this paper presents a new approach based on a camera-less gaze tracking system using a smart contact lens. A scleral lens is fitted with photodetectors illuminated by specific spectacles. Photo-currents vary with eye movements as the light photodetectors received varies. The gaze direction is obtained then by computing a barycenter from the photocurrents by means of an integrated circuit implemented on the lens and powered using an inductive link. Experimental measurements with a prototype lens fitted with four infrared photodiodes and mounted on an artificial eyeball validate the method. Designed for the AMS 0.35-µm CMOS process, a 170 µW integrated circuit is proposed, including a subthreshold analog barycenter computation unit and an analog-todigital converter. Monte Carlo analysis based on the circuit layout and measured photo-currents shows an accuracy of 0.2 • can be achieved. This is 2.5 times better than current camera-based eye-trackers.

2018 IEEE SENSORS, 2018

This paper presents a cost effective electronic nose prototype for the detection of 1.6 ppm of di... more This paper presents a cost effective electronic nose prototype for the detection of 1.6 ppm of dimethyl methylphosphonate (DMMP) in a complex background. The device comprises of seven cross-sensitive carbon nanotube mat (CNT-mat) type sensors, an impedance measurement circuit and a microcomputer for data pre-treatment and classification stages. This study focused on the detection of DMMP in a gas mixture, using the responses of the sensors before they reach a stable and repeatable behavior. Even with this major constraint, the support vector machine used for classification reached 98% precision for the recognition of the samples.

Optics Express, 2020

Most eye trackers nowadays are video-based, which allows for a relatively simple and non-invasive... more Most eye trackers nowadays are video-based, which allows for a relatively simple and non-invasive approach but also imposes several constraints in terms of necessary computing power and conditions of use (e.g., lighting, spectacles, etc.). We introduce a new eye tracker using a scleral lens equipped with photodiodes and an eyewear with active illumination. The direction of gaze is obtained from the weighted average of photocurrents (centroid) and communicated through an optical link. After discussing the optimum photodiodes configuration (number, layout) and associated lighting (collimated, Lambertian), we present prototypes demonstrating the high performances possibilities (0.11° accuracy when placed on an artificial eye) and wireless optical communication.

IEEE Transactions on Circuits and Systems I: Regular Papers, 2018

Clique-based neural networks implement lowcomplexity functions working with a reduced connectivit... more Clique-based neural networks implement lowcomplexity functions working with a reduced connectivity between neurons. Thus, they address very specific applications operating with a very low-energy budget. However, the implementation in the state of the art is not flexible and a fabricated circuit is only usable in a unique use case. Besides, the silicon area of hardwired circuits grows exponentially with the number of implemented neurons that is prohibitive for embedded applications. This paper proposes a flexible and iterative neural architecture capable of implementing multiple types of clique-based neural networks of up to 3968 neurons. The circuit has been integrated in an ST 65-nm CMOS ASIC and occupies a 0.21-mm 2 silicon surface area. The proper functioning of the circuit is illustrated using two application cases: a keyword recovery application and an electrocardiogram classification. The neurons outputs are updated 83 ns after a stimulation, and a neuron needs an energy of 115 fJ to propagate a change at the input to its output.

2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 2016

Body Area Sensor Networks (BASN) are expected to provide a way to improve medical care while redu... more Body Area Sensor Networks (BASN) are expected to provide a way to improve medical care while reducing its costs. Reducing their energy consumption is a critical step before building reliable and durable systems. Acquisition and classification of Electrocardiogram (ECG) signals is a central task in medical BASNs. This paper introduces a method to perform the classification between three abnormal types of heart beats at ultra-low power using Sparse Neural Associative Memories (SNAM). Based on recent analog implementation of a SNAM node using the ST CMOS 65 nm design kit, the proposed SNAM uses only 864 fJ per classification. Compared to a digital ultra-low power multi-core architecture, this SNAM consumes several orders of magnitude less energy while achieving classification accuracy of 93.5 %.

IEEE transactions on neural networks and learning systems, Jan 26, 2015

Associative memories are data structures that allow retrieval of previously stored messages given... more Associative memories are data structures that allow retrieval of previously stored messages given part of their content. They, thus, behave similarly to the human brain's memory that is capable, for instance, of retrieving the end of a song, given its beginning. Among different families of associative memories, sparse ones are known to provide the best efficiency (ratio of the number of bits stored to that of the bits used). Recently, a new family of sparse associative memories achieving almost optimal efficiency has been proposed. Their structure, relying on binary connections and neurons, induces a direct mapping between input messages and stored patterns. Nevertheless, it is well known that nonuniformity of the stored messages can lead to a dramatic decrease in performance. In this paper, we show the impact of nonuniformity on the performance of this recent model, and we exploit the structure of the model to improve its performance in practical applications, where data are no...

IEEE Transactions on Circuits and Systems II: Express Briefs, 2016

Traditional memories use an address to index the stored data. Associative memories rely on a diff... more Traditional memories use an address to index the stored data. Associative memories rely on a different principle: Part of previously stored data are used to retrieve the remaining part. They are widely used, for instance, in network routers for packet forwarding. A classical way to implement such memories is content-addressable memory (CAM). Since its operation is fully parallel, the response is obtained in a single clock cycle. However, this comes at the cost of energy consumption. This brief proposes to use a recent type of neural networks as a novel way to implement associative memories. Owing to an efficient retrieval algorithm guided by the information being searched, they are a good candidate for low-power associative memory. Compared to the CAM-based system, the analog implementation of 12-kb neuro-inspired memory designed for 65-nm CMOS technology offers 48% energy savings.

IEEE Transactions on Microwave Theory and Techniques, 2015

The aim of this paper is to show the possibility to harvest RF energy to supply wireless sensor n... more The aim of this paper is to show the possibility to harvest RF energy to supply wireless sensor networks in an outdoor environment. In those conditions, the number of existing RF bands is unpredictable. The RF circuit has to harvest all the potential RF energy present and cannot be designed for a single RF tone. In this paper, the designed RF harvester adds powers coming from an unlimited number of sub-frequency bands. The harvester's output voltage ratios increase with the number of RF bands. As an application example, a 4-RF band rectenna is designed. The system harvests energy from GSM900 (Global System for Mobile Communications), GSM1800, UMTS (Universal Mobile Telecommunications System) and WiFi bands simultaneously. RF-to-dc conversion efficiency is measured at 62% for a cumulative 10-dBm input power homogeneously widespread over the four RF bands and reaches 84% at 5.8 dBm. The relative error between the measured dc output power with all four RF bands ON and the ideal sum of each of the four RF bands power contribution is less than 3%. It is shown that the RF-to-dc conversion efficiency is more than doubled compared to that measured with a single RF source, thanks to the proposed rectifier architecture.

2013 Loughborough Antennas & Propagation Conference (LAPC), 2013

ABSTRACT

2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 2008

This paper analyses the effect of inherent bipolar transistor parasitic elements over the computi... more This paper analyses the effect of inherent bipolar transistor parasitic elements over the computing nodes performance used in BJT analog decoders. It is shown that these undesirable effects significantly degrade, up to 85%, the conversion of Log-Likelihood Ratios into probabilities. This can lead to a wrong decoding outcome when complex computing nodes are designed. Simulation results are shown for a 0.25-µm BiCMOS process from NXP. I.

2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, 2009

ABSTRACT

2010 6th International Symposium on Turbo Codes & Iterative Information Processing, 2010

ABSTRACT This paper presents an analog decoder computing cell less sensitive to bipolar junction ... more ABSTRACT This paper presents an analog decoder computing cell less sensitive to bipolar junction transistor (BJT) parasitic elements. Unlike customary cells, the proposed cell does not invert the output probabilities ranking, hence limiting the wrong decoding outcome. This is achieved with a slight complexity increase as only two diodes are added to the basic computing cell. It is also shown that the proposed cell can improve the decoding performance even for large biasing current, opening the way to improve the decoding convergence of an analog BiCMOS decoder. Simulation results are shown for a 0.25-μm BiCMOS process from NXP with minimal size transistors.

Une réalisation de décodeur analogique de codes convolutifs duo-binaires est proposée pour une ap... more Une réalisation de décodeur analogique de codes convolutifs duo-binaires est proposée pour une application industrielle (la norme DVB-RCS). L'utilisation des caractéristiques exponentielles des transistors bipolaires a permis d'implanter l'algorithme MAP dans une technologie Philips BiCMOS SiGe 0,25µm. Des simulationsélectriques ont validé le décodage d'une trame de 24 symboles duo-binaires. L'utilisation de ce décodeurélémentaire dans une structure "turbo" est ensuite envisagée afin de fournir un décodeur complet. Des simulations comportementales montrent une amélioration des performances de décodage allant jusqu'à 0,1dB (pour un taux d'erreur binaire de 10 −4) par rapportà une structure numériqueéquivalente.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2014

Higher density of integration and lower power technologies are becoming more sensitive to soft er... more Higher density of integration and lower power technologies are becoming more sensitive to soft errors caused by radiations. Not only memories and latches are being affected but also combinatorial circuits. Hardening by design techniques based on increasing the amount of charge representing the bit and redundancy techniques have been used over the years. However, what happens if the hardening is affected? Who guards the guardians? This brief proposes a system that acts as a single-event transient (SET) filter and as a checkpoint with self-healing properties to prevent SET propagation. This is achieved due to feedback using bulk built-in current sensors.

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013

This paper presents a sensitivity study to ionizing particles, which are caused by cosmic rays, o... more This paper presents a sensitivity study to ionizing particles, which are caused by cosmic rays, on a particular combinatorial function of an ST 65nm CMOS technology SAR ADC. A methodology for this study is exposed along with the simulation results. A geometrical visualization of the impacts shows the influence of the impact location effects on the function during operation. An ADC operating cycle analysis is made related to the impact effects showing combinatorial and memorization errors.

Analog Integrated Circuits and Signal Processing, 2014

Encoded neural networks (ENN) combine the principles of associative memories and error correcting... more Encoded neural networks (ENN) combine the principles of associative memories and error correcting decoders. Thus, they are good candidates to solve problems where decisions have to be made based on partial input information. This paper introduces an analog implementation of this new type of network to manage the power distribution in a Multiprocessor System-on-Chip (MPSoC). The proposed circuit has been designed for the 1 V supply ST CMOS 65 nm process, with a low complexity and low power consumption (less than 1 % of the MPSoC power). Compared to a digital counterpart based on game theory (GT), this analog solution consumes 6,800 times less energy and reacts 4,500 times faster. Thus, this analog circuit allows fully exploiting dynamic voltage and frequency scaling circuits switching capabilities to continuously adapt the power distribution of an MPSoC. From a given energy budget, GT saves 38 % while the analog ENN saves 60 %.

2005 IEEE International Symposium on Circuits and Systems

This paper presents the design of an analog turbo decoder for the DVB-RCS standard. It uses a sli... more This paper presents the design of an analog turbo decoder for the DVB-RCS standard. It uses a slice architecture which enhances the design in terms of simplicity, robustness, testability and reusability. Transistor-level simulations show potential throughput up to 1.2Gb/s for a 2.8mW power consumption per information bit and per state in a 0.25µm BiCMOS process.