Fausto Pellandini - Academia.edu (original) (raw)

Papers by Fausto Pellandini

Research paper thumbnail of Efficient algorithm to compute LSP parameters from 10th-order LPC coefficients

Line Spectrum Pair (LSP) representation of Linear Predictive Coding (LPC) parameters is widely us... more Line Spectrum Pair (LSP) representation of Linear Predictive Coding (LPC) parameters is widely used in speech coding applications. An efficient method for LPC to LSP conversion is Kabal's method. In this method the LSPs are the roots of two polynomials P' p (x) and Q' p (x), and are found by a zero crossing search followed by successive bisections and interpolation. The precision of the obtained LSPs is higher than required by most applications, but the number of bisections cannot be decreased without compromising the zero crossing search. In this paper, it is shown that, in the case of 10 th-order LPC, five intervals containing each only one zero crossing of P' 10 (x) and one zero crossing of Q' 10 (x) can be calculated, avoiding the zero crossing search. This allows a trade-off between LSP precision and computational complexity resulting in considerable computational saving.

Research paper thumbnail of Design methodology for VLSI implementation of image and video coding algorithms

Research paper thumbnail of <title>Countering illumination variations in a video surveillance environment</title>

Proceedings of SPIE, May 8, 2001

Research paper thumbnail of Effective static response compensation suitable for low-power ASIC implementation with an application to pressure sensors

This paper presents an efficient all-digital compensation technique for sensors measuring static ... more This paper presents an efficient all-digital compensation technique for sensors measuring static or slowly-varying quantities such as pressure. The proposed solution compensates the temperature dependencies and further non-linearities affecting the accuracy and measure ment range of the sensors. In addition, for the considered pressure sensors, the trimming that is usually performed in factory can be replaced by a measure of the sensor characteristics to be used for the digital sensor compensation. The whole design procedure, starting from the description of the pressure sensors down to the low-power ASIC implementation of the processor architecture is discussed in detail.

Research paper thumbnail of Comparison of feature extraction techniques for face verification using elastic graph matching on low-power mobile devices

Biometric face verification using elastic graph matching is considered and two feature extraction... more Biometric face verification using elastic graph matching is considered and two feature extraction techniques used as a pre-processing stage are compared. Low-complexity vs. performance is of particular interest for mobile devices. A modified technique based on a normalization of mathematical morphology feature is introduced and show a performance comparable to that of Gabor features at a much-reduced computational complexity.

Research paper thumbnail of Architecture VLSI faible consommation pour le traitement numérique du signal

... D Ǘ • ••-D M&gt;^ Sorties (&quot;Q&quot;) des bascules Etat initial 1111 i 11111... more ... D Ǘ • ••-D M&gt;^ Sorties (&quot;Q&quot;) des bascules Etat initial 1111 i 111111 il ••• ГТТП Etat après 3 cycles d&#x27;horloge |0|0|0|11 l|f| • • • Ulli Etat après 4 cycles d&#x27;horloge lOlOlOlOl llTl • • • Ulli Etat précédant l&#x27;état initial lOIOIOIOIQIO] ••• 10111 FIGURE 2. Principe de fonctionnement de l ...

Research paper thumbnail of Fast LSP calculation and quantization with application to the CELP FS1016 speech coder

European Signal Processing Conference, Sep 8, 1998

Research paper thumbnail of A multiscale morphological coprocessor for low-power face authentication

European Signal Processing Conference, Sep 3, 2002

Research paper thumbnail of Implementation of a micro power 15-bit “floating-point” A/D converter

International Symposium on Low Power Electronics and Design, Aug 12, 1996

Micro power A/D converter are required for power sensitive, battery-operated equipment such as he... more Micro power A/D converter are required for power sensitive, battery-operated equipment such as hearing aids. This paper overviews the principles of the 15-bit 'Floating point' converter and presents its implementation in a low voltage 2 µm CMOS technology. The die area is 1.4 by 1.4 mm and the power consumption 50 µW at ±1.25 V and 16 kHz sampling frequency. Measurement showed that the internal noise level is higher then expected resulting in a reduced dynamic range of 13 to 14 bits. Informal listening tests showed a very good speech quality.

Research paper thumbnail of Micro power “relative precision” 13 bits cyclic RSD A/D converter

International Symposium on Low Power Electronics and Design, Aug 12, 1996

Recent progress in Digital Signal Processing makes the application of digital algorithms more and... more Recent progress in Digital Signal Processing makes the application of digital algorithms more and more attractive in various fields. However, in battery-operating equipment which needs analog interfaces, the power consumption of the additional today's available A/D and D/A converters restricts the use of digital signal processing. Typical audio applications need a bandwidth above 6 kHz and a dynamic range of about 80 dB corresponding to 13 to 14 bits precision. It is clear that converters with such features consuming distinctly less than 1 mW are not standard components today. Fortunately, in many audio applications, these requirements may be loosened without loss of perceived signal quality. Numerous masking experiments [Schr79] indicate that noise at a level of 30 dB below signal components does not cause any perceptual degradation. Consequently, for such applications, the design constrains are the dynamic range and the minimal signal-to-noise ratio. 2 Related works In [Scha92] the "relative precision" is achieved by a kind of floating point converter. The minimal signal-to-noise ratio determines the number of bits of the mantissa realised as a normal linear converter. At the front end, a variable gain pre-amplifier provides the required dynamic range (see [Gri95] and [Gri96] for an implementation). 3 "Relative precision" using RSD An RSD (Redundant Signed Digit) converter which algorithm can be seen in figure 1, has been published in [Gin92].

Research paper thumbnail of Adaptive block-size transform coding for image compression

In this paper we report the results of an adaptive blocksize transform coding scheme that is base... more In this paper we report the results of an adaptive blocksize transform coding scheme that is based on the sequential JPEG algorithm. This minimum informationoverhead method implies a transform coding technique with two different block sizes: N ×N and 2N ×2N pixels. The input image is divided into blocks of 2N × 2N pixels and each of these blocks is classified according to its image activity. Depending on this classification, either four N-point or a single 2N-point 2-D DCT is applied on the block. The purpose of the algorithm is to take advantage of large uniform regions that can be coded as a single large unit instead of four small units-as it is made by a fixed block-size scheme. For the same reconstruction quality, the results of the adaptive algorithm show a significant improvement of the compression ratio with respect to the non-adaptive scheme.

Research paper thumbnail of Study of a VLSI Implementation of a Noise Reduction Algorithm for Digital Hearing Aids

European Signal Processing Conference, Sep 13, 1994

A methodology for meeting the tight constraints in the physical realization of functional blocks ... more A methodology for meeting the tight constraints in the physical realization of functional blocks for digital hearing aids was applied to the implementation of a noise reduction system based on lattice structures. This methodology fully exploits the flexibility of custom VLSI design through a good interrelation among all the steps of the design. The emphasis was placed in the study of the fixed point quantization effects to find the minimum number of bits and scaling required at every point of the algorithm. Based on these results, an estimation of the power consumption and required silicon area was done in the case of an implementation using a low power VLSI architecture.

Research paper thumbnail of <title>VLSI systems for image compression: a power-consumption/image-resolution trade-off approach</title>

Proceedings of SPIE, Sep 16, 1996

Low power consumption is a requirement for any battery powered p ortable equipment. When designin... more Low power consumption is a requirement for any battery powered p ortable equipment. When designing ASICs for image and video c ompression, emphasis has been placed mainly on building circuits that are fast enough to satisfy the high data throughput associated with image and video p r ocessing. The imminent development of portable systems featuring full multimedia applications, adds the low-power constraint to the design of VLSI circuits for this kind of applications. Several techniques as lowering the supply voltage, architectural parallelization, pipelining etc., have been proposed in the literature to achieve low-power consumption. In this paper we report a VLSI circuit featuring a power management user-controllable technique that trades image quality for power consumption in a transform-based algorithm.

Research paper thumbnail of Power Estimation Techniques for the Purpose of the Architectural Synthesis of Digital Signal Processing Algorithms

Research paper thumbnail of Audio Coder for Telesurveillance Applications with Real Time Implementation on a Multimedia DSP

Research paper thumbnail of Implementation of a Micro POWW 1546% 'Floating-Pointf AD Converter

Micro power AA) converter are required for power sensitive, battery-operated equipment such as he... more Micro power AA) converter are required for power sensitive, battery-operated equipment such as hearing aids. This paper overviews the principles of the 1S-bit ‘Floating pointu converter and presents its implementation in a low voltage 2 p CMOS technology. The die area is 1.4 by 1.4 mm and the power consumption 50 pW at k1.25 V and 16 kHz sampling frequency. Measurement showed that the internal noise level is higher then expected resulting in a reduced dynamic range of 13 to 14 bits, Informal listening tests showed a very good speech quality.

Research paper thumbnail of ASIC DSP compiler for optimized synthesis

International Conference on Signal Processing, Oct 16, 2000

This paper presents a high level DSP architecture compiler for cycle-constrained filters and data... more This paper presents a high level DSP architecture compiler for cycle-constrained filters and datapath applications. The tool offers an easy way to get, from an equation representation of a filter, a synthetisable VHLD description of an application specific DSP architecture. Inputs of the DSP compiler are an equation file to define the filter structure and a resource definition file to specify the available resource units. The equation syntax is very comfortable. Resource mapping, scheduling, binding and furthermore the quantification of each operation is usually performed automatically, but can be controlled by the user. The result is a very fast filter synthesis time combined with highest flexibility for the users.

Research paper thumbnail of Speaker recognition on compressed speech

We have investigated the influence of GSM speech coding in the performance of a text-independent ... more We have investigated the influence of GSM speech coding in the performance of a text-independent speaker recognition system based on Gaussian Mixture Models (GMM) classifiers. The performance degradation due to the utilization of the three GSM speech coders was first assessed, using three transcoded databases, obtained by passing the TIMIT through each GSM coder / decoder. The coded databases were used for training and testing the speaker identification system. The speaker recognition performance was also assessed using the original TIMIT and its 8 kHz downsampled version. Then, different experiments aimed to explore feature calculation directly from the encoded parameters, and to measure the degradation introduced by different aspects of the coders were carried out.

Research paper thumbnail of Bit-Rate Control for the JPEG Algorithm

Kluwer Academic Publishers eBooks, Dec 30, 2005

ABSTRACT JPEG is an international industry standard algorithm for compressing continuoustone stil... more ABSTRACT JPEG is an international industry standard algorithm for compressing continuoustone still images. JPEG which stands for Joint Photographic Expert Group is currently one of the most popular encoding formats used for storing and transmitting images. JPEG is a variable coding bit-rate method and in this chapter two algorithms for controlling the produced compression ratio are reported. The bit-rate control techniques feature an excellent accuracy, a low computational complexity, and a full compliance with the JPEG standard bitstream. Furthermore, the application of these algorithms does not affect the quality of the decompressed images, i.e., to reach the target compression ratio there are no additional losses other than those inherent to JPEG. The most performant of the two bit-rate control techniques has been successfully implemented in a consumer electronics industrial prototype.

Research paper thumbnail of Micro Power High-Resolution A/D Converter

International Conference on Signal Processing, 1999

Due to their low number of biased components, algorithmic A/D converters are often used in low po... more Due to their low number of biased components, algorithmic A/D converters are often used in low power implementations. This paper describes an algorithm developed at the Institute of Microtechnology (IMT) which allows extending performances of cyclic RSD converters, without greatly impairing its benefits (reduced silicon area, low consumption). To achieve a Total Harmonic Distortion + Noise (THD+N) of 14 bits as well as a Dynamic Range (DR) of 16 bits, this algorithm combines oversampling, filtering, pre-and postprocessing. Results of such converter are discussed and widely presented.

Research paper thumbnail of Efficient algorithm to compute LSP parameters from 10th-order LPC coefficients

Line Spectrum Pair (LSP) representation of Linear Predictive Coding (LPC) parameters is widely us... more Line Spectrum Pair (LSP) representation of Linear Predictive Coding (LPC) parameters is widely used in speech coding applications. An efficient method for LPC to LSP conversion is Kabal's method. In this method the LSPs are the roots of two polynomials P' p (x) and Q' p (x), and are found by a zero crossing search followed by successive bisections and interpolation. The precision of the obtained LSPs is higher than required by most applications, but the number of bisections cannot be decreased without compromising the zero crossing search. In this paper, it is shown that, in the case of 10 th-order LPC, five intervals containing each only one zero crossing of P' 10 (x) and one zero crossing of Q' 10 (x) can be calculated, avoiding the zero crossing search. This allows a trade-off between LSP precision and computational complexity resulting in considerable computational saving.

Research paper thumbnail of Design methodology for VLSI implementation of image and video coding algorithms

Research paper thumbnail of <title>Countering illumination variations in a video surveillance environment</title>

Proceedings of SPIE, May 8, 2001

Research paper thumbnail of Effective static response compensation suitable for low-power ASIC implementation with an application to pressure sensors

This paper presents an efficient all-digital compensation technique for sensors measuring static ... more This paper presents an efficient all-digital compensation technique for sensors measuring static or slowly-varying quantities such as pressure. The proposed solution compensates the temperature dependencies and further non-linearities affecting the accuracy and measure ment range of the sensors. In addition, for the considered pressure sensors, the trimming that is usually performed in factory can be replaced by a measure of the sensor characteristics to be used for the digital sensor compensation. The whole design procedure, starting from the description of the pressure sensors down to the low-power ASIC implementation of the processor architecture is discussed in detail.

Research paper thumbnail of Comparison of feature extraction techniques for face verification using elastic graph matching on low-power mobile devices

Biometric face verification using elastic graph matching is considered and two feature extraction... more Biometric face verification using elastic graph matching is considered and two feature extraction techniques used as a pre-processing stage are compared. Low-complexity vs. performance is of particular interest for mobile devices. A modified technique based on a normalization of mathematical morphology feature is introduced and show a performance comparable to that of Gabor features at a much-reduced computational complexity.

Research paper thumbnail of Architecture VLSI faible consommation pour le traitement numérique du signal

... D Ǘ • ••-D M&gt;^ Sorties (&quot;Q&quot;) des bascules Etat initial 1111 i 11111... more ... D Ǘ • ••-D M&gt;^ Sorties (&quot;Q&quot;) des bascules Etat initial 1111 i 111111 il ••• ГТТП Etat après 3 cycles d&#x27;horloge |0|0|0|11 l|f| • • • Ulli Etat après 4 cycles d&#x27;horloge lOlOlOlOl llTl • • • Ulli Etat précédant l&#x27;état initial lOIOIOIOIQIO] ••• 10111 FIGURE 2. Principe de fonctionnement de l ...

Research paper thumbnail of Fast LSP calculation and quantization with application to the CELP FS1016 speech coder

European Signal Processing Conference, Sep 8, 1998

Research paper thumbnail of A multiscale morphological coprocessor for low-power face authentication

European Signal Processing Conference, Sep 3, 2002

Research paper thumbnail of Implementation of a micro power 15-bit “floating-point” A/D converter

International Symposium on Low Power Electronics and Design, Aug 12, 1996

Micro power A/D converter are required for power sensitive, battery-operated equipment such as he... more Micro power A/D converter are required for power sensitive, battery-operated equipment such as hearing aids. This paper overviews the principles of the 15-bit 'Floating point' converter and presents its implementation in a low voltage 2 µm CMOS technology. The die area is 1.4 by 1.4 mm and the power consumption 50 µW at ±1.25 V and 16 kHz sampling frequency. Measurement showed that the internal noise level is higher then expected resulting in a reduced dynamic range of 13 to 14 bits. Informal listening tests showed a very good speech quality.

Research paper thumbnail of Micro power “relative precision” 13 bits cyclic RSD A/D converter

International Symposium on Low Power Electronics and Design, Aug 12, 1996

Recent progress in Digital Signal Processing makes the application of digital algorithms more and... more Recent progress in Digital Signal Processing makes the application of digital algorithms more and more attractive in various fields. However, in battery-operating equipment which needs analog interfaces, the power consumption of the additional today's available A/D and D/A converters restricts the use of digital signal processing. Typical audio applications need a bandwidth above 6 kHz and a dynamic range of about 80 dB corresponding to 13 to 14 bits precision. It is clear that converters with such features consuming distinctly less than 1 mW are not standard components today. Fortunately, in many audio applications, these requirements may be loosened without loss of perceived signal quality. Numerous masking experiments [Schr79] indicate that noise at a level of 30 dB below signal components does not cause any perceptual degradation. Consequently, for such applications, the design constrains are the dynamic range and the minimal signal-to-noise ratio. 2 Related works In [Scha92] the "relative precision" is achieved by a kind of floating point converter. The minimal signal-to-noise ratio determines the number of bits of the mantissa realised as a normal linear converter. At the front end, a variable gain pre-amplifier provides the required dynamic range (see [Gri95] and [Gri96] for an implementation). 3 "Relative precision" using RSD An RSD (Redundant Signed Digit) converter which algorithm can be seen in figure 1, has been published in [Gin92].

Research paper thumbnail of Adaptive block-size transform coding for image compression

In this paper we report the results of an adaptive blocksize transform coding scheme that is base... more In this paper we report the results of an adaptive blocksize transform coding scheme that is based on the sequential JPEG algorithm. This minimum informationoverhead method implies a transform coding technique with two different block sizes: N ×N and 2N ×2N pixels. The input image is divided into blocks of 2N × 2N pixels and each of these blocks is classified according to its image activity. Depending on this classification, either four N-point or a single 2N-point 2-D DCT is applied on the block. The purpose of the algorithm is to take advantage of large uniform regions that can be coded as a single large unit instead of four small units-as it is made by a fixed block-size scheme. For the same reconstruction quality, the results of the adaptive algorithm show a significant improvement of the compression ratio with respect to the non-adaptive scheme.

Research paper thumbnail of Study of a VLSI Implementation of a Noise Reduction Algorithm for Digital Hearing Aids

European Signal Processing Conference, Sep 13, 1994

A methodology for meeting the tight constraints in the physical realization of functional blocks ... more A methodology for meeting the tight constraints in the physical realization of functional blocks for digital hearing aids was applied to the implementation of a noise reduction system based on lattice structures. This methodology fully exploits the flexibility of custom VLSI design through a good interrelation among all the steps of the design. The emphasis was placed in the study of the fixed point quantization effects to find the minimum number of bits and scaling required at every point of the algorithm. Based on these results, an estimation of the power consumption and required silicon area was done in the case of an implementation using a low power VLSI architecture.

Research paper thumbnail of <title>VLSI systems for image compression: a power-consumption/image-resolution trade-off approach</title>

Proceedings of SPIE, Sep 16, 1996

Low power consumption is a requirement for any battery powered p ortable equipment. When designin... more Low power consumption is a requirement for any battery powered p ortable equipment. When designing ASICs for image and video c ompression, emphasis has been placed mainly on building circuits that are fast enough to satisfy the high data throughput associated with image and video p r ocessing. The imminent development of portable systems featuring full multimedia applications, adds the low-power constraint to the design of VLSI circuits for this kind of applications. Several techniques as lowering the supply voltage, architectural parallelization, pipelining etc., have been proposed in the literature to achieve low-power consumption. In this paper we report a VLSI circuit featuring a power management user-controllable technique that trades image quality for power consumption in a transform-based algorithm.

Research paper thumbnail of Power Estimation Techniques for the Purpose of the Architectural Synthesis of Digital Signal Processing Algorithms

Research paper thumbnail of Audio Coder for Telesurveillance Applications with Real Time Implementation on a Multimedia DSP

Research paper thumbnail of Implementation of a Micro POWW 1546% 'Floating-Pointf AD Converter

Micro power AA) converter are required for power sensitive, battery-operated equipment such as he... more Micro power AA) converter are required for power sensitive, battery-operated equipment such as hearing aids. This paper overviews the principles of the 1S-bit ‘Floating pointu converter and presents its implementation in a low voltage 2 p CMOS technology. The die area is 1.4 by 1.4 mm and the power consumption 50 pW at k1.25 V and 16 kHz sampling frequency. Measurement showed that the internal noise level is higher then expected resulting in a reduced dynamic range of 13 to 14 bits, Informal listening tests showed a very good speech quality.

Research paper thumbnail of ASIC DSP compiler for optimized synthesis

International Conference on Signal Processing, Oct 16, 2000

This paper presents a high level DSP architecture compiler for cycle-constrained filters and data... more This paper presents a high level DSP architecture compiler for cycle-constrained filters and datapath applications. The tool offers an easy way to get, from an equation representation of a filter, a synthetisable VHLD description of an application specific DSP architecture. Inputs of the DSP compiler are an equation file to define the filter structure and a resource definition file to specify the available resource units. The equation syntax is very comfortable. Resource mapping, scheduling, binding and furthermore the quantification of each operation is usually performed automatically, but can be controlled by the user. The result is a very fast filter synthesis time combined with highest flexibility for the users.

Research paper thumbnail of Speaker recognition on compressed speech

We have investigated the influence of GSM speech coding in the performance of a text-independent ... more We have investigated the influence of GSM speech coding in the performance of a text-independent speaker recognition system based on Gaussian Mixture Models (GMM) classifiers. The performance degradation due to the utilization of the three GSM speech coders was first assessed, using three transcoded databases, obtained by passing the TIMIT through each GSM coder / decoder. The coded databases were used for training and testing the speaker identification system. The speaker recognition performance was also assessed using the original TIMIT and its 8 kHz downsampled version. Then, different experiments aimed to explore feature calculation directly from the encoded parameters, and to measure the degradation introduced by different aspects of the coders were carried out.

Research paper thumbnail of Bit-Rate Control for the JPEG Algorithm

Kluwer Academic Publishers eBooks, Dec 30, 2005

ABSTRACT JPEG is an international industry standard algorithm for compressing continuoustone stil... more ABSTRACT JPEG is an international industry standard algorithm for compressing continuoustone still images. JPEG which stands for Joint Photographic Expert Group is currently one of the most popular encoding formats used for storing and transmitting images. JPEG is a variable coding bit-rate method and in this chapter two algorithms for controlling the produced compression ratio are reported. The bit-rate control techniques feature an excellent accuracy, a low computational complexity, and a full compliance with the JPEG standard bitstream. Furthermore, the application of these algorithms does not affect the quality of the decompressed images, i.e., to reach the target compression ratio there are no additional losses other than those inherent to JPEG. The most performant of the two bit-rate control techniques has been successfully implemented in a consumer electronics industrial prototype.

Research paper thumbnail of Micro Power High-Resolution A/D Converter

International Conference on Signal Processing, 1999

Due to their low number of biased components, algorithmic A/D converters are often used in low po... more Due to their low number of biased components, algorithmic A/D converters are often used in low power implementations. This paper describes an algorithm developed at the Institute of Microtechnology (IMT) which allows extending performances of cyclic RSD converters, without greatly impairing its benefits (reduced silicon area, low consumption). To achieve a Total Harmonic Distortion + Noise (THD+N) of 14 bits as well as a Dynamic Range (DR) of 16 bits, this algorithm combines oversampling, filtering, pre-and postprocessing. Results of such converter are discussed and widely presented.