G. Visweswaran - Academia.edu (original) (raw)

Papers by G. Visweswaran

IEEE Journal of Solid-State Circuits, 1991

are derived. It is also shown in this paper that the useful loop gain for the desired oscillation... more are derived. It is also shown in this paper that the useful loop gain for the desired oscillations to start is restricted to a similar region by the crystal shunt capacitance and series resistance. Possible design approaches to improve the circuit performance are discussed. All theoretical predictions are verified experimentally and with computer simulations. ACKNOWLEDGMENT The author would like to thank his colleagues D. Aziz and F. Ferraiolo for the measurements and helpful discussions.

2020 IEEE 17th India Council International Conference (INDICON), 2020

In this paper, a voltage control function generator using highly linear second generation current... more In this paper, a voltage control function generator using highly linear second generation current conveyor (CCII) is presented. The current architecture of function generator is based on band pass filter (BPF) which simultaneously provides sinusoidal, square and triangular voltage outputs. The proposed circuit implementation utilizes only five CCII and four grounded capacitors. The tunable frequency range of proposed circuit is 25MHz to 47MHz. All circuits have been evaluated using Spectre simulation in UMC 130nm CMOS technology at 1.2V supply voltage.

2016 29th IEEE International System-on-Chip Conference (SOCC), 2016

With emerging deep submicron technology, device variations limit the SRAM performance and yield. ... more With emerging deep submicron technology, device variations limit the SRAM performance and yield. Cell stability defined by the Static Noise Margin (SNM) of the SRAM cell among other figure of merits (FOMs) governs the yield in SRAMs. Variations in the scaled SRAMs increase the probability of cells becoming weak. To ensure reliability of SRAMs it is important to identify such cells post fabrication. In this work, we propose a correlation based test methodology to detect the weak bits in SRAMs with respect to SNM. The proposed methodology efficiently measures effectiveness of test at CAD level. It enables designer to compare tests for their accuracy in identifying weak bits at nominal test conditions. We compare the traditional weak pull-up (PU) test with Word line (WL) boosting test technique for 64 Mb SRAM in 28nm FDSOI technology. We show that WL boost test method is more effective than the conventional weak PU test and that it is able to screen weak bits beyond 6σ. We also presented a WL boost circuit for detecting weak bits, which requires minimal design complexity.

IETE Journal of Education, 2007

In this article we will start with a basic Common Emitter Amplifier, obtain its gain relationship... more In this article we will start with a basic Common Emitter Amplifier, obtain its gain relationship and interpret it as a multiplication operation. From identifying the short coming of using a CF. Amplifier as a multiplier, that multiplies and ac voltage by a DC voltage, to developing corrective measures and obtaining the traditional multiplier circuit is brought out in stages. The stages of development include moving from CK Amplifier to a Differential Amplifier allowing one of the signals to be multiplied be both dc and ac to improvements in the differential amplifier structure that gives multiplication of two signals that could be dc or ac small signal and finally to a structure that has a large dynamic range for a multiplier.

Discrete Wavelet Transform (DWT) and its generalization, Wavelet Packets (WPs) have acquired cent... more Discrete Wavelet Transform (DWT) and its generalization, Wavelet Packets (WPs) have acquired central position for signal representation. DWT provides good compaction for low pass signals only. On the other hand WPs offers good approximation property for arbitrary signal but the associated computational cost of finding an optimal WP basis is quite high. In this paper, we introduce a signal conditioning based modulated wavelet transform. The proposed transformation provides better approximation performance than that offered by DWT for signal with arbitrary spectra, which can be used in signal approximation, compression, de-noising etc. The proposed transformation in its original form requires computation of signal parity information for which a fast algorithm is proposed. The proposed transform can be implemented efficiently similar to wavelet transform. Simulation results to demonstrate the improved approximation performance are also provided.

All in-text references underlined in blue are linked to publications on ResearchGate, letting you... more All in-text references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately.

IEEE Transactions on Circuits and Systems I: Regular Papers, 2017

An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide volta... more An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35-1.2 V at all process corners. A differential read asymmetric 8 T memory cell and a data dependent differential supply and body modulation write assist scheme are proposed. We also propose a layout that reduces metal capacitance of wordlines by 54% and also enables bit-interleaving. The proposed assist scheme can be combined with conventional assist schemes to further lower minimum write operational voltage of the SRAM by 70-130 mV at iso-performance without causing reliability concerns. A 32 kb instance is fabricated in 28-nm UTBB-FDSOI technology and efficiency of the proposed scheme is demonstrated with lowest write voltage of 0.32 V. Multiple read assist schemes have been used to simultaneously lower read voltage to 0.35 V. 50 MHz operation is measured when integrated in a DSP processor at 0.358 V. Low voltage and wide voltage range figure of merits are also defined to benchmark the proposed solutions with other works.

2016 29th IEEE International System-on-Chip Conference (SOCC), 2016

Embedded SRAM based memory sub-systems are an integral part of SoCs and have a large area footpri... more Embedded SRAM based memory sub-systems are an integral part of SoCs and have a large area footprint in modern SoCs today. Huge memory requirements are typically met by using an array of SRAM instances and optimal selection of these memory instances becomes imperative for SoC designers. We propose a framework based on the following approach: pre-sort a list of most suitable SRAM instances; create a memory assembly using one of these SRAM instances; calculate total assembly area, power and performance of the resultant sub-system using estimation models; iterate through this process to find out the optimal memory assembly possible that conforms to the user-defined PPA criteria. This automated framework assists SoC designers to select an optimal SRAM instance from the potentially large number of combinations possible through generic memory compilers. Through this paper, we also demonstrate that the optimal memory solution can actually lie in using a combination of distinct memory instances, their characteristics varying on the type of optimization desired. We refer to this approach as approach of heterogeneous memory assemblies. These heterogeneous memory assemblies can potentially achieve even better performance than what can be achieved by homogeneity, whatever be the scope of optimization, viz. area, dynamic power or leakage optimization. Through our advanced memory sub-system exploration framework (MSSEF), we demonstrate that for a 4 M-bit memory requirement, we can achieve area savings up to 11 % by using a combination of heterogeneous memory instances instead of homogeneous assemblies.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2017

A tunable oscillator, whose frequency is a function of the total charge in the oscillating nodes,... more A tunable oscillator, whose frequency is a function of the total charge in the oscillating nodes, is introduced in this paper. Three variants of charge-controlled oscillators that oscillate around 3.6 GHz are presented. The figure-of-merit(s) of these oscillators, obtained from simulation, are 169 dB, 172 dB and 178 dB. The measured FoM of the third QCO is 179 dB. We also show that the use of a charge-controlled oscillator in a frequency synthesizer eliminates the requirement of an explicit loop filter. Further, an example of an all-digital phase locked loop (ADPLL) based on a charge-controlled oscillator is shown.

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015

An adaptive SRAM architecture that can dynamically detect and correct read and write failures is ... more An adaptive SRAM architecture that can dynamically detect and correct read and write failures is discussed. The proposed method detects the failures, extends the failing cycles and subsequently corrects those. Data in the failing clock cycle are discarded and are made available in the subsequent cycle, if the failure is corrected. To detect write failures an adaptive write technique based on dummy write column is used. While for the read failures, the proposed read technique uses two non-identical sense amplifiers. We could achieve a Vmin lowering of 180mV for a 90nm ultra low power, high density 6T CMOS SRAM with less than 0.1 percent impact on throughput. This has been achieved without using assist-circuits or ECC. Area overhead is 3 percent for a 128Kb memory instance.

2016 IEEE 34th VLSI Test Symposium (VTS), 2016

In this paper we discuss the need to consider Crosstalk and Process Variation effects for test po... more In this paper we discuss the need to consider Crosstalk and Process Variation effects for test power reduction during Launch-on-Capture scheme for at-speed delay test. We show that consideration of these effects can have significant effect on capture power reduction technique. This effect is a manifestation of increased IR drops in the presence of crosstalk and process variation. Thus both these factors should be taken into account during the design as well as the test phase of nanometer technologies. Our experimental results on two significantly sized industrial designs in 28nm show that when these effects are considered the number of high capture power patterns selected for post-processing are impacted by 13% and 30% respectively. Thus not considering these effects might lead to some high power consuming patterns left untouched or over processing of the patterns.

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016

A low Vmin, 6T-SRAM is realized in 28nm UTBB (Ultra-Thin Body and BOX) FDSOI technology using rea... more A low Vmin, 6T-SRAM is realized in 28nm UTBB (Ultra-Thin Body and BOX) FDSOI technology using read and write assist methods. We could reduce the Vmin of SRAM cell to 0.5V for the 0.120um2 high density 6T-SRAM. Read margin of the SRAM cell is recovered using a compensated under driven word line scheme. Write assist is realized using negative bit-line approach. Bit-line is pulled to a required negative value in order to provide sufficient assistance for the write operation. Required word line under drive is 90mV to ensure correct read operation. For write assist, the undershoot requirement is 114mV. We could achieve a performance of 1.2MHz at 0.5V and 40MHz at 0.6V for a 288Kb capacity SRAM with 2K words of 144bits width. The area overhead of the read and write assist scheme is 1.0 percent and 2.5 percent respectively.

IETE Journal of Research, 1992

This paper discusses the problem of heat generation, heat conduction and the effects of these on ... more This paper discusses the problem of heat generation, heat conduction and the effects of these on the performance of integrated circuits. The result obtained is in the form of two dimensional isothermal contours on the chip. Using these contours, the location of the various functional blocks and their average operating temperatures are determined and resulting performance obtained through simulation.

Microelectronics Journal, 1998

International Journal of Electronics, 1991

The design is presented of a ternary D/A converter using current mirror sources. The design goal ... more The design is presented of a ternary D/A converter using current mirror sources. The design goal has been to obtain a system with a higher tolerance to both power supply and physical parameter fluctuations compared to existing systems. Furthermore, comparison with previously reported 3R-4R resistive network D/A converters reveals a better area saving in the present design.

2016 20th International Symposium on VLSI Design and Test (VDAT), 2016

In advanced technology nodes, device variations limit the SRAM performance and yield. Cell stabil... more In advanced technology nodes, device variations limit the SRAM performance and yield. Cell stability defined by the Static Noise Margin (SNM) of the SRAM cell primarily governs the performance with respect to yield in SRAMs. Variations in the scaled SRAMs increase the probability of cells becoming weak. To ensure reliability of SRAMs it is important to identify such cells post silicon. In this work, we propose a correlation based test methodology to detect the weak bits in SRAMs with respect to SNM. We present a case study for 64×64 SRAM in 28nm FDSOI technology. The proposed methodology targets high speed testing and lower test costs. It enables to perform the test at nominal operating voltage and room temperature. Suitable read stress is induced by boosting the Word Line (WL) voltage of the 6T SRAM cell. To validate the effectiveness of the test and find appropriate test stress we propose correlation methodology. With this test we could detect the weak cells possessing SNM upto 60...

Solid-State Circuits, …, 1991

are derived. It is also shown in this paper that the useful loop gain for the desired oscillation... more are derived. It is also shown in this paper that the useful loop gain for the desired oscillations to start is restricted to a similar region by the crystal shunt capacitance and series resistance. Possible design approaches to improve the circuit performance are discussed. All theoretical predictions are verified experimentally and with computer simulations. ACKNOWLEDGMENT The author would like to thank his colleagues D. Aziz and F. Ferraiolo for the measurements and helpful discussions.

IETE Journal of Research, 1992

IEEE Journal of Solid-State Circuits, 1991

are derived. It is also shown in this paper that the useful loop gain for the desired oscillation... more are derived. It is also shown in this paper that the useful loop gain for the desired oscillations to start is restricted to a similar region by the crystal shunt capacitance and series resistance. Possible design approaches to improve the circuit performance are discussed. All theoretical predictions are verified experimentally and with computer simulations. ACKNOWLEDGMENT The author would like to thank his colleagues D. Aziz and F. Ferraiolo for the measurements and helpful discussions.

2020 IEEE 17th India Council International Conference (INDICON), 2020

In this paper, a voltage control function generator using highly linear second generation current... more In this paper, a voltage control function generator using highly linear second generation current conveyor (CCII) is presented. The current architecture of function generator is based on band pass filter (BPF) which simultaneously provides sinusoidal, square and triangular voltage outputs. The proposed circuit implementation utilizes only five CCII and four grounded capacitors. The tunable frequency range of proposed circuit is 25MHz to 47MHz. All circuits have been evaluated using Spectre simulation in UMC 130nm CMOS technology at 1.2V supply voltage.

2016 29th IEEE International System-on-Chip Conference (SOCC), 2016

With emerging deep submicron technology, device variations limit the SRAM performance and yield. ... more With emerging deep submicron technology, device variations limit the SRAM performance and yield. Cell stability defined by the Static Noise Margin (SNM) of the SRAM cell among other figure of merits (FOMs) governs the yield in SRAMs. Variations in the scaled SRAMs increase the probability of cells becoming weak. To ensure reliability of SRAMs it is important to identify such cells post fabrication. In this work, we propose a correlation based test methodology to detect the weak bits in SRAMs with respect to SNM. The proposed methodology efficiently measures effectiveness of test at CAD level. It enables designer to compare tests for their accuracy in identifying weak bits at nominal test conditions. We compare the traditional weak pull-up (PU) test with Word line (WL) boosting test technique for 64 Mb SRAM in 28nm FDSOI technology. We show that WL boost test method is more effective than the conventional weak PU test and that it is able to screen weak bits beyond 6σ. We also presented a WL boost circuit for detecting weak bits, which requires minimal design complexity.

IETE Journal of Education, 2007

In this article we will start with a basic Common Emitter Amplifier, obtain its gain relationship... more In this article we will start with a basic Common Emitter Amplifier, obtain its gain relationship and interpret it as a multiplication operation. From identifying the short coming of using a CF. Amplifier as a multiplier, that multiplies and ac voltage by a DC voltage, to developing corrective measures and obtaining the traditional multiplier circuit is brought out in stages. The stages of development include moving from CK Amplifier to a Differential Amplifier allowing one of the signals to be multiplied be both dc and ac to improvements in the differential amplifier structure that gives multiplication of two signals that could be dc or ac small signal and finally to a structure that has a large dynamic range for a multiplier.

Discrete Wavelet Transform (DWT) and its generalization, Wavelet Packets (WPs) have acquired cent... more Discrete Wavelet Transform (DWT) and its generalization, Wavelet Packets (WPs) have acquired central position for signal representation. DWT provides good compaction for low pass signals only. On the other hand WPs offers good approximation property for arbitrary signal but the associated computational cost of finding an optimal WP basis is quite high. In this paper, we introduce a signal conditioning based modulated wavelet transform. The proposed transformation provides better approximation performance than that offered by DWT for signal with arbitrary spectra, which can be used in signal approximation, compression, de-noising etc. The proposed transformation in its original form requires computation of signal parity information for which a fast algorithm is proposed. The proposed transform can be implemented efficiently similar to wavelet transform. Simulation results to demonstrate the improved approximation performance are also provided.

All in-text references underlined in blue are linked to publications on ResearchGate, letting you... more All in-text references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately.

IEEE Transactions on Circuits and Systems I: Regular Papers, 2017

An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide volta... more An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35-1.2 V at all process corners. A differential read asymmetric 8 T memory cell and a data dependent differential supply and body modulation write assist scheme are proposed. We also propose a layout that reduces metal capacitance of wordlines by 54% and also enables bit-interleaving. The proposed assist scheme can be combined with conventional assist schemes to further lower minimum write operational voltage of the SRAM by 70-130 mV at iso-performance without causing reliability concerns. A 32 kb instance is fabricated in 28-nm UTBB-FDSOI technology and efficiency of the proposed scheme is demonstrated with lowest write voltage of 0.32 V. Multiple read assist schemes have been used to simultaneously lower read voltage to 0.35 V. 50 MHz operation is measured when integrated in a DSP processor at 0.358 V. Low voltage and wide voltage range figure of merits are also defined to benchmark the proposed solutions with other works.

2016 29th IEEE International System-on-Chip Conference (SOCC), 2016

Embedded SRAM based memory sub-systems are an integral part of SoCs and have a large area footpri... more Embedded SRAM based memory sub-systems are an integral part of SoCs and have a large area footprint in modern SoCs today. Huge memory requirements are typically met by using an array of SRAM instances and optimal selection of these memory instances becomes imperative for SoC designers. We propose a framework based on the following approach: pre-sort a list of most suitable SRAM instances; create a memory assembly using one of these SRAM instances; calculate total assembly area, power and performance of the resultant sub-system using estimation models; iterate through this process to find out the optimal memory assembly possible that conforms to the user-defined PPA criteria. This automated framework assists SoC designers to select an optimal SRAM instance from the potentially large number of combinations possible through generic memory compilers. Through this paper, we also demonstrate that the optimal memory solution can actually lie in using a combination of distinct memory instances, their characteristics varying on the type of optimization desired. We refer to this approach as approach of heterogeneous memory assemblies. These heterogeneous memory assemblies can potentially achieve even better performance than what can be achieved by homogeneity, whatever be the scope of optimization, viz. area, dynamic power or leakage optimization. Through our advanced memory sub-system exploration framework (MSSEF), we demonstrate that for a 4 M-bit memory requirement, we can achieve area savings up to 11 % by using a combination of heterogeneous memory instances instead of homogeneous assemblies.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2017

A tunable oscillator, whose frequency is a function of the total charge in the oscillating nodes,... more A tunable oscillator, whose frequency is a function of the total charge in the oscillating nodes, is introduced in this paper. Three variants of charge-controlled oscillators that oscillate around 3.6 GHz are presented. The figure-of-merit(s) of these oscillators, obtained from simulation, are 169 dB, 172 dB and 178 dB. The measured FoM of the third QCO is 179 dB. We also show that the use of a charge-controlled oscillator in a frequency synthesizer eliminates the requirement of an explicit loop filter. Further, an example of an all-digital phase locked loop (ADPLL) based on a charge-controlled oscillator is shown.

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015

An adaptive SRAM architecture that can dynamically detect and correct read and write failures is ... more An adaptive SRAM architecture that can dynamically detect and correct read and write failures is discussed. The proposed method detects the failures, extends the failing cycles and subsequently corrects those. Data in the failing clock cycle are discarded and are made available in the subsequent cycle, if the failure is corrected. To detect write failures an adaptive write technique based on dummy write column is used. While for the read failures, the proposed read technique uses two non-identical sense amplifiers. We could achieve a Vmin lowering of 180mV for a 90nm ultra low power, high density 6T CMOS SRAM with less than 0.1 percent impact on throughput. This has been achieved without using assist-circuits or ECC. Area overhead is 3 percent for a 128Kb memory instance.

2016 IEEE 34th VLSI Test Symposium (VTS), 2016

In this paper we discuss the need to consider Crosstalk and Process Variation effects for test po... more In this paper we discuss the need to consider Crosstalk and Process Variation effects for test power reduction during Launch-on-Capture scheme for at-speed delay test. We show that consideration of these effects can have significant effect on capture power reduction technique. This effect is a manifestation of increased IR drops in the presence of crosstalk and process variation. Thus both these factors should be taken into account during the design as well as the test phase of nanometer technologies. Our experimental results on two significantly sized industrial designs in 28nm show that when these effects are considered the number of high capture power patterns selected for post-processing are impacted by 13% and 30% respectively. Thus not considering these effects might lead to some high power consuming patterns left untouched or over processing of the patterns.

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016

A low Vmin, 6T-SRAM is realized in 28nm UTBB (Ultra-Thin Body and BOX) FDSOI technology using rea... more A low Vmin, 6T-SRAM is realized in 28nm UTBB (Ultra-Thin Body and BOX) FDSOI technology using read and write assist methods. We could reduce the Vmin of SRAM cell to 0.5V for the 0.120um2 high density 6T-SRAM. Read margin of the SRAM cell is recovered using a compensated under driven word line scheme. Write assist is realized using negative bit-line approach. Bit-line is pulled to a required negative value in order to provide sufficient assistance for the write operation. Required word line under drive is 90mV to ensure correct read operation. For write assist, the undershoot requirement is 114mV. We could achieve a performance of 1.2MHz at 0.5V and 40MHz at 0.6V for a 288Kb capacity SRAM with 2K words of 144bits width. The area overhead of the read and write assist scheme is 1.0 percent and 2.5 percent respectively.

IETE Journal of Research, 1992

This paper discusses the problem of heat generation, heat conduction and the effects of these on ... more This paper discusses the problem of heat generation, heat conduction and the effects of these on the performance of integrated circuits. The result obtained is in the form of two dimensional isothermal contours on the chip. Using these contours, the location of the various functional blocks and their average operating temperatures are determined and resulting performance obtained through simulation.

Microelectronics Journal, 1998

International Journal of Electronics, 1991

The design is presented of a ternary D/A converter using current mirror sources. The design goal ... more The design is presented of a ternary D/A converter using current mirror sources. The design goal has been to obtain a system with a higher tolerance to both power supply and physical parameter fluctuations compared to existing systems. Furthermore, comparison with previously reported 3R-4R resistive network D/A converters reveals a better area saving in the present design.

2016 20th International Symposium on VLSI Design and Test (VDAT), 2016

In advanced technology nodes, device variations limit the SRAM performance and yield. Cell stabil... more In advanced technology nodes, device variations limit the SRAM performance and yield. Cell stability defined by the Static Noise Margin (SNM) of the SRAM cell primarily governs the performance with respect to yield in SRAMs. Variations in the scaled SRAMs increase the probability of cells becoming weak. To ensure reliability of SRAMs it is important to identify such cells post silicon. In this work, we propose a correlation based test methodology to detect the weak bits in SRAMs with respect to SNM. We present a case study for 64×64 SRAM in 28nm FDSOI technology. The proposed methodology targets high speed testing and lower test costs. It enables to perform the test at nominal operating voltage and room temperature. Suitable read stress is induced by boosting the Word Line (WL) voltage of the 6T SRAM cell. To validate the effectiveness of the test and find appropriate test stress we propose correlation methodology. With this test we could detect the weak cells possessing SNM upto 60...

Solid-State Circuits, …, 1991

are derived. It is also shown in this paper that the useful loop gain for the desired oscillation... more are derived. It is also shown in this paper that the useful loop gain for the desired oscillations to start is restricted to a similar region by the crystal shunt capacitance and series resistance. Possible design approaches to improve the circuit performance are discussed. All theoretical predictions are verified experimentally and with computer simulations. ACKNOWLEDGMENT The author would like to thank his colleagues D. Aziz and F. Ferraiolo for the measurements and helpful discussions.

IETE Journal of Research, 1992