Germán Luna - Academia.edu (original) (raw)
Papers by Germán Luna
Abstract—This paper presents the architecture and circuit design of a single chip 32 mm2 90 nm CM... more Abstract—This paper presents the architecture and circuit design of a single chip 32 mm2 90 nm CMOS DSP transceiver for electronic dispersion compensation (EDC) of multimode fibers at 10 Gb/s, based on maximum likelihood sequence detection (MLSD). This is the first MLSD-based transceiver for multimode fibers and the first fully integrated DSP based transceiver for optical channels reported in the technical literature. The digital receiver incorporates equalization, Viterbi detection, channel estimation, timing recovery, and gain control functions. The analog front-end incorporates an 8-way interleaved ADC with self-calibration, a programmable gain amplifier, a phase interpolator, and the transmitter. Also integrated are a XAUI interface, the physical coding sublayer (PCS), and miscellaneous test and control functions. Experimental results using the stressors specified by the IEEE 10 GBASE-LRM standard [1], as well as industry-defined worst-case fibers are reported. A sensitivity of ...
2006 IEEE International Symposium on Circuits and Systems
IEEE Journal of Solid-State Circuits, 2008
IEEE Journal of Solid-State Circuits, 2000
2006 IEEE International Symposium on Circuits and Systems, 2006
IEEE Journal of Solid-State Circuits, 2000
Abstract—This paper presents the architecture and circuit design of a single chip 32 mm2 90 nm CM... more Abstract—This paper presents the architecture and circuit design of a single chip 32 mm2 90 nm CMOS DSP transceiver for electronic dispersion compensation (EDC) of multimode fibers at 10 Gb/s, based on maximum likelihood sequence detection (MLSD). This is the first MLSD-based transceiver for multimode fibers and the first fully integrated DSP based transceiver for optical channels reported in the technical literature. The digital receiver incorporates equalization, Viterbi detection, channel estimation, timing recovery, and gain control functions. The analog front-end incorporates an 8-way interleaved ADC with self-calibration, a programmable gain amplifier, a phase interpolator, and the transmitter. Also integrated are a XAUI interface, the physical coding sublayer (PCS), and miscellaneous test and control functions. Experimental results using the stressors specified by the IEEE 10 GBASE-LRM standard [1], as well as industry-defined worst-case fibers are reported. A sensitivity of ...
2006 IEEE International Symposium on Circuits and Systems
IEEE Journal of Solid-State Circuits, 2008
IEEE Journal of Solid-State Circuits, 2000
2006 IEEE International Symposium on Circuits and Systems, 2006
IEEE Journal of Solid-State Circuits, 2000