Giovanni De Micheli - Academia.edu (original) (raw)

Papers by Giovanni De Micheli

Proceedings of the 1999 international symposium on Low power electronics and design - ISLPED '99

In this work we propose an exact technique for efficient computation of signal statistics during ... more In this work we propose an exact technique for efficient computation of signal statistics during high-level synthesis for low-power of general control-dominated designs. Our approach does not require iterative simulation: simulation is performed once for all to collect boundary information that will be repeatedly exploited for computing signal statistics for alternative implementations.

Proceedings of the 1997 international symposium on Low power electronics and design - ISLPED '97, 1997

paper we propose a solution to power minimization under timing constraints, where we minimize pow... more paper we propose a solution to power minimization under timing constraints, where we minimize power without trading off performance. Moreover, we focus on the last stages-of the synthesis process, namely we target the po\ver.optlmization of a mapped netlist. Post-mapping optlmlzatlon is often called re-mapping. In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algorithm based on Boolean relations that allows us to find reduced-power replacements for clusters of more than one cell. Our approach is robust and scales well with circuit size: it has been tested on all largest examples of the MCNC91 benchmark suite. In average, power is reduced by more than 17% with no speed penalty compared to minimum delay implementations. Area is virtually unchanged. 1 L. Benini was supported by NSF under contract MIP-942119. P. Vuillod was on leave from INPG-CSI, FRANCE.

2003 Design, Automation and Test in Europe Conference and Exhibition

Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC... more Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the packet dataflows that are transported on the network. In this paper, by introducing a packetized on-chip communication power model, we discuss the packetization impact on MPSoC performance and power consumption. Particularly, we propose a quantitative analysis method to evaluate the relationship between different design options (cache, memory, packetization scheme, etc.) at the architectural level. From the benchmark experiments, we show that optimal performance and power tradeoff can be achieved by the selection of appropriate packet sizes.

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2011

Three-dimensional (3D) integrated circuits and systems are expected to be present in electronic p... more Three-dimensional (3D) integrated circuits and systems are expected to be present in electronic products in the short term. We consider specifically 3D multi-processor systems-on-chips (MPSoCs), realized by stacking silicon CMOS chips and interconnecting them by means of through-silicon vias (TSVs). Because of the high power density of devices and interconnect in the 3D stack, thermal issues pose critical challenges, such as hot-spot avoidance and thermal gradient reduction. Thermal management is achieved by a combination of active control of on-chip switching rates as well as active interlayer cooling with pressurized fluids. In this paper, we propose a novel online thermal management policy for high-performance 3D systems with liquid cooling. Our proposed controller uses a hierarchical approach with a global controller regulating the active cooling and local controllers (on each layer) performing dynamic voltage and frequency scaling (DVFS) and interacting with the global controller. Then, the on-line control is achieved by policies that are computed off-line by solving an optimization problem that considers the thermal profile of 3D-MPSoCs, its evolution over time and current time-varying workload requirements. The proposed hierarchical scheme is scalable to complex (and heterogeneous) 3D chip stacks. We perform experiments on a 3D-MPSoC case study with different interlayer cooling structures, using benchmarks ranging from web-accessing to playing multimedia. Results show significant advantages in terms of energy savings that reaches values up to 50% versus state-of-the-art thermal control techniques for liquid cooling, and thermal balance with differences of less than 10 C per layer. Index Terms-Hardware/software co-design, multilayer, multiprocessor system-on-chip (SoC), power modeling and estimation, thermal.

Proceedings of 1996 International Symposium on Low Power Electronics and Design

The presence of large current peaks on the power and ground lines is a serious concern for design... more The presence of large current peaks on the power and ground lines is a serious concern for designers of synchronous digital circuits. Current peaks are caused by the simultaneous switching of highly loaded clock lines and by the signal propagation through the sequential logic elements. In this work we propose a methodology for reducing the amplitude of the current peaks. This result is obtained by clock skew optimization. We propose an algorithm that, for a given clock cycle time, determines the clock arrival time at each flip-flop in order to minimize the current peaks while respecting timing constraint. Our results on benchmark circuits show that current peaks can be reduced without penalty on cycle time and average power dissipation. Our methodology is therefore well-suited for low-power systems with reduced supply voltage, where low noise margins are a primary concern.

Proceedings International Conference on Computer Design. VLSI in Computers and Processors

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010

Meeting temperature constraints and reducing the hot-spots are critical for achieving reliable an... more Meeting temperature constraints and reducing the hot-spots are critical for achieving reliable and efficient operation of complex multi-core systems. In this paper we aim at achieving an online smooth thermal control action that minimizes the performance loss as well as the computational and hardware overhead of embedding a thermal management system inside the MPSoC. The optimization problem considers the thermal profile of the system, its evolution over time and current timevarying workload requirements. We formulate this problem as a discrete-time control problem using model predictive control. The solution is computed off-line and partially on-line using an explicit approximate algorithm. This proposed method, compared with the optimum approach provides a significant reduction in hardware requirements and computational cost at the expense of a small loss in accuracy. We perform experiments on a model of the 8-core Niagara-1 multicore architecture using benchmarks ranging from web-accessing to playing multimedia. Results show that the proposed method provides comparable performance(loss up to 2.7%) versus the optimum solution with a reduction up to 72.5× in the the computational complexity.

2008 IEEE Sensors, 2008

This paper presents a switched-capacitor (SC) current integrator circuit for impedance measuremen... more This paper presents a switched-capacitor (SC) current integrator circuit for impedance measurement of tethered bilayer lipid membrane (tBLM) biosensors. The circuit comprises a small number of high performance components enabling enhanced experimental flexibility and reliability. The sensitivity is improved significantly by suppressing the output offset through pseudo-differential operation, using R-C components for the reference impedance. The sensing and reference electrodes are excited with low-amplitude differential voltage pulses and the current response to membrane resistance (R M) change of the tBLM biosensor is converted to voltage by a precision, low-noise SC integrator available as a single-package IC. Tests with both electrical models and actual biosensors demonstrated that the proposed circuit operates with high sensitivity and can be used in single chip versions for low-cost and high-sensitive tBLM biosensor arrays, featuring multiple electrode sites. I.

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011

Multi-Processor Systems-on-Chip (MPSoCs) are penetrating the electronics market as a powerful, ye... more Multi-Processor Systems-on-Chip (MPSoCs) are penetrating the electronics market as a powerful, yet commercially viable, solution to answer the strong and steadily growing demand for scalable and high performance systems, at limited design complexity. However, it is critical to develop dedicated system-level design methodologies for multi-core architectures that seamlessly address their thermal modeling, analysis and management. In this work, we first formulate the problem of system-level thermal modeling and link it to produce a global thermal management formulation as a discrete-time optimal control problem, which can be solved using finite-horizon model-predictive control (MPC) techniques, while adapting to the actual time-varying unbalanced MPSoC workload requirements. Finally, we compare the system-level MPC-based thermal modeling and management approaches on an industrial 8-core MPSoC design and show their different trade-offs regarding performance while respecting operating temperature bounds.

2012 IEEE International Symposium on Circuits and Systems, 2012

In biological applications and systems where even the smallest details have a meaning, CCD camera... more In biological applications and systems where even the smallest details have a meaning, CCD cameras are mostly preferred and they hold most of the market share despite their high costs. In this paper, we propose a custom-designed CMOS camera to compete with the default CCD camera of an inverted microscope for fluorescence imaging. The custom-designed camera includes a commercially available mid-performance CMOS image sensor and a Field-Programmable Gate Array (FPGA) based hardware platform (FPGA4U). The high cost CCD camera of the microscope is replaced by the custom-designed CMOS camera and the two are quantitatively compared for a specific application where an Estrogen Reception (ER) expression in breast cancer diagnostic samples that emits light at 665nm has been imaged by both cameras. The gray-scale images collected by both cameras show a very similar intensity distribution. In addition, normalized white pixels after thresholding resulted in 4.96% for CCD and 3.38% for CMOS. The results and images after thresholding show that depending on the application even a mid-performance CMOS camera can provide enough image quality when the target is localization of fluorescent stained biological details. Therefore the cost of the cameras can be drastically reduced while benefiting from the inherent advantages of CMOS devices plus adding more features and flexibility to the camera systems with FPGAs.

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009

The quest for technologies with superior device characteristics has showcased Carbon Nanotube Fie... more The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects necessary for today's grail in CNFET technology, achieving functional immunity to Carbon Nanotube (CNT) manufacturing issues (such as mispositioned CNTs and metallic CNTs) is of paramount importance. In this work we present a new design technique to build compact layouts while ensuring 100% functional immunity to mispositioned CNTs. Then, as second contribution of this work, we have developed a CNFET Design Kit (DK) to realize a complete design flow from logic-to-GDSII traversing the conventional CMOS design flow. This flow enables a framework that allows accurate comparison between CMOS and CNFET-based circuits. This paper also presents simulation results to illustrate such analysis, namely, a CNFETbased inverter can achieve gains, with respect to the Energy-Delay Product (EDP) metric, of more than 4x in delay, 2x in energy/cycle and significant area savings (more than 30%) when compared to a corresponding CMOS inverter benchmarked with an industrial 65nm technology.

2007 14th Ieee International Conference on Electronics, Circuits and Systems, Vols 1-4, 2007

Latest fabrication technologies of self-assembly nano-circuits (carbon nanotubes, silicon nanowir... more Latest fabrication technologies of self-assembly nano-circuits (carbon nanotubes, silicon nanowires, etc.) have deployed bottom-up techniques that reach feature sizes well below 65nm, holding great promise for future large silicon-based integrated circuits. However, new nano-devices intrinsically have much higher failure rates than CMOS-based ones. Thus, new design methodologies must address the combination of devicelevel error-prone technologies with system integration constraints (low power, performance) to deliver competitive devices at the nanometer scale. In this paper we show that a very promising way to achieve nano-scale devices is combining imperfectionaware design techniques during fabrication with gate defect modeling at circuit level. Our results using this approach to define a Carbon Nanotube Field-Effect Transistor (CNFET)-based design flow for nanoscale logic circuits attain more than 3× energydelay-product advantage compared to 65nm CMOS-based ones.

Intelligent Decision Making Systems, 2010

ABSTRACT

Proceedings Design, Automation and Test in Europe, 1998

We propose a new approach to RT-level power modeling for combinational macros, that does not requ... more We propose a new approach to RT-level power modeling for combinational macros, that does not require simulationbased characterization. A p attern-dependent power model for a macro is analytically constructed using only structural information about its gate-level implementation. The approach has three main advantages over traditional techniques: i it provides models whose accuracy does not depend on input statistics, ii it o ers a wide range of tradeo between accuracy and complexity, and iii it enables the construction of pattern-dependent conservative upper bounds.

International Symposium on System Synthesis (IEEE Cat. No.01EX526)

Power Aware Design Methodologies, 2002

The complexity of current and future integrated systems requires a paradigm shift towards compone... more The complexity of current and future integrated systems requires a paradigm shift towards component-based design techno logies that enable the integration of large computational cores, memory hierarchies and communication channel as well as system and application software onto a single chip. Moving from a set of case studies, we give an overview of energy-efficient systemlevel design, emphasizing a component-based approach.

2008 Asia and South Pacific Design Automation Conference, 2008

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies ... more Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges to maintain manufacturing yield rates and reliable devices in their expected lifetimes for latest nanometer-scale dimensions. In fact, new system and processor microarchitectures require new reliability-aware design methods and exploration tools that can face these challenges without significantly increasing manufacturing cost, reducing system performance or imposing large area overheads due to redundancy. In this paper we overview the latest approaches in reliability modeling and variability-tolerant design for latest technology nodes, and advocate the need of reliabilityaware design for forthcoming consumer electronics. Moreover, we illustrate with a case study of an embedded processor that effective reliability-aware design can be achieved in nanometer-scale devices through integral design approaches that covers modeling and exploration of reliability effects, and hardware-software architectural techniques to provide reliability-enhanced solutions at both microarchitectural-and system-level.

IFIP International Federation for Information Processing

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architect... more Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can lead to deadlock-free operation with minimum power and area overhead are important for designing application-specific NoCs. The deadlocks that can occur in NoCs can be broadly categorized into two classes: routingdependent deadlocks and message-dependent deadlocks. In this work, we present methods to design NoCs that avoid both types of deadlocks. The methods are integrated with the topology synthesis phase of the NoC design flow. We show that by considering the deadlock avoidance issue during topology synthesis, we can obtain a significantly better NoC design than traditional methods, where the deadlock avoidance issue is dealt with separately. Our experiments on several SoC benchmarks show that our proposed scheme provides large reduction in NoC power consumption (an average of 38.5%) and NoC area (an average of 30.7%) when compared to traditional approaches.

2006 IFIP International Conference on Very Large Scale Integration, 2006