Vincent HUARD - Academia.edu (original) (raw)

Papers by Vincent HUARD

Research paper thumbnail of Correlation Technologies for Emerging Wireless Applications

Electronics, 2022

In this article, we introduce correlation technologies both at RF/mmWave and baseband frequencies... more In this article, we introduce correlation technologies both at RF/mmWave and baseband frequencies. At RF and mmWave frequencies, power-spectra and energy-spectra metrics are introduced for measuring the power-density of mobile devices and systems. New ASIC-embedded smart connectors are developed for bringing correlation-based signal processing close to antenna modules. At baseband frequencies, DSP-based convolutional accelerators are proposed for fast and accurate measurement of EVM (error vector magnitude) using correlation technologies. Porting of the DSP-based convolutional accelerators into advanced fully depleted silicon-on-insulator (FDSOI)-based ASIC platforms for co-integration with adaptive RF/mmWave front-end modules will enable real-time extraction of auto-correlation and cross-correlation functions of stochastic signals. Perspectives for optically synchronized interferometric-correlation technologies are drawn for accurate measurements in noisy environments of stochastic...

Research paper thumbnail of Robust automotive products in advanced CMOS nodes

2017 IEEE International Reliability Physics Symposium (IRPS), 2017

In this work, additional elements needed on top of conventional foundry reliability knowledge to ... more In this work, additional elements needed on top of conventional foundry reliability knowledge to enable robust automotive products in compliance with all restrictive norms are introduced. For intrinsic reliability, the main element is the reliability models (a design compatible WLR description). Their usage for design margins definition and their thorough validation at IP level is described. For extrinsics failure, two different screening procedures, Vstress and Burn-In (conventional or wafer-level), are here well documented and in use for volume production to bring the failure rate level down below 1ppm automotive target. Altogether, the global approach developed in STMicroelectronics enable robust automotive products based on controlled and validated procedures.

Research paper thumbnail of BTI induced dispersion: Challenges and opportunities for SRAM bit cell optimization

2016 IEEE International Reliability Physics Symposium (IRPS), 2016

One of major CMOS reliability concern for advanced nodes is the Bias Temperature Instability mech... more One of major CMOS reliability concern for advanced nodes is the Bias Temperature Instability mechanism. In addition to the native local process dispersion, BTI induced dispersion is becoming a field of intensive research. Important works focus on the distribution tail of the Vth shift after NBTI stress and efforts are deployed to high-sigma accurate modeling (defect-centric, Skellam). However, in many analog applications (ADC, SRAM) sensitive to devices matching, it is important to understand how the initial Vth distribution evolves in time. In this paper some key results of spread induced by BTI are reviewed for 14nm and 28nm Fully Depleted SOI from STMicroelectronics. Analysis between initial Vth and aged Vth correlation is presented. Then, measurement of fresh and post HTOL memory VDDmin is presented for different conditions of temperature and process centering. Then, a powerful algorithm of yield optimization is presented. It enables design centering and yield improvement (through devices sizing by moving the mean value and modifying the local process parameter impact on the performance spread) including ageing, under constraint of foot print.

Research paper thumbnail of Modeling of Process (Ge, N) Dependence and Mechanical Strain Impact on NBTI in HKMG SiGe GF FDSOI p-MOSFETs and RMG p-FinFETs

2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018

A physical framework is used to model time kinetics of Negative Bias Temperature Instability (NBT... more A physical framework is used to model time kinetics of Negative Bias Temperature Instability (NBTI) in Si and SiGe FDSOI p-MOSFETs and p-FinFETs. The effects of Germanium (Ge%) in the channel and Nitrogen (N%) in the High-K Metal Gate (HKMG) gate stack are explained. Mechanical strain effects in terms of STI to active distance (SA) for FDSOI and channel length (L) scaling for FinFET are explained. Band structure is calculated to correlate the process (Ge%, N%, strain) impact on device degradation. The model is included in Sentaurus Device TCAD to predict NBTI kinetics in Si and SiGe FinFETs.

Research paper thumbnail of Memory OTP-based MOSFET devices

Research paper thumbnail of Improve Macroscopic Degradation Modeling of MOSFETs

Degradation modeling is based usually on macroscopic parameters which can yield to wrong conclusi... more Degradation modeling is based usually on macroscopic parameters which can yield to wrong conclusions, since similar degradation might result from very different microscopic situations. The focus on degradation modeling at a microscopic level is proposed. Other authors only compare results from different characterization methods on their common measurement area. This paper proposes to use their complementarities to extend the probed areas. A more accurate determination of defects is obtained with multiple characterization method cross-fertilization allowing 1) ascertaining defect localizations, 2) extending probed areas and 3) identifying microscopic differences between similar macroscopic parameters. The tested devices are NMOS transistors with a 5 nm SiO2 gate oxide and with various gate geometries. INTRODUCTION The development of new technology nodes has seen the arising importance of accurate degradation characterization. Recent work on Hot Carrier Stress (HCS) modeling has consi...

Research paper thumbnail of New Hot-Carrier Lifetime Technique for High- to Low-Supplied Voltage nMOSFETs

2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2007

ABSTRACT In this paper, we propose to distinguish the distinct carrier degradation modes as a fun... more ABSTRACT In this paper, we propose to distinguish the distinct carrier degradation modes as a function of the energy range developing a complete lifetime extrapolation technique down to the low voltage operation. This provides a starting point of a more accurate modeling of CHC effects during product operations. This work shows that CHC effects in nMOSFET consist in three different regimes depending on the gate voltage (Vg). A simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions was detailed for each regime. We also propose an answer to the contradictory debate of the respective contributions of electron-electron scattering (EES) (Rauch et al., 2001) and the multiple vibrational excitation (MVE) (Hess et al., 1999) to CHC effects in the low energy range.

Research paper thumbnail of Evidence for defect-generation-driven wear-out of breakdown conduction path in ultra thin oxides

IEEE International Integrated Reliability Workshop Final Report, 2002., 2002

This paper considers the physical mechanisms responsible for the progressive (i.e. smooth or nois... more This paper considers the physical mechanisms responsible for the progressive (i.e. smooth or noisy) breakdown manifestation commonly measured on ultra-thin oxides (Tox<25 Å). First, it is verified that the theory previously published is relevant by highlighting progressive behavior predicted on thicker oxides (50 Å). Second, the stored energy is shown not to be correlated to the progressive behavior even if

Research paper thumbnail of A Cost-Effective Low Power Platform for the 45-nm Technology Node

2006 International Electron Devices Meeting, 2006

... 1 STMicroelectronics, 2 Freescale Semiconductor, 3 NXP, 850 rue Jean-Monnet, 38920 Crolles, F... more ... 1 STMicroelectronics, 2 Freescale Semiconductor, 3 NXP, 850 rue Jean-Monnet, 38920 Crolles, France 4 CEA-LETI, 17 rue des Martyrs, 38000 Grenoble, France emmanuel.josse@ st.com; phone: +33 438 92 26 07; fax: +33 438 92 29 52 Abstract ...

Research paper thumbnail of Space radiation and reliability qualifications on 65nm CMOS 600MHz microprocessors

Recent space programs have reached the limits of the current space digital ASIC offers, mainly re... more Recent space programs have reached the limits of the current space digital ASIC offers, mainly relying on CMOS 180nm. The new ST CMOS 65nm space program described in this paper shows how those limits are overcome. Small modifications to the commercial bulk process, paired with cost effective design reinforcements allow higher density and better energy efficiency while ensuring a strong space-grade resilience. The implementation of a 32-bit SPARC LEON3 microprocessor demonstrates the capabilities of this new technology.

Research paper thumbnail of New hole trapping characterization during NBTI in 65nm node technology with distinct nitridation processing

IEEE International Integrated Reliability Workshop Final Report, 2004

ABSTRACT We have developed in this work a new characterization methodology which includes stressi... more ABSTRACT We have developed in this work a new characterization methodology which includes stressing and measurement in a single experimental step. This overcomes the influence of the hole detrapping effect in ultra-thin gate-oxides (TOX=1.4-1.6 nm) and enables comparison of gate-oxide nitridation impacts on negative bias temperature instability (NBTI). This new approach offers possibilities to measure the whole degradation and to improve DC NBTI characterization in operating logic circuits.

Research paper thumbnail of Trapping and detrapping mechanism in hafnium based dielectrics characterized by pulse gate voltage techniques

IEEE International Integrated Reliability Workshop Final Report, 2004

A very efficient trapping has already been reported on transistors with Hf-based gate oxides. The... more A very efficient trapping has already been reported on transistors with Hf-based gate oxides. The authors have attributed these phenomena to the presence of electron traps at the HfO2/SiO2, interface or in the HfO2 bulk. More recent experimental results show that the trapping occurs in the bulk of the high-k dielectrics rather than at the high-k/SiO2 interface. In this work,

Research paper thumbnail of Unified Perspective of NBTI and Hot-Carrier Degradation in CMOS using on-the-Fly Bias Patterns

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007

ABSTRACT This work views NBTI and various conditions of channel hot carrier (CHC) degradation in ... more ABSTRACT This work views NBTI and various conditions of channel hot carrier (CHC) degradation in PMOS and NMOS devices from a unified perspective. This is accomplished by a novel technique using sequential application of stress biases and monitoring the degradation on-the-fly. Thereby, we are able to observe and segregate the distinct mechanisms co-existing during a particular condition of degradation. In particular, we gain critical insights into recovery phenomena, which are observed during certain conditions of CHC degradation (Mistry et al., 1991) as well as during NBTI (Rangan, 2003). These findings set the stage for consistent physical models for degradation as well as for design simulation under multiple operating modes

Research paper thumbnail of New Extensive MVHR Breakdown Models

2006 IEEE International Reliability Physics Symposium Proceedings, 2006

ABSTRACT Nowadays the SiO2 layer thickness (tox) is 1.2 nm or less, and the reliability of such u... more ABSTRACT Nowadays the SiO2 layer thickness (tox) is 1.2 nm or less, and the reliability of such ultra-thin oxide layers has become a major concern for continued scaling. Experimental observation of the empirical power law voltage-dependence was reported on ultra-thin oxides as presented in Wu et al. (2002). We have shown that this unexpected dependence could originate from the multi-vibrational excitation of the Si-H bond as stated in Ribes et al. (2004). Based on the last "multi-vibrational hydrogen release (MVHR)" model as presented in Ribes et al. (2004), we show that the MVHR model explains also oxide thickness and temperature dependences of the time to breakdown

Research paper thumbnail of Physical Modeling of Negative Bias Temperature Instabilities for Predictive Extrapolation

2006 IEEE International Reliability Physics Symposium Proceedings, 2006

Research paper thumbnail of Extraction of slow oxide trap profiles by low-frequency noise analysis: Application to hot-electron-induced degradation

2008 9th International Conference on Ultimate Integration of Silicon, 2008

Abstract We have developed a two-dimensional noise model based on a Green's function approac... more Abstract We have developed a two-dimensional noise model based on a Green's function approach. This model allows slow trap density profiles to be determined. The model was applied in the investigation of low-frequency degradation of MOSFETs stressed by hot-...

Research paper thumbnail of Post breakdown oxide lifetime based on digital circuit failure

The Reliability margin of aggressively scaled SiO-based gate dielectrics is strongly reduced. How... more The Reliability margin of aggressively scaled SiO-based gate dielectrics is strongly reduced. However, the first breakdown (BD) event of ultrathin oxide MOS devices does not always cause the functional failure of digital circuits. This opens the possibility of gaining additional reliability margins from the post-BD stage and has motivated a lot of research in this field. One of the areas of activity has been the study of the statistics of successive BD events because a very important chip lifetime enhancement is obtained when a number of BD events are tolerated without chip failure. However the lifetime extension based on basic transistor parameters shift DeltaVt, DeltaIdsat after breakdown is lacking. This paper provides the first methodology which extends the lifetime of a broken transistor using typical transistor failure criteria: DeltaVt = 50 mV and DeltaIdsat = 10%. The lifetime extension provided by this new methodology is compared to lifetime extension based on multiple brea...

Research paper thumbnail of Impact of the gate-stack change from 40nm node SiON to 28nm High-K Metal Gate on the Hot-Carrier and Bias Temperature damage

2013 IEEE International Reliability Physics Symposium (IRPS), 2013

High-K Metal-Gate 28nm node (C28) with equivalent gate-oxide thickness EOT= 1.35nm has been compa... more High-K Metal-Gate 28nm node (C28) with equivalent gate-oxide thickness EOT= 1.35nm has been compared to low power 40nm CMOS node (1.7nm) on silicon bulk. Hot-Carrier damage in C28 originates from the same permanent ΔN IT mechanism under current driven Multiple Particle (MP) interactions, relative to the SiON interface layer while border to bulk oxide traps make the larger difference between NMOS and PMOS transistors. This has been obtained by their respective temperature activation and AC response behaviors at Room Temperature and High Temperature due to the distinct proportion of accessible shallow/deep defects in the HK-MG structures.

Research paper thumbnail of New insights into gate-dielectric breakdown by electrical characterization of interfacial and oxide defects with reverse modeling methodology

2012 IEEE International Reliability Physics Symposium (IRPS), 2012

ABSTRACT A new methodology of defect characterization, through combination of measurements and si... more ABSTRACT A new methodology of defect characterization, through combination of measurements and simulations, is used to monitor the defect creation rate leading to gate-oxide breakdown. Two defect time-power creation rates were extracted, thus modifying the classical understanding of Weibull slope variation with oxide thickness. Based on our methodology, an explanation of the gate current increase prior to hard BD is proposed.

Research paper thumbnail of Breakdown mechanisms in ultra-thin oxides: impact of carrier energy and current through substrate hot carrier stress study

Microelectronic Engineering, 2004

An experimental investigation of breakdown phenomenon using substrate hot hole and electron stres... more An experimental investigation of breakdown phenomenon using substrate hot hole and electron stresses of silicon dioxide ranging in thickness from 2 to 5 nm is reported. First, we demonstrate that the scattering effect is responsible of the low activation energy already observed by other authors [J. Appl. Phys. 90(5) (2001)]. Based on a method of carrier energy measurement we characterize the scattering effect. Second, we demonstrate the decorrelation between carrier energy and carrier density showing that the carriers-carriers scattering is negligible. Finally being capable to confirm the real decorrelation between energy and density we observed a current dependence of the charge to breakdown. Besides, we give a theory using the multiple vibrational excitation of the Si-H bound [Surf. Sci. 368-377 (1996); Science 268 (1995) 1590]. Hence, we demonstrate once again that the hydrogen species behavior is strongly linked to breakdown phenomenon.

Research paper thumbnail of Correlation Technologies for Emerging Wireless Applications

Electronics, 2022

In this article, we introduce correlation technologies both at RF/mmWave and baseband frequencies... more In this article, we introduce correlation technologies both at RF/mmWave and baseband frequencies. At RF and mmWave frequencies, power-spectra and energy-spectra metrics are introduced for measuring the power-density of mobile devices and systems. New ASIC-embedded smart connectors are developed for bringing correlation-based signal processing close to antenna modules. At baseband frequencies, DSP-based convolutional accelerators are proposed for fast and accurate measurement of EVM (error vector magnitude) using correlation technologies. Porting of the DSP-based convolutional accelerators into advanced fully depleted silicon-on-insulator (FDSOI)-based ASIC platforms for co-integration with adaptive RF/mmWave front-end modules will enable real-time extraction of auto-correlation and cross-correlation functions of stochastic signals. Perspectives for optically synchronized interferometric-correlation technologies are drawn for accurate measurements in noisy environments of stochastic...

Research paper thumbnail of Robust automotive products in advanced CMOS nodes

2017 IEEE International Reliability Physics Symposium (IRPS), 2017

In this work, additional elements needed on top of conventional foundry reliability knowledge to ... more In this work, additional elements needed on top of conventional foundry reliability knowledge to enable robust automotive products in compliance with all restrictive norms are introduced. For intrinsic reliability, the main element is the reliability models (a design compatible WLR description). Their usage for design margins definition and their thorough validation at IP level is described. For extrinsics failure, two different screening procedures, Vstress and Burn-In (conventional or wafer-level), are here well documented and in use for volume production to bring the failure rate level down below 1ppm automotive target. Altogether, the global approach developed in STMicroelectronics enable robust automotive products based on controlled and validated procedures.

Research paper thumbnail of BTI induced dispersion: Challenges and opportunities for SRAM bit cell optimization

2016 IEEE International Reliability Physics Symposium (IRPS), 2016

One of major CMOS reliability concern for advanced nodes is the Bias Temperature Instability mech... more One of major CMOS reliability concern for advanced nodes is the Bias Temperature Instability mechanism. In addition to the native local process dispersion, BTI induced dispersion is becoming a field of intensive research. Important works focus on the distribution tail of the Vth shift after NBTI stress and efforts are deployed to high-sigma accurate modeling (defect-centric, Skellam). However, in many analog applications (ADC, SRAM) sensitive to devices matching, it is important to understand how the initial Vth distribution evolves in time. In this paper some key results of spread induced by BTI are reviewed for 14nm and 28nm Fully Depleted SOI from STMicroelectronics. Analysis between initial Vth and aged Vth correlation is presented. Then, measurement of fresh and post HTOL memory VDDmin is presented for different conditions of temperature and process centering. Then, a powerful algorithm of yield optimization is presented. It enables design centering and yield improvement (through devices sizing by moving the mean value and modifying the local process parameter impact on the performance spread) including ageing, under constraint of foot print.

Research paper thumbnail of Modeling of Process (Ge, N) Dependence and Mechanical Strain Impact on NBTI in HKMG SiGe GF FDSOI p-MOSFETs and RMG p-FinFETs

2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018

A physical framework is used to model time kinetics of Negative Bias Temperature Instability (NBT... more A physical framework is used to model time kinetics of Negative Bias Temperature Instability (NBTI) in Si and SiGe FDSOI p-MOSFETs and p-FinFETs. The effects of Germanium (Ge%) in the channel and Nitrogen (N%) in the High-K Metal Gate (HKMG) gate stack are explained. Mechanical strain effects in terms of STI to active distance (SA) for FDSOI and channel length (L) scaling for FinFET are explained. Band structure is calculated to correlate the process (Ge%, N%, strain) impact on device degradation. The model is included in Sentaurus Device TCAD to predict NBTI kinetics in Si and SiGe FinFETs.

Research paper thumbnail of Memory OTP-based MOSFET devices

Research paper thumbnail of Improve Macroscopic Degradation Modeling of MOSFETs

Degradation modeling is based usually on macroscopic parameters which can yield to wrong conclusi... more Degradation modeling is based usually on macroscopic parameters which can yield to wrong conclusions, since similar degradation might result from very different microscopic situations. The focus on degradation modeling at a microscopic level is proposed. Other authors only compare results from different characterization methods on their common measurement area. This paper proposes to use their complementarities to extend the probed areas. A more accurate determination of defects is obtained with multiple characterization method cross-fertilization allowing 1) ascertaining defect localizations, 2) extending probed areas and 3) identifying microscopic differences between similar macroscopic parameters. The tested devices are NMOS transistors with a 5 nm SiO2 gate oxide and with various gate geometries. INTRODUCTION The development of new technology nodes has seen the arising importance of accurate degradation characterization. Recent work on Hot Carrier Stress (HCS) modeling has consi...

Research paper thumbnail of New Hot-Carrier Lifetime Technique for High- to Low-Supplied Voltage nMOSFETs

2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2007

ABSTRACT In this paper, we propose to distinguish the distinct carrier degradation modes as a fun... more ABSTRACT In this paper, we propose to distinguish the distinct carrier degradation modes as a function of the energy range developing a complete lifetime extrapolation technique down to the low voltage operation. This provides a starting point of a more accurate modeling of CHC effects during product operations. This work shows that CHC effects in nMOSFET consist in three different regimes depending on the gate voltage (Vg). A simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions was detailed for each regime. We also propose an answer to the contradictory debate of the respective contributions of electron-electron scattering (EES) (Rauch et al., 2001) and the multiple vibrational excitation (MVE) (Hess et al., 1999) to CHC effects in the low energy range.

Research paper thumbnail of Evidence for defect-generation-driven wear-out of breakdown conduction path in ultra thin oxides

IEEE International Integrated Reliability Workshop Final Report, 2002., 2002

This paper considers the physical mechanisms responsible for the progressive (i.e. smooth or nois... more This paper considers the physical mechanisms responsible for the progressive (i.e. smooth or noisy) breakdown manifestation commonly measured on ultra-thin oxides (Tox<25 Å). First, it is verified that the theory previously published is relevant by highlighting progressive behavior predicted on thicker oxides (50 Å). Second, the stored energy is shown not to be correlated to the progressive behavior even if

Research paper thumbnail of A Cost-Effective Low Power Platform for the 45-nm Technology Node

2006 International Electron Devices Meeting, 2006

... 1 STMicroelectronics, 2 Freescale Semiconductor, 3 NXP, 850 rue Jean-Monnet, 38920 Crolles, F... more ... 1 STMicroelectronics, 2 Freescale Semiconductor, 3 NXP, 850 rue Jean-Monnet, 38920 Crolles, France 4 CEA-LETI, 17 rue des Martyrs, 38000 Grenoble, France emmanuel.josse@ st.com; phone: +33 438 92 26 07; fax: +33 438 92 29 52 Abstract ...

Research paper thumbnail of Space radiation and reliability qualifications on 65nm CMOS 600MHz microprocessors

Recent space programs have reached the limits of the current space digital ASIC offers, mainly re... more Recent space programs have reached the limits of the current space digital ASIC offers, mainly relying on CMOS 180nm. The new ST CMOS 65nm space program described in this paper shows how those limits are overcome. Small modifications to the commercial bulk process, paired with cost effective design reinforcements allow higher density and better energy efficiency while ensuring a strong space-grade resilience. The implementation of a 32-bit SPARC LEON3 microprocessor demonstrates the capabilities of this new technology.

Research paper thumbnail of New hole trapping characterization during NBTI in 65nm node technology with distinct nitridation processing

IEEE International Integrated Reliability Workshop Final Report, 2004

ABSTRACT We have developed in this work a new characterization methodology which includes stressi... more ABSTRACT We have developed in this work a new characterization methodology which includes stressing and measurement in a single experimental step. This overcomes the influence of the hole detrapping effect in ultra-thin gate-oxides (TOX=1.4-1.6 nm) and enables comparison of gate-oxide nitridation impacts on negative bias temperature instability (NBTI). This new approach offers possibilities to measure the whole degradation and to improve DC NBTI characterization in operating logic circuits.

Research paper thumbnail of Trapping and detrapping mechanism in hafnium based dielectrics characterized by pulse gate voltage techniques

IEEE International Integrated Reliability Workshop Final Report, 2004

A very efficient trapping has already been reported on transistors with Hf-based gate oxides. The... more A very efficient trapping has already been reported on transistors with Hf-based gate oxides. The authors have attributed these phenomena to the presence of electron traps at the HfO2/SiO2, interface or in the HfO2 bulk. More recent experimental results show that the trapping occurs in the bulk of the high-k dielectrics rather than at the high-k/SiO2 interface. In this work,

Research paper thumbnail of Unified Perspective of NBTI and Hot-Carrier Degradation in CMOS using on-the-Fly Bias Patterns

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007

ABSTRACT This work views NBTI and various conditions of channel hot carrier (CHC) degradation in ... more ABSTRACT This work views NBTI and various conditions of channel hot carrier (CHC) degradation in PMOS and NMOS devices from a unified perspective. This is accomplished by a novel technique using sequential application of stress biases and monitoring the degradation on-the-fly. Thereby, we are able to observe and segregate the distinct mechanisms co-existing during a particular condition of degradation. In particular, we gain critical insights into recovery phenomena, which are observed during certain conditions of CHC degradation (Mistry et al., 1991) as well as during NBTI (Rangan, 2003). These findings set the stage for consistent physical models for degradation as well as for design simulation under multiple operating modes

Research paper thumbnail of New Extensive MVHR Breakdown Models

2006 IEEE International Reliability Physics Symposium Proceedings, 2006

ABSTRACT Nowadays the SiO2 layer thickness (tox) is 1.2 nm or less, and the reliability of such u... more ABSTRACT Nowadays the SiO2 layer thickness (tox) is 1.2 nm or less, and the reliability of such ultra-thin oxide layers has become a major concern for continued scaling. Experimental observation of the empirical power law voltage-dependence was reported on ultra-thin oxides as presented in Wu et al. (2002). We have shown that this unexpected dependence could originate from the multi-vibrational excitation of the Si-H bond as stated in Ribes et al. (2004). Based on the last "multi-vibrational hydrogen release (MVHR)" model as presented in Ribes et al. (2004), we show that the MVHR model explains also oxide thickness and temperature dependences of the time to breakdown

Research paper thumbnail of Physical Modeling of Negative Bias Temperature Instabilities for Predictive Extrapolation

2006 IEEE International Reliability Physics Symposium Proceedings, 2006

Research paper thumbnail of Extraction of slow oxide trap profiles by low-frequency noise analysis: Application to hot-electron-induced degradation

2008 9th International Conference on Ultimate Integration of Silicon, 2008

Abstract We have developed a two-dimensional noise model based on a Green's function approac... more Abstract We have developed a two-dimensional noise model based on a Green's function approach. This model allows slow trap density profiles to be determined. The model was applied in the investigation of low-frequency degradation of MOSFETs stressed by hot-...

Research paper thumbnail of Post breakdown oxide lifetime based on digital circuit failure

The Reliability margin of aggressively scaled SiO-based gate dielectrics is strongly reduced. How... more The Reliability margin of aggressively scaled SiO-based gate dielectrics is strongly reduced. However, the first breakdown (BD) event of ultrathin oxide MOS devices does not always cause the functional failure of digital circuits. This opens the possibility of gaining additional reliability margins from the post-BD stage and has motivated a lot of research in this field. One of the areas of activity has been the study of the statistics of successive BD events because a very important chip lifetime enhancement is obtained when a number of BD events are tolerated without chip failure. However the lifetime extension based on basic transistor parameters shift DeltaVt, DeltaIdsat after breakdown is lacking. This paper provides the first methodology which extends the lifetime of a broken transistor using typical transistor failure criteria: DeltaVt = 50 mV and DeltaIdsat = 10%. The lifetime extension provided by this new methodology is compared to lifetime extension based on multiple brea...

Research paper thumbnail of Impact of the gate-stack change from 40nm node SiON to 28nm High-K Metal Gate on the Hot-Carrier and Bias Temperature damage

2013 IEEE International Reliability Physics Symposium (IRPS), 2013

High-K Metal-Gate 28nm node (C28) with equivalent gate-oxide thickness EOT= 1.35nm has been compa... more High-K Metal-Gate 28nm node (C28) with equivalent gate-oxide thickness EOT= 1.35nm has been compared to low power 40nm CMOS node (1.7nm) on silicon bulk. Hot-Carrier damage in C28 originates from the same permanent ΔN IT mechanism under current driven Multiple Particle (MP) interactions, relative to the SiON interface layer while border to bulk oxide traps make the larger difference between NMOS and PMOS transistors. This has been obtained by their respective temperature activation and AC response behaviors at Room Temperature and High Temperature due to the distinct proportion of accessible shallow/deep defects in the HK-MG structures.

Research paper thumbnail of New insights into gate-dielectric breakdown by electrical characterization of interfacial and oxide defects with reverse modeling methodology

2012 IEEE International Reliability Physics Symposium (IRPS), 2012

ABSTRACT A new methodology of defect characterization, through combination of measurements and si... more ABSTRACT A new methodology of defect characterization, through combination of measurements and simulations, is used to monitor the defect creation rate leading to gate-oxide breakdown. Two defect time-power creation rates were extracted, thus modifying the classical understanding of Weibull slope variation with oxide thickness. Based on our methodology, an explanation of the gate current increase prior to hard BD is proposed.

Research paper thumbnail of Breakdown mechanisms in ultra-thin oxides: impact of carrier energy and current through substrate hot carrier stress study

Microelectronic Engineering, 2004

An experimental investigation of breakdown phenomenon using substrate hot hole and electron stres... more An experimental investigation of breakdown phenomenon using substrate hot hole and electron stresses of silicon dioxide ranging in thickness from 2 to 5 nm is reported. First, we demonstrate that the scattering effect is responsible of the low activation energy already observed by other authors [J. Appl. Phys. 90(5) (2001)]. Based on a method of carrier energy measurement we characterize the scattering effect. Second, we demonstrate the decorrelation between carrier energy and carrier density showing that the carriers-carriers scattering is negligible. Finally being capable to confirm the real decorrelation between energy and density we observed a current dependence of the charge to breakdown. Besides, we give a theory using the multiple vibrational excitation of the Si-H bound [Surf. Sci. 368-377 (1996); Science 268 (1995) 1590]. Hence, we demonstrate once again that the hydrogen species behavior is strongly linked to breakdown phenomenon.