Hani Ahmad - Academia.edu (original) (raw)

Papers by Hani Ahmad

Journal of Circuits, Systems and Computers

This work presents a fully integrated mixed-mode low-dropout voltage regulator that achieves a fa... more This work presents a fully integrated mixed-mode low-dropout voltage regulator that achieves a fast transient response by utilizing two feedback mechanisms. The first feedback mechanism is the conventional analog regulation that includes an operational amplifier. The second feedback mechanism is based on digitizing any fast change in the output voltage using multiple comparators and subsequently enabling either an NMOS-based or a PMOS-based current DAC. The DAC provides current in opposite polarity to the sharp transient change in load current. As a result, addressing sharp changes in load current is not limited by the gain–bandwidth product of the error amplifier. The LDO was implemented using 180-nm CMOS technology devices. It uses a supply voltage input range of 1.6–2[Formula: see text]V and produces an output voltage of 1.2[Formula: see text]V. In simulations, the LDO regulator achieves 143-[Formula: see text] A quiescent current, [Formula: see text]56-dB PSRR @ 1-kHz noise freq...

Jordanian Journal of Computers and Information Technology

PCCC 2005. 24th IEEE International Performance, Computing, and Communications Conference, 2005., 2005

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

... ISSCC 2010 / SESSION 10 / DC-DC POWER CONVERSION / 10.4 10.4 A 300mA 14mV-Ripple Digitally Co... more ... ISSCC 2010 / SESSION 10 / DC-DC POWER CONVERSION / 10.4 10.4 A 300mA 14mV-Ripple Digitally Controlled Buck Converter Using Frequency Domain ΔΣ ADC and Hybrid PWM Generator Hani H Ahmad, Bertan Bakkaloglu Arizona State University, Tempe, AZ ...

2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010

... [3] Syed, E. Ahmad and D. Maksimovic, “Digital ... 6, pp. 4689-4695, June 2004. [4] M. Hovin,... more ... [3] Syed, E. Ahmad and D. Maksimovic, “Digital ... 6, pp. 4689-4695, June 2004. [4] M. Hovin, A. Olsen, TS Lande and C. Toumazou, “Delta-Sigma Modulators using Frequency-Modulated Intermediate Values” IEEE Journal of Solid-Sate Circuits, vol. 32, no. 1, pp. 13-22, Jan 1997. ...

2020 32nd International Conference on Microelectronics (ICM)

A DC-DC boost-converter-based, three-string White LED (WLED) driver with pure combinational logic... more A DC-DC boost-converter-based, three-string White LED (WLED) driver with pure combinational logic in the forward voltage compensation circuit is presented. The proposed architecture optimizes efficiency with the presence of different forward voltage drop across each WLED connected in series in one string and among different strings. The strings don’t even need to be balanced (could have different numbers of WLEDs per string). The efficiency optimization is done via setting the minimum proper voltage (in real-time) at the output of the boost converter that activates all parallel strings and by choosing the appropriate arrangement of strings (number of strings and number of WLEDs in each string). Each string has a constant regulated current of 25 mA to drive the series-connected WLEDs in that string. An efficiency of 88.85 % was achieved with input voltage ranges between 3 V to 3.8 V and output voltage up to 25 V . The circuit is implemented using a 40 nm TSMC CMOS process.

This paper describes a novel feedback digitization architecture for a digitally controlled PWM DC... more This paper describes a novel feedback digitization architecture for a digitally controlled PWM DC-DC buck converter. A combination of a VCO followed by an all digital first-order Σ−∆ frequency discriminators (SDFD) is used as a feedback analog-to-digital converter (ADC). The output of the discriminator is decimated to obtain a higher resolution depending on the output ripple specifications. A block diagram and a behavioral model are presented along with simulation results. Based on 1% allowed output voltage ripple, a 8-bit ADC resolution is achieved using a reference clock frequency of 16MHz. Since the SNR of this ADC is a strong function of sampling clock frequency and carrier frequency deviation, it is easy to achieve higher accuracy (resolution) to satisfy wide range of regulation and accuracy requirements. This architecture is flexible and scalable and can fully be implemented in standard digital CMOS.

Journal of Circuits, Systems and Computers

This work presents a fully integrated mixed-mode low-dropout voltage regulator that achieves a fa... more This work presents a fully integrated mixed-mode low-dropout voltage regulator that achieves a fast transient response by utilizing two feedback mechanisms. The first feedback mechanism is the conventional analog regulation that includes an operational amplifier. The second feedback mechanism is based on digitizing any fast change in the output voltage using multiple comparators and subsequently enabling either an NMOS-based or a PMOS-based current DAC. The DAC provides current in opposite polarity to the sharp transient change in load current. As a result, addressing sharp changes in load current is not limited by the gain–bandwidth product of the error amplifier. The LDO was implemented using 180-nm CMOS technology devices. It uses a supply voltage input range of 1.6–2[Formula: see text]V and produces an output voltage of 1.2[Formula: see text]V. In simulations, the LDO regulator achieves 143-[Formula: see text] A quiescent current, [Formula: see text]56-dB PSRR @ 1-kHz noise freq...

Jordanian Journal of Computers and Information Technology

PCCC 2005. 24th IEEE International Performance, Computing, and Communications Conference, 2005., 2005

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

... ISSCC 2010 / SESSION 10 / DC-DC POWER CONVERSION / 10.4 10.4 A 300mA 14mV-Ripple Digitally Co... more ... ISSCC 2010 / SESSION 10 / DC-DC POWER CONVERSION / 10.4 10.4 A 300mA 14mV-Ripple Digitally Controlled Buck Converter Using Frequency Domain ΔΣ ADC and Hybrid PWM Generator Hani H Ahmad, Bertan Bakkaloglu Arizona State University, Tempe, AZ ...

2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010

... [3] Syed, E. Ahmad and D. Maksimovic, “Digital ... 6, pp. 4689-4695, June 2004. [4] M. Hovin,... more ... [3] Syed, E. Ahmad and D. Maksimovic, “Digital ... 6, pp. 4689-4695, June 2004. [4] M. Hovin, A. Olsen, TS Lande and C. Toumazou, “Delta-Sigma Modulators using Frequency-Modulated Intermediate Values” IEEE Journal of Solid-Sate Circuits, vol. 32, no. 1, pp. 13-22, Jan 1997. ...

2020 32nd International Conference on Microelectronics (ICM)

A DC-DC boost-converter-based, three-string White LED (WLED) driver with pure combinational logic... more A DC-DC boost-converter-based, three-string White LED (WLED) driver with pure combinational logic in the forward voltage compensation circuit is presented. The proposed architecture optimizes efficiency with the presence of different forward voltage drop across each WLED connected in series in one string and among different strings. The strings don’t even need to be balanced (could have different numbers of WLEDs per string). The efficiency optimization is done via setting the minimum proper voltage (in real-time) at the output of the boost converter that activates all parallel strings and by choosing the appropriate arrangement of strings (number of strings and number of WLEDs in each string). Each string has a constant regulated current of 25 mA to drive the series-connected WLEDs in that string. An efficiency of 88.85 % was achieved with input voltage ranges between 3 V to 3.8 V and output voltage up to 25 V . The circuit is implemented using a 40 nm TSMC CMOS process.

This paper describes a novel feedback digitization architecture for a digitally controlled PWM DC... more This paper describes a novel feedback digitization architecture for a digitally controlled PWM DC-DC buck converter. A combination of a VCO followed by an all digital first-order Σ−∆ frequency discriminators (SDFD) is used as a feedback analog-to-digital converter (ADC). The output of the discriminator is decimated to obtain a higher resolution depending on the output ripple specifications. A block diagram and a behavioral model are presented along with simulation results. Based on 1% allowed output voltage ripple, a 8-bit ADC resolution is achieved using a reference clock frequency of 16MHz. Since the SNR of this ADC is a strong function of sampling clock frequency and carrier frequency deviation, it is easy to achieve higher accuracy (resolution) to satisfy wide range of regulation and accuracy requirements. This architecture is flexible and scalable and can fully be implemented in standard digital CMOS.