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Papers by Hasan Sohofi

Forum on specification and Design Languages, 2007

Fifteenth International Symposium on Quality Electronic Design, 2014

As design abstraction has now got to its next upper level that is System Level, one of the main c... more As design abstraction has now got to its next upper level that is System Level, one of the main challenges in this area is how to verify designs that are modeled at System Level. In this paper, we are presenting an environment for functionally verifying system-level designs using assertions. This environment adapts existing EDA simulation tools, which are mainly used for RTL design and verification, and utilizes them for system level verification. In this environment, designs are modeled in SystemC-TLM 2.0, and assertions are written in SystemVerilog. Design and verification parts are connected together using SystemVerilog DPI mechanism, and designs are verified against system level assertions in the course of simulation.

Microprocess. Microsystems, 2014

This paper presents a hardware based solution for a scalable runtime address generation scheme fo... more This paper presents a hardware based solution for a scalable runtime address generation scheme for DSP applications mapped to a parallel distributed coarse grain reconfigurable computation and storage fabric. The scheme can also deal with non-affine functions of multiple variables that typically correspond to multiple nested loops. The key innovation is the judicious use of two categories of address generation resources. The first category of resource is the low cost AGU that generates addresses for given address bounds for affine functions of up to two variables. Such low cost AGUs are distributed and associated with every read/write port in the distributed memory architecture. The second category of resource is relatively more complex but is also distributed but shared among a few storage units and is capable of handling more complex address generation requirements like dynamic computation of address bounds that are then used to configure the AGUs, transformation of non-affine fun...

This paper presents Anahita Processor Description Language (APDL) for generation of retargetable ... more This paper presents Anahita Processor Description Language (APDL) for generation of retargetable processor design tool sets. The emphasis is on the applicability of the generated tools in the design space exploration (DSE) phase of designing a new embedded processor. APDL descriptions can be used for generating cycle-accurate instruction set simulators, assembler/disassembler tools, production quality compilers and architecture verification tools. The paper first investigates the features required for a language to be useful for DSE and then presents APDL constructs along with code samples.

2010 15th Ieee European Test Symposium, May 24, 2010

2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015

In spite of decades of research, only a small percentage of hardware is designed using high-level... more In spite of decades of research, only a small percentage of hardware is designed using high-level synthesis because of the large gap between the abstraction levels of standard cells and algorithmic level. We propose a grid-based regular physical design platform composed of large grain hardened building blocks called SiLago blocks. This platform is divided into regions which are specialized for different functionalities like computation, storage, system control, etc. The characterized micro-architectural operations of the SiLago platform serve as the interface to meet-in-the-middle high-level and system-level syntheses framework. This framework was used to generate three hardware macro instances, derived from SiLago platform for three applications from signal processing domain. Results show two orders of magnitude improvements in efficiency of the system-level design space exploration and synthesis time, with average loss in design quality of 18% for energy and 54% for area compared to the commercial SOC flow.

IEICE Electronics Express, 2007

Two of the most challenging issues in online testing are deriving a general tester scheme for var... more Two of the most challenging issues in online testing are deriving a general tester scheme for various circuits and reducing the area overhead. This paper presents a novel reconfigurable online tester using artificial neural networks to test combinational hardware. Our proposed BIST architecture has the capability of testing a number of arbitrary sub-modules of a big design simultaneously by time-multiplexing between them. Output partitioning method is proposed as a powerful technique to reduce neural network training time and the tester area overhead. Our experimental results show that after proper partitioning the average area overhead is reduced by 16% in data-path and 33% in memory area. Also average fault detection latency has been improved by 14%.

25th IEEE VLSI Test Symmposium (VTS'07), 2007

Forum on specification and Design Languages, 2007

Fifteenth International Symposium on Quality Electronic Design, 2014

As design abstraction has now got to its next upper level that is System Level, one of the main c... more As design abstraction has now got to its next upper level that is System Level, one of the main challenges in this area is how to verify designs that are modeled at System Level. In this paper, we are presenting an environment for functionally verifying system-level designs using assertions. This environment adapts existing EDA simulation tools, which are mainly used for RTL design and verification, and utilizes them for system level verification. In this environment, designs are modeled in SystemC-TLM 2.0, and assertions are written in SystemVerilog. Design and verification parts are connected together using SystemVerilog DPI mechanism, and designs are verified against system level assertions in the course of simulation.

Microprocess. Microsystems, 2014

This paper presents a hardware based solution for a scalable runtime address generation scheme fo... more This paper presents a hardware based solution for a scalable runtime address generation scheme for DSP applications mapped to a parallel distributed coarse grain reconfigurable computation and storage fabric. The scheme can also deal with non-affine functions of multiple variables that typically correspond to multiple nested loops. The key innovation is the judicious use of two categories of address generation resources. The first category of resource is the low cost AGU that generates addresses for given address bounds for affine functions of up to two variables. Such low cost AGUs are distributed and associated with every read/write port in the distributed memory architecture. The second category of resource is relatively more complex but is also distributed but shared among a few storage units and is capable of handling more complex address generation requirements like dynamic computation of address bounds that are then used to configure the AGUs, transformation of non-affine fun...

This paper presents Anahita Processor Description Language (APDL) for generation of retargetable ... more This paper presents Anahita Processor Description Language (APDL) for generation of retargetable processor design tool sets. The emphasis is on the applicability of the generated tools in the design space exploration (DSE) phase of designing a new embedded processor. APDL descriptions can be used for generating cycle-accurate instruction set simulators, assembler/disassembler tools, production quality compilers and architecture verification tools. The paper first investigates the features required for a language to be useful for DSE and then presents APDL constructs along with code samples.

2010 15th Ieee European Test Symposium, May 24, 2010

2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015

In spite of decades of research, only a small percentage of hardware is designed using high-level... more In spite of decades of research, only a small percentage of hardware is designed using high-level synthesis because of the large gap between the abstraction levels of standard cells and algorithmic level. We propose a grid-based regular physical design platform composed of large grain hardened building blocks called SiLago blocks. This platform is divided into regions which are specialized for different functionalities like computation, storage, system control, etc. The characterized micro-architectural operations of the SiLago platform serve as the interface to meet-in-the-middle high-level and system-level syntheses framework. This framework was used to generate three hardware macro instances, derived from SiLago platform for three applications from signal processing domain. Results show two orders of magnitude improvements in efficiency of the system-level design space exploration and synthesis time, with average loss in design quality of 18% for energy and 54% for area compared to the commercial SOC flow.

IEICE Electronics Express, 2007

Two of the most challenging issues in online testing are deriving a general tester scheme for var... more Two of the most challenging issues in online testing are deriving a general tester scheme for various circuits and reducing the area overhead. This paper presents a novel reconfigurable online tester using artificial neural networks to test combinational hardware. Our proposed BIST architecture has the capability of testing a number of arbitrary sub-modules of a big design simultaneously by time-multiplexing between them. Output partitioning method is proposed as a powerful technique to reduce neural network training time and the tester area overhead. Our experimental results show that after proper partitioning the average area overhead is reduced by 16% in data-path and 33% in memory area. Also average fault detection latency has been improved by 14%.

25th IEEE VLSI Test Symmposium (VTS'07), 2007

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