Hazem Abd - Academia.edu (original) (raw)
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Visvesvaraya Technological University
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Papers by Hazem Abd
Reed-Solomon (RS) codes have a widespread use to provide error protection especially for burst er... more Reed-Solomon (RS) codes have a widespread use to provide error protection especially for burst errors. This feature has been an important factor in adopting RS codes in many practical applications such as wireless communication system, cable modem, computer memory. The most popular RS decoder architecture , can be summarized into four steps : 1) calculating the syndromes from the received codeword; 2) computing the error locator polynomial and the error evaluator polynomial; 3) finding the error locations; and 4) computing error values. This thesis proposes an area efficient, low energy, high speed architecture for a Reed-Solomon RS(255,239) decoder based on Decomposed Inversionless Berlekamp-Massey Algorithm, where the error locator and evaluator polynomial can be computed serially. In the proposed architecture, a new scheduling of t finite field multipliers is used to calculate the error locator and evaluator polynomials to achieve a good balance between area, latency, and throughput. This architecture is tested in two different decoders. The first one is a two parallel decoder, as two parallel syndrome and two parallel Chien search are used. The second one is a serial decoder, as serial syndrome and Chien search are used. In our architectures we have investigated hardware area, throughput, and energy per symbol and we did a good optimization between the latency, throughput, and energy per symbol while maintaining a small area.
Reed-Solomon (RS) codes have a widespread use to provide error protection especially for burst er... more Reed-Solomon (RS) codes have a widespread use to provide error protection especially for burst errors. This feature has been an important factor in adopting RS codes in many practical applications such as wireless communication system, cable modem, computer memory. The most popular RS decoder architecture , can be summarized into four steps : 1) calculating the syndromes from the received codeword; 2) computing the error locator polynomial and the error evaluator polynomial; 3) finding the error locations; and 4) computing error values. This thesis proposes an area efficient, low energy, high speed architecture for a Reed-Solomon RS(255,239) decoder based on Decomposed Inversionless Berlekamp-Massey Algorithm, where the error locator and evaluator polynomial can be computed serially. In the proposed architecture, a new scheduling of t finite field multipliers is used to calculate the error locator and evaluator polynomials to achieve a good balance between area, latency, and throughput. This architecture is tested in two different decoders. The first one is a two parallel decoder, as two parallel syndrome and two parallel Chien search are used. The second one is a serial decoder, as serial syndrome and Chien search are used. In our architectures we have investigated hardware area, throughput, and energy per symbol and we did a good optimization between the latency, throughput, and energy per symbol while maintaining a small area.