Hervé Petit - Academia.edu (original) (raw)

Papers by Hervé Petit

Journal of Low Power Electronics, 2012

ABSTRACT In this paper, we propose a methodology for simultaneously analyzing the ageing effects ... more ABSTRACT In this paper, we propose a methodology for simultaneously analyzing the ageing effects and process variations. Nominal ageing simulation and statistical methods are applied to reliability simulation of AMS integrated circuits and systems. Response surface modeling (RSM) is used to build direct relationship between process parameters and circuit/system performances. With Varied/fixed RSMs, designers can have reliability information of designed circuit/system. Also, this methodology has been developed with behavioral modeling for reliability consideration of large AMS circuits and systems (e.g., modulator, RF front-end). Conventional Monte-Carlo (MC) method is infeasible in these complex circuits and systems. The methodology is validated with a series of circuits and systems in 65 nm CMOS technology: simple current mirrors, a dynamic comparator and a 2nd order continuous-time analog-to-digital modulator. It is shown that this methodology can provide designers with reliability information graphically with a general perspective. It can achieve better simulation efficiency than traditional Monte-Carlo analysis, while still guaranteeing good simulation accuracy.

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2013

ABSTRACT Noise-immunity is an important design criterion with CMOS dimension scaling to nanometer... more ABSTRACT Noise-immunity is an important design criterion with CMOS dimension scaling to nanometers. Furthermore, nanometer circuits devices are also more prone to soft errors induced by single event transients (SETs). In this work, we set up a model to analyze the reliability induced by both SETs and noise. We derive the constraints for the reliability enhancement of logic circuits for allowing design circuits with both better noise-immunity and higher tolerance to soft errors. Simulation combining Hspice and Matlab are given to verify the proposed constraints.

Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010

Page 1. AMS and RF Design for Reliability Methodology Pietro M. Ferreira, Hervé Petit and Jean-Fr... more Page 1. AMS and RF Design for Reliability Methodology Pietro M. Ferreira, Hervé Petit and Jean-François Naviner Institut TELECOM ; TELECOM ParisTech ; CNRS LTCI ; ParisTech maris@ieee.org,(herve.petit,jean-francois.naviner)@telecom-paristech.fr ...

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011

Page 1. A New Synthesis Methodology for Reliable RF front-end Design Pietro M. Ferreira, Hervé Pe... more Page 1. A New Synthesis Methodology for Reliable RF front-end Design Pietro M. Ferreira, Hervé Petit and Jean-François Naviner Institut TELECOM ; TELECOM ParisTech ; CNRS LTCI ; ParisTech maris@ieee.org,(herve.petit,jean-francois.naviner)@telecom-paristech.fr ...

2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, 2009

Radio frequency (RF) products are very demanding in terms of technology developments. Reliability... more Radio frequency (RF) products are very demanding in terms of technology developments. Reliability will be one of the most important challenges for the semiconductor industry during the following years. This work presents a wideband low noise amplifier (WBLNA) designed in CMOS 65 nm, its model for reliability estimation, and simulated results of fresh and aged devices. The WBLNA failure, defined

Reliability becomes a critical challenge in analogue integrated circuits (ICs) design in deep sub... more Reliability becomes a critical challenge in analogue integrated circuits (ICs) design in deep sub-micron region. In order to manufacture ICs with high quality, methodology and analysis must include reliability consideration in design loop. In this paper, we propose a new statistical reliability-aware approach to evaluate circuit performance under ageing effects and process variations. BSIM4 transistor physical parameters are investigated. The non-dominated sorting-based multi-objective evolutionary algorithms is used to find the worst-case aged circuit performances. This approach is studied with a two stage Miller-operational-amplifier (Op-Amp) with 65nm CMOS technology. Simulation results show that the Op-Amp is HCI non-sensitive but suffer from NBTI degradation. Compared to traditional Monte-Carlo method, simulation time is reduced to 40%, with a trade-off of only 0.05% to 1.7% accuracy loss.

Microelectronics Reliability, 2014

ABSTRACT In order to achieve reliability study in large and complex analog and mixed signal (AMS)... more ABSTRACT In order to achieve reliability study in large and complex analog and mixed signal (AMS) circuits and systems, it is required to develop effective reliability-aware design methodologies and exploration tools. This paper discusses two aging mechanisms: hot carrier injection (HCI) and negative bias temperature instability (NBTI) and their effect on 65 nm CMOS integrated circuits and systems (ICs). We propose an aging-aware cross-layer approach to comprehensively evaluate aging induced performance degradation at the abstraction (system) level. This approach is composed by hierarchical aging analysis at transistor/circuit level, block failure analysis at abstraction level and system-level aging considerations, which can essentially highlight sensitive blocks for circuit designers. This approach is demonstrated with a continuous-time (CT) sigma-delta ( ) modulator. Analog loop filter and clock distributor are studied with failure boundary and transistor level aging simulation. The aging investigation approach reports system level aging-aware consideration of these building blocks. Results show that amplifiers in analog loop filter have enough margin to cope with aging induced degradations. However, aging risk exists in clock circuits, especially when implementing with high transistors. NBTI induced clock jitter from clock distributor can influence clocked block in CT modulator and degrade signal-to-noise ratio (SNR).

Microelectronics Reliability, 2011

Circuit ageing degradation is becoming worse in advanced technologies, while application fields l... more Circuit ageing degradation is becoming worse in advanced technologies, while application fields like military, medical and energy demand more reliability. Thus, reliability is one of the most important challenges of the semiconductor industry . In this work, we review the physical ageing phenomena, their simulation model, and how they can be avoided. Then, we propose a synthesis methodology composed of classical circuit optimization with the reliability analysis in earlier stages. Also, the variability of the integration process technology is taken into account. We compare a classical and a reliable designed digital controlled oscillator (DCO) in order to show a reduction of 16% in the oscillation frequency ageing degradation. In this way, the reliable design makes the circuit lifetime five times longer, if we fix the maximum frequency ageing degradation at 2.0%. Finally, we present the reliability as a design criterion, advantages and disadvantages of our methodology.

Circuit ageing degradation is becoming worse in advanced node technologies, where low power and l... more Circuit ageing degradation is becoming worse in advanced node technologies, where low power and low cost RF front-end should be implemented. Thus, reliability is one of the most important challenges. In this work, we analyze a WLAN/WiMAX RF front-end architecture reliability with a behavioral description language (VerilogA) using a top-down approach. We have found the sensitive building blocks and the worst performance variations. We pointed out the programmable gain amplifier (PGA) as the most sensitive building block. The PGA failure is responsible for the degradation of the gain, the noise, and the linearity of the architecture. In low frequency signals, the digital controlled oscillator (DCO) becomes the dominant source of noise degradation.

annals of …, 2002

An ideal radio communication receiver places the analog to digital conversion just after the ante... more An ideal radio communication receiver places the analog to digital conversion just after the antenna. It is an objective in a Òsoftware radioÓ perspective. The available silicon technologies do not provide the performance required by this application. We are able to evaluate the present limits and the gap between these limits and the ideal solution proposed. In this paper, we describe the present possibilities in terms of receiver architectures and we deduce the ADC speciÞcations. Then we analyse different ADC architectures adapted to this application. The choice is mainly between pipeline and sigma-delta ADC. We compare them in terms of power consumption and we introduce a factor of merit. The future technologies will have an impact on ADC performance. Superconductor technology applied to ADC may be a solution and it is analysed at the end of this paper.