Hisao Katto - Academia.edu (original) (raw)

Papers by Hisao Katto

1985 Symposium on VLSI Technology. Digest of Technical Papers, 1985

INTRODUCTION Hot carrier instability is known to be a strong function of stress biases, and usual... more INTRODUCTION Hot carrier instability is known to be a strong function of stress biases, and usually go degradation results especially for the case of p-SiN passivation El). The purpose of this paper is to present a practical evaluation method of hot carrier instability and thoroughly characterize the stress bias dependence. Based on the method, the fabrication process dependence of hot carrier instability and the extraporated long term lifetime at 5V operations is discussed. SAMPLE PREPARATION AND MEASUREMENT The n+ poly gate devices were fabricated by the 2pgm CMOS process with tox= 350A with different oxidation methods and passivation films. The source and drain has xj= 0.3pm with As implant. To compare different types of devices, the devices with the same substrate current peak IBBmax at VD= 5V are carefully selected for the stress test from among the devices with approximately the same gate lengths. To monitor the gm degradation effectively, Vt was defined to be the gate voltage...

Technical Digest., International Electron Devices Meeting

The authors report on the improvement of the hot-carrier instability of MOSFETs by putting a plas... more The authors report on the improvement of the hot-carrier instability of MOSFETs by putting a plasma silicon oxide (P-SiO) of specific composition between the MOSFETs and the plasma silicon nitride (P-SiN) passivation layer. The P-SiO was found to have the capability of completely blocking hydrogen diffusion and water penetration. The hydrogen-blocking effect is attributed to hydrogen trapping by the dangling

1980 International Electron Devices Meeting, 1980

A new structure for a Floating Si-gate Channel Corner Avalanche Transition nonvolatile memory dev... more A new structure for a Floating Si-gate Channel Corner Avalanche Transition nonvolatile memory device (FCAT-II) is described. The new structure uses a modification of the previously reported FCAT (FCAT-I). The key improvement is that the floating gate couples better with the control gate. This device can oprate in both write and erase modes under high speed ( ≥ 50 ns( and low voltage ( ≤ 15 V) condition. Another useful feature is the saturation of the high level thresold voltage independent of write pulse widhs greater than 50 ns.

2001 IEEE International Integrated Reliability Workshop. Final Report (Cat. No.01TH8580)

The paper reports on the newly analyzed BT instability that can threaten scaled CMOS devices. Dur... more The paper reports on the newly analyzed BT instability that can threaten scaled CMOS devices. During the development of 1.8V technology with surface-channel PMOSFETs, a large PMOS negative bias instability is found. The instability resembles the reported NBTI, but three different modes are found through detailed analyses: PMOS degrades under both stress polarities (p+, p-), and NMOS degrades slowly and only under negative V/sub G/ (n-). Through the detailed analysis of MOSFET and MOSC degradation, positive fixed charges are not found, and it is confirmed that the generation of donor surface states is common to all three modes of degradation. In PMOSFETs, the Fermi level, E/sub F/ is low in the device operation, and positively charged donor states cause large V/sub T/ shifts. In NMOSFETs, since E/sub F/ is high in the device operation, the donor states are mostly neutral, and only minor V/sub T/ shift results.

IEEE International Integrated Reliability Workshop Final Report, 2003

Anomalous hot-carrier (HC) degradation is found in some products attributable to the reverse devi... more Anomalous hot-carrier (HC) degradation is found in some products attributable to the reverse device measurement. Disproportionately great reverse degradation is found the core problem. Assuming that the HC degradation is a power function of time, the anomalous degradation is theoretically characterized using the parameters of HC degradation. It is confirmed that the time-dependence slope in the reverse direction and voltage dependence factor are important parameters.

1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)

The acceleration factors of hot carrier (HC) degradation are investigated in detail for scaled PM... more The acceleration factors of hot carrier (HC) degradation are investigated in detail for scaled PMOSFETs. Extrapolated lifetimes under usage conditions are found to be much longer than might be expected from DC stress tests simply interpreted in a traditional manner. The new findings are: (1) the LOG(lifetime) depends on stress-V/sub D/ not by a factor 1/V/sub D/ as in NMOSFETs, but by 1/(|V/sub D/-V/sub 0/), where the constant V/sub 0/ is a weak function of stress-V/sub G/; (2) device parameters have different acceleration factors; /spl Sigma/I/sub ds/, which best represents inverter operation, degrades more slowly than V/sub T/ or I/sub ds/ (at V/sub cc//2) under usage condition; (3) the PMOSFET degradation can be slow for another reason: the release of trapped electrons from oxide back to the silicon (Brox et al, IEEE Trans. vol. ED-41, pp. 1184-1196, 1994).

2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)

The exact least square fit (LSF) technique assuming quadratic dependence on E/sub OX/ and 1/T is ... more The exact least square fit (LSF) technique assuming quadratic dependence on E/sub OX/ and 1/T is applied to analyze the published experimental TDDB data of MOS gate oxides. The E/sub OX/ and 1/T dependence is found more complicated than the simple E model suggests. The linear E/sub OX/ dependence of E/spl alpha/ and the linear 1/T dependence of Gamma is confirmed, and the disagreement with the original papers is discussed. The E model is preferred in the measured E/sub OX/ and 1/T region, but, by extrapolation, the 1/E dependence may have merit at specific regions.

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)

The current constant stress (J-constant) technique is useful for evaluating the resistance rise, ... more The current constant stress (J-constant) technique is useful for evaluating the resistance rise, but can not evaluate "n" values because of metal temperature scattering among samples. Two modified Jc techniques are advised. By controlling the metal temperature at t(stress)=0 within /spl plusmn/1/spl deg/C of the target temperature, the "temperature-controlled" J-constant technique can evaluate n values efficiently. By monitoring the power and adjusting the stress current, the power-constant technique can reduce excess joule-heating and keep the metal temperature constant during stress, and smaller n values are obtained.

1978 International Electron Devices Meeting, 1978

The structure and principle of a new nonvolatile charge storage device are described. The Floatin... more The structure and principle of a new nonvolatile charge storage device are described. The Floating Si-gate Channel Corner Avalanche Transition (FCAT) memory device is an n-channel MOS transistor with a floating gate. The p+regions are placed outside the channel area by aligning them with the floating gate and are adjacent to the diffused n+source and/or drain regions. This device can operate write/erase modes under low voltage (12 V) and high speed (< 1 ms) conditions using only a pair of positive pulses. This is achieved with a novel avalanche transition at the channel corner through a relatively thin oxide under the open drain condition.

1996 International Integrated Reliability Workshop Final Report

A new technique is proposed for Bias-Temperature (BT) stress tests of parasitic MOSFETs: the temp... more A new technique is proposed for Bias-Temperature (BT) stress tests of parasitic MOSFETs: the temperature is kept constant during the BT stress and Vt measurement steps. Application of a positive substrate bias, Vb, makes the threshold voltage, Vt, smaller than the stress bias, so that Vt remains stable during the measurement. The method is applied to evaluate A1-2 NMOSFETs with pTEOS adopted as an intermetallic oxide. Both positive and negative instabilities are found depending on the planarization process.

International Report on Wafer Level Reliability Workshop, 1992

International Integrated Reliability Workshop Final Report

Engineers involved with oxide reliability have different languages, (1) the breakdown voltage (Vb... more Engineers involved with oxide reliability have different languages, (1) the breakdown voltage (Vbd) distribution or the defect density at wafer level, (2) the bum-in failure rate analyzed by assuming Weibull distribution, and the field failure rate. To relate these parameters theoretically, the effective oxide thickness, tox-eff, distribution and the basic acceleration models, the E model and the l/E model, were adopted. A simulator is presented that derives the Vbd distribution and the field failure rate from the Weibull distribution of the burn-in failures. For the better use of the theory, we need to accumulate accurate values of acceleration parameters.

Solid-State Electronics, 2002

Abstract Simple analytical formulas for the extrinsic time-dependent dielectric breakdown lifetim... more Abstract Simple analytical formulas for the extrinsic time-dependent dielectric breakdown lifetime are derived by extending intrinsic models to include the contribution of oxide defects, mathematically taking advantage of the characteristics of Weibull function. The lifetime is given by a simple function of electric field E with only four fitting parameters, two for intrinsic and two for extrinsic failures. Two types of formulas are compared to explain the data with the Weibull slope inversely proportional to E : one is a three-term formula assuming the extrinsic charge to breakdown, Q BD based on the 1/ E theory, and the other is a two-term formula based on the E model using the idea of oxide thinning. It is discussed that the difference between the two formulas is only in the third term, and will be more clearly tested if the probed E range is increased. The E n model is derived modifying the E model to cover experiments where the E or 1/ E model does not simply apply. The experimental data with the Weibull slope not inversely proportional to E is successfully explained using the n value derived from the extrinsic Weibull slope.

Solid-State Electronics, 2001

The quantum mechanical interference method to extract oxide thickness is examined in detail by fu... more The quantum mechanical interference method to extract oxide thickness is examined in detail by fully using the least square fit technique. The current density, J0, that corresponds to oscillatory peaks of n=1,2,3 and 4 is plotted against n, and by doing so, data scattering among the devices is clearly recognized. The extracted physical parameters, ΦM and m2, have large standard deviation around the average depending on device and polarity conditions. Despite the scattering, an apparent success of the quantum interference (QI) analysis is obtained when the averaged parameters, ΦM=2.94 eV and m2/m0=0.54, are used. It is discussed that both ΦM and m2 are equally critical to the accuracy of the QI method, and they luckily deviate in the opposite direction around the average to cancel with each other. An essential limitation of the QI method is that the device characteristics depend on the factor (tOX√ΦM) and we cannot decide ΦM and tOX separately. tOX to extract ΦM and m2 must be evaluated by the help of other technique like ellipsometry or C–V measurements.

Solid-State Electronics, 2006

A compact channel-current model is proposed for the linear, saturation and sub-threshold regions ... more A compact channel-current model is proposed for the linear, saturation and sub-threshold regions of MOSFETs with eight parameters at the maximum. To derive new formulas both physically reasonable and analytically simple, the core part of the known theories and formulas including BSIM is carefully examined, and the comparison with the exact gradual model is made. A simple formula for the linear region is obtained considering the velocity saturation effect, the bias dependent mobility and the series resistance in the source and drain junctions. It is theoretically predicted and experimentally confirmed that the two new parameters in the denominator strongly depend on the channel length. Simple expressions are additionally advised for the saturation and the sub-threshold regions. By applying the model to a set of devices covering a wide range of channel length, the parameters are extracted, and good agreement between theory and measurement is demonstrated.

Solid-State Electronics, 2008

The series resistance at source and drain junctions is evaluated using a surface potential based ... more The series resistance at source and drain junctions is evaluated using a surface potential based current vs. gate bias (I-V G) model. To achieve ultimate accuracy and efficiency, a I 0-V G model is newly advised for spreadsheet analysis. The electric field dependent mobility model in the literature is modified for easier graphical comparison with the conventional V T-based expression. Using NMOSFETs with different gate length, the exponent for the surface phonon scattering is evaluated to be %0.61 for the electric field based expression, and is close to unity in case of the V T-based expression. A smoothly non-linear series resistance vs. gate length relation is successfully confirmed, and the rough agreement with the conventional analysis is discussed to be reasonable.