Hyunwon Moon - Academia.edu (original) (raw)

Papers by Hyunwon Moon

Research paper thumbnail of A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 μm CMOS

IEEE J. Semiconductor Technology and …, 2011

Research paper thumbnail of 1.3 V low close-in phase noise NMOS LC-VCO with parallel PMOS transistors

Electronics Letters, 2008

ABSTRACT A new NMOS cross-coupled LC-VCO with parallel PMOS transistors is proposed. The proposed... more ABSTRACT A new NMOS cross-coupled LC-VCO with parallel PMOS transistors is proposed. The proposed LC-VCO is useful for suppressing flicker noise upconversion and very suitable for low voltage application. It is implemented in 0.18 mum CMOS technology and has superior characteristics to a conventional complementary LC-VCO. Measured phase noise is -93 dBc/Hz at 100 kHz and -116 dBc/Hz at 1 MHz offsets and its core current is only 2 mA for a 1.3 V supply voltage.

Research paper thumbnail of Highly linear and low noise differential bipolar MOSFET down-converter in CMOS process

Electronics Letters, 2009

ABSTRACT A highly linear, low noise differential down-converter employing a new linearisation tec... more ABSTRACT A highly linear, low noise differential down-converter employing a new linearisation technique derived from composite transistors, i.e. nMOSFET and vertical NPN BJT, is proposed and implemented in a 0.18 mum CMOS technology. It draws 1 mA from a 2.5 V supply voltage and has a voltage gain of 13 dB, a double-sideband noise figure of 9.5 dB, an IIP2 of more than 49 dBm, and an IIP3 of 6.5 dBm.

Research paper thumbnail of An Area-Efficient 0.13-μm CMOS Multiband WCDMA/HSDPA Receiver

Microwave Theory and …, 2010

In this paper, a multiband wideband code-division multiple access/high-speed downlink packet acce... more In this paper, a multiband wideband code-division multiple access/high-speed downlink packet access direct-conversion receiver to cover all six Third-Generation Partnership Project bands is implemented in a 0.13-μm CMOS process. To reduce the increase of chip size due to implementation of the multimode multiband RF transceiver integrated circuit, a new integrated inductor structure sharing an inner diameter, a proposed mixed-type dc

Research paper thumbnail of A 27mW 2.2dB NF GPS receiver using a capacitive cross-coupled structure in 65nm CMOS

… (CICC), 2010 IEEE, 2010

A fully integrated low-IF GPS receiver with minimum external components is implemented in a 65nm ... more A fully integrated low-IF GPS receiver with minimum external components is implemented in a 65nm CMOS process. It has an integrated LNA and an active complex bandpass filter with a switchable signal bandwidth of 2MHz or 6 MHz to achieve the SNR improvement. To reduce power consumption, the current reusing method and current mode interface technique using a capacitive cross-coupled common-gate structure are applied. The measured noise figure of whole receiver including an external inter-stage SAW filter is 2.2dB. Its current consumption is 15mA at 1.8V supply.

Research paper thumbnail of Characterization and modeling of stacked MIM on-chip capacitors with high-capacitance density up to 20 GHz frequency region

Microwave and Optical Technology Letters, 2009

In this article, double-stacked and triple-stacked metal-insulator-metal (MIM) capacitors fabrica... more In this article, double-stacked and triple-stacked metal-insulator-metal (MIM) capacitors fabricated in 0.18 μm CMOS process are reported. These provide high-capacitance density of 2 fF/μm2 and 3.2 fF/μm2 and excellent dc and RF characteristics, respectively. The lumped circuit model of the stacked MIM capacitors is presented for high-frequency applications up to 20 GHz. The stacked MIM capacitors offer a reduced chip area for a given capacitance value and are expected to be a viable choice for integration of RF/mixed-mode circuits in a single chip. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1235–1238, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24305

Research paper thumbnail of A Wideband CMOS RF Front-End Using AC-Coupled Current Mirrored Technique for Multiband Multistandard Mobile TV Tuners

Microwave and Wireless …, 2007

ABSTRACT In this paper, a wideband CMOS radio frequency (RF) front-end for various terrestrial mo... more ABSTRACT In this paper, a wideband CMOS radio frequency (RF) front-end for various terrestrial mobile digital TV applications such as digital video broadcasting-handheld, terrestrial digital multimedia broadcasting, and integrated services digital broadcasting-terrestrial is proposed. To cover VHF III, UHF, and L bands and reduce the silicon area simultaneously, it employs three low-noise amplifiers and single-to-differential transconductors and shares the rest of the RF front-end. By applying ac-coupled current mirrored technique, the proposed RF front-end has good wideband performance, high linearity, and precise gain control. It is fabricated in 0.18 mum CMOS process and draws 15 mA~20 mA from a 1.8 V supply voltage for each band. It shows a gain of more than 29 dB, noise figure of lower than 2.5 dB, IIP2 of more than 30 dBm, IIP3 of more than -10 dBm for entire bands.

Research paper thumbnail of Differentially tuned LC-VCO using modified anti-parallel structure

Solid-State and Integrated Circuits Technology …, 2004

This paper presents a new differentially tuned LC-VCO using a modified anti-parallel. The propose... more This paper presents a new differentially tuned LC-VCO using a modified anti-parallel. The proposed LC-VCO has lower phase noise and better robustness to the common-mode noise than the previous differentially tuned LC-VCO using the anti-parallel structure. The proposed LC-VCO is implemented using SiGe BiCMOS process. It is tunable from 4.25 to 4.43 GHz and the measured phase noise is -103 dBc/Hz at 100 kHz offset and -119 dBc/Hz at 1 MHz offset over the entire tuning range. Also, its CMRR characteristic is improved about 2dB. Its core current is 1.7 mA at 2.5V supply voltage.

Research paper thumbnail of A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS

Solid-State Circuits …, 2010

A 2.5 mm2 GPS radio chip with a robust interference rejection performance working in the L1 band ... more A 2.5 mm2 GPS radio chip with a robust interference rejection performance working in the L1 band at 1575.42 MHz is implemented in a 65 nm CMOS process. The receiver with internal LNA shows 2.3 dB NF, 30 dB IRR, and -15 dBm blocker IP1dB at 1710 MHz. Power consumption of 23 mW from a single 1.8 V supply is achieved by using a switched-mode power supply (SMPS).

Research paper thumbnail of A fully differential LC-VCO using a new varactor control structure

Microwave and Wireless …, 2004

ABSTRACT This paper presents a fully differential inductor-capacitor voltage-controlled oscillato... more ABSTRACT This paper presents a fully differential inductor-capacitor voltage-controlled oscillator (LC-VCO) with a new differentially-tuned varactor structure. The proposed LC-VCO has lower phase noise and better robustness to the injected common-mode noise than the differentially-tuned LC-VCO using the previous antiparallel structure. The LC-VCO implemented using 0.5-μm SiGe BiCMOS technology is tunable from 4.251 to 4.428 GHz and the measured phase noise is -119 dBc/Hz at 1-MHz offset over the entire tuning range. Its core current is only 1.7 mA at 2.5-V supply voltage.

Research paper thumbnail of A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 μm CMOS

IEEE J. Semiconductor Technology and …, 2011

Research paper thumbnail of 1.3 V low close-in phase noise NMOS LC-VCO with parallel PMOS transistors

Electronics Letters, 2008

ABSTRACT A new NMOS cross-coupled LC-VCO with parallel PMOS transistors is proposed. The proposed... more ABSTRACT A new NMOS cross-coupled LC-VCO with parallel PMOS transistors is proposed. The proposed LC-VCO is useful for suppressing flicker noise upconversion and very suitable for low voltage application. It is implemented in 0.18 mum CMOS technology and has superior characteristics to a conventional complementary LC-VCO. Measured phase noise is -93 dBc/Hz at 100 kHz and -116 dBc/Hz at 1 MHz offsets and its core current is only 2 mA for a 1.3 V supply voltage.

Research paper thumbnail of Highly linear and low noise differential bipolar MOSFET down-converter in CMOS process

Electronics Letters, 2009

ABSTRACT A highly linear, low noise differential down-converter employing a new linearisation tec... more ABSTRACT A highly linear, low noise differential down-converter employing a new linearisation technique derived from composite transistors, i.e. nMOSFET and vertical NPN BJT, is proposed and implemented in a 0.18 mum CMOS technology. It draws 1 mA from a 2.5 V supply voltage and has a voltage gain of 13 dB, a double-sideband noise figure of 9.5 dB, an IIP2 of more than 49 dBm, and an IIP3 of 6.5 dBm.

Research paper thumbnail of An Area-Efficient 0.13-μm CMOS Multiband WCDMA/HSDPA Receiver

Microwave Theory and …, 2010

In this paper, a multiband wideband code-division multiple access/high-speed downlink packet acce... more In this paper, a multiband wideband code-division multiple access/high-speed downlink packet access direct-conversion receiver to cover all six Third-Generation Partnership Project bands is implemented in a 0.13-μm CMOS process. To reduce the increase of chip size due to implementation of the multimode multiband RF transceiver integrated circuit, a new integrated inductor structure sharing an inner diameter, a proposed mixed-type dc

Research paper thumbnail of A 27mW 2.2dB NF GPS receiver using a capacitive cross-coupled structure in 65nm CMOS

… (CICC), 2010 IEEE, 2010

A fully integrated low-IF GPS receiver with minimum external components is implemented in a 65nm ... more A fully integrated low-IF GPS receiver with minimum external components is implemented in a 65nm CMOS process. It has an integrated LNA and an active complex bandpass filter with a switchable signal bandwidth of 2MHz or 6 MHz to achieve the SNR improvement. To reduce power consumption, the current reusing method and current mode interface technique using a capacitive cross-coupled common-gate structure are applied. The measured noise figure of whole receiver including an external inter-stage SAW filter is 2.2dB. Its current consumption is 15mA at 1.8V supply.

Research paper thumbnail of Characterization and modeling of stacked MIM on-chip capacitors with high-capacitance density up to 20 GHz frequency region

Microwave and Optical Technology Letters, 2009

In this article, double-stacked and triple-stacked metal-insulator-metal (MIM) capacitors fabrica... more In this article, double-stacked and triple-stacked metal-insulator-metal (MIM) capacitors fabricated in 0.18 μm CMOS process are reported. These provide high-capacitance density of 2 fF/μm2 and 3.2 fF/μm2 and excellent dc and RF characteristics, respectively. The lumped circuit model of the stacked MIM capacitors is presented for high-frequency applications up to 20 GHz. The stacked MIM capacitors offer a reduced chip area for a given capacitance value and are expected to be a viable choice for integration of RF/mixed-mode circuits in a single chip. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1235–1238, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24305

Research paper thumbnail of A Wideband CMOS RF Front-End Using AC-Coupled Current Mirrored Technique for Multiband Multistandard Mobile TV Tuners

Microwave and Wireless …, 2007

ABSTRACT In this paper, a wideband CMOS radio frequency (RF) front-end for various terrestrial mo... more ABSTRACT In this paper, a wideband CMOS radio frequency (RF) front-end for various terrestrial mobile digital TV applications such as digital video broadcasting-handheld, terrestrial digital multimedia broadcasting, and integrated services digital broadcasting-terrestrial is proposed. To cover VHF III, UHF, and L bands and reduce the silicon area simultaneously, it employs three low-noise amplifiers and single-to-differential transconductors and shares the rest of the RF front-end. By applying ac-coupled current mirrored technique, the proposed RF front-end has good wideband performance, high linearity, and precise gain control. It is fabricated in 0.18 mum CMOS process and draws 15 mA~20 mA from a 1.8 V supply voltage for each band. It shows a gain of more than 29 dB, noise figure of lower than 2.5 dB, IIP2 of more than 30 dBm, IIP3 of more than -10 dBm for entire bands.

Research paper thumbnail of Differentially tuned LC-VCO using modified anti-parallel structure

Solid-State and Integrated Circuits Technology …, 2004

This paper presents a new differentially tuned LC-VCO using a modified anti-parallel. The propose... more This paper presents a new differentially tuned LC-VCO using a modified anti-parallel. The proposed LC-VCO has lower phase noise and better robustness to the common-mode noise than the previous differentially tuned LC-VCO using the anti-parallel structure. The proposed LC-VCO is implemented using SiGe BiCMOS process. It is tunable from 4.25 to 4.43 GHz and the measured phase noise is -103 dBc/Hz at 100 kHz offset and -119 dBc/Hz at 1 MHz offset over the entire tuning range. Also, its CMRR characteristic is improved about 2dB. Its core current is 1.7 mA at 2.5V supply voltage.

Research paper thumbnail of A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS

Solid-State Circuits …, 2010

A 2.5 mm2 GPS radio chip with a robust interference rejection performance working in the L1 band ... more A 2.5 mm2 GPS radio chip with a robust interference rejection performance working in the L1 band at 1575.42 MHz is implemented in a 65 nm CMOS process. The receiver with internal LNA shows 2.3 dB NF, 30 dB IRR, and -15 dBm blocker IP1dB at 1710 MHz. Power consumption of 23 mW from a single 1.8 V supply is achieved by using a switched-mode power supply (SMPS).

Research paper thumbnail of A fully differential LC-VCO using a new varactor control structure

Microwave and Wireless …, 2004

ABSTRACT This paper presents a fully differential inductor-capacitor voltage-controlled oscillato... more ABSTRACT This paper presents a fully differential inductor-capacitor voltage-controlled oscillator (LC-VCO) with a new differentially-tuned varactor structure. The proposed LC-VCO has lower phase noise and better robustness to the injected common-mode noise than the differentially-tuned LC-VCO using the previous antiparallel structure. The LC-VCO implemented using 0.5-μm SiGe BiCMOS technology is tunable from 4.251 to 4.428 GHz and the measured phase noise is -119 dBc/Hz at 1-MHz offset over the entire tuning range. Its core current is only 1.7 mA at 2.5-V supply voltage.