Iris Jiang - Academia.edu (original) (raw)

Papers by Iris Jiang

2019 IEEE 13th International Conference on ASIC (ASICON)

Multiple patterning lithography has been widely adopted in advanced technology nodes of VLSI manu... more Multiple patterning lithography has been widely adopted in advanced technology nodes of VLSI manufacturing. As a key step in the design flow, multiple patterning layout decomposition (MPLD) is critical to design closure. Due to the NP-hardness of the general decomposition problem, various efficient algorithms have been proposed with high quality solutions. However, with increasingly complicated design flow and peripheral processing steps, developing a high-quality layout decomposer becomes more and more difficult, slowing down the further advancement in this field. This paper presents OpenMPL [1], an open-source layout decomposition framework, with well-separated peripheral processing and the core solving steps. We demonstrate the flexibility of the framework with efficient implementations of various state-of-the-art algorithms, which enable us to reproduce most of the recent results on widely-recognized benchmarks. We believe OpenMPL can pave the road for developing layout decomposition engines and stimulate further researches on this problem.

Proceedings of the 2023 International Symposium on Physical Design

This panel explores domain-specific computing from hardware, software, and electronic design auto... more This panel explores domain-specific computing from hardware, software, and electronic design automation (EDA) perspectives. Hennessey and Patterson signaled a new "golden age of computer architecture" in 2018 [1]. Process technology advances and general-purpose processor improvements provided much faster and more efficient computation, but scaling with Moore's law has slowed significantly. Domain-specific customization can improve power-performance efficiency by orders-of-magnitude for important application domains, such as graphics, deep neural networks (DNN) for machine learning [2], simulation, bioinformatics [3], image processing, and many other tasks.

ACM Transactions on Design Automation of Electronic Systems, 2006

As technology advances apace, crosstalk becomes a design metric of comparable importance to area ... more As technology advances apace, crosstalk becomes a design metric of comparable importance to area and delay. This article focuses mainly on the crosstalk issue, specifically on the impacts of physical design and process variation on crosstalk. While the feature size shrinks below 0.25μ m , the impact of process variation on crosstalk increases rapidly. Hence, a crosstalk insensitive design is desirable in the deep submicron regime. In this article, crosstalk sensitivity is referred to as the influence of process variation on crosstalk in a circuit. We show that the lower bound of crosstalk sensitivity grows quadratically, while that of crosstalk increases linearly. Therefore, designers should also consider crosstalk sensitivity, when optimizing other design objectives such as crosstalk, area, and delay. According to our modeling, these objectives are all in posynomial forms, and thus the multi-objective optimization problem can optimally be solved by Lagrangian relaxation. Experiment...

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021

2008 IEEE International Conference on Computer Design, 2008

The rectilinear Steiner minimal tree (RSMT) problem is essential in physical design. Moreover, th... more The rectilinear Steiner minimal tree (RSMT) problem is essential in physical design. Moreover, the variant constraints for fabrication issues, including obstacle avoidance, multiple routing layers, layer-specific routing directions, cannot be ignored during RSMT construction for modern SoC and nano technologies. This paper proposes a construction-by-correction approach for obstacle-avoiding preferred direction rectilinear Steiner tree construction. Experimental results show that our algorithm is promising and outperforms the state-of-the-art works.

In this paper, we present DATC Robust Design Flow (RDF) from logic synthesis to detailed routing.... more In this paper, we present DATC Robust Design Flow (RDF) from logic synthesis to detailed routing. Our goals are 1) to provide an open-source academic design flow from logic synthesis to detailed routing based on existing contest results, 2) to construct a database for design benchmarks and point tool libraries, and 3) to interact with industrial designs by using industrial standard design input/output formats. We also demonstrate RDF in a scalable cloud infrastructure. Design methodology and cross-stage optimization research can be conducted via RDF.

ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Embedded Computing Systems

Proceedings of the 35th International Conference on Computer-Aided Design - ICCAD '16, 2016

1999 Ieee Acm International Conference on Computer Aided Design Digest of Technical Papers, 1999

Improving logic density by time-sharing, time-multiplexed FPGAs (TMFPGAs) have become an importan... more Improving logic density by time-sharing, time-multiplexed FPGAs (TMFPGAs) have become an important research topic for reconfigurable computing. Due to the precedence and capacity constraints in TMFPGAs, the clustering and partitioning problems for TMFPGAs are different from the traditional ones. In this paper, we propose a two-phase hierarchical approach to solve the partitioning problem for TMFPGAs. With the precedence and capacity considerations for both phases, the first phase clusters nodes to reduce the problem size, and the second phase applies a probability-based iterative-improvement approach to minimize cut cost. Experimental results based on the Xilinx TMFPGA architecture show that our algorithm significantly outperforms previous works.

2008 Ieee International Conference on Computer Design, Oct 1, 2008

Interconnect delay and low power are two of the main issues in nano technology. Buffer insertion ... more Interconnect delay and low power are two of the main issues in nano technology. Buffer insertion during routing effectively reduces interconnect delay; power state management and multiple supply voltage significantly lower power consumption. However, buffering without considering power states in multiple supply voltage designs may cause the signal integrity problem. This paper first considers power states into buffered tree construction. Based on a hierarchical approach combined with dynamic programming, we can simultaneously minimize power, satisfy timing constraints and maintain signal integrity.

Proceedings of 2010 Ieee International Symposium on Circuits and Systems, 2010

To ease the time-to-market pressure and save the photomask cost, metal-only ECO realizes the last... more To ease the time-to-market pressure and save the photomask cost, metal-only ECO realizes the last-minute design changes by revising the photomasks of metal layers only. This task is challenging because the pre-injected spare cells are limited in number and in cell types. We develop a metal-only ECO synthesizer, named ECOS, that automates the incremental design changes without sacrificing timing and

Proceedings of the 19th Acm Great Lakes Symposium, 2009

This paper proposes a new architecture of variability-tolerant chip-multiprocessor. To mitigate t... more This paper proposes a new architecture of variability-tolerant chip-multiprocessor. To mitigate the impact of process variability on throughput and power, voltage and frequency islands are introduced into chip-multiprocessors. Thus, voltage island frequency island chip-multiprocessors enable per-core scaling on the supply voltage and operating frequency. It can naturally collaborate with dynamic voltage frequency scaling. The process variations are characterized through an analytical model, and are quantified through Monte Carlo analysis. Compared with the design without process variations, when 70 threads are run on a chip of 70 small cores, our results show throughput degradation is 0.06%, while power reduction is 36.27%.

Acm Transactions on Design Automation of Electronic Systems, Nov 18, 2014

Abstract As technology advances apace, crosstalk becomes a design met-ric of comparable importanc... more Abstract As technology advances apace, crosstalk becomes a design met-ric of comparable importance to area and timing. This paper fo-cuses mainly on the crosstalk issue, spec$cally on the impacts of physical design and process variation on crosstalk. While the feature ...

Proceedings of the 2014 Ieee Acm International Conference, Nov 3, 2014

Proceedings of the International Conference on Computer Aided Design, Nov 5, 2012

2014 Ieee Acm International Conference on Computer Aided Design, Nov 3, 2014