Ivan Sutherland - Academia.edu (original) (raw)

Papers by Ivan Sutherland

2015 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Lecture Notes in Computer Science, 2010

Abstract. This paper reports spreadsheet calculations intended to verify the timing of 6-4 GasP a... more Abstract. This paper reports spreadsheet calculations intended to verify the timing of 6-4 GasP asynchronous Network on Chip (NoC) control circuits. The Logical Effort model used in the spreadsheet estimates the delays of each logic gate in the GasP control. The calculations show how ...

CHI '05 extended abstracts on Human factors in computing systems - CHI '05, 2005

The activity centered around the TX-2 computer at Lincoln Laboratory in the 1960's laid the found... more The activity centered around the TX-2 computer at Lincoln Laboratory in the 1960's laid the foundation for much of HCI. Through the use of archival film footage, and live presentations by some of the key protagonists, this panel is intended to contribute to a more general awareness of this work, its historical importance to HCI, and its relevance to research today.

IEEE Transactions on Computers, 2000

Communications of the ACM, 1974

A new family of clipping algorithms is described. These algorithms are able to clip polygons agai... more A new family of clipping algorithms is described. These algorithms are able to clip polygons against irregular convex plane-faced volumes in three dimensions, removing the parts of the polygon which lie outside the volume. In two dimensions the algorithms permit clipping against irregular convex windows.Polygons to be clipped are represented as an ordered sequence of vertices without repetition of first

... Basic Limitations in Microcircuit Fabrication Technology Ivan E. Sutherland, Carver A. Mead, ... more ... Basic Limitations in Microcircuit Fabrication Technology Ivan E. Sutherland, Carver A. Mead, and Thomas E. Everhart - REIDUtCED • ? ... Basic Limitations in Microcircuit Fabrication TechnologyIvan E. Sutherland, Carver A. Mead, and Thomas E. Everhart A Report prepared foi ...

13th Symposium on High Performance Interconnects (HOTI'05), 2005

Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwi... more Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwidth when compared to their flop/s of instruction execution rate. The resulting bottleneck limits the bytes/flop that a processor may access from the full memory footprint of a machine and can hinder overall performance. This paper discusses physical and functional views of memory hierarchies and examines existing ratios of bandwidth to execution rate versus memory capacity (or bytes/flop versus capacity ) found in a number of large-scale computers. The paper then explores a set of technologies, Proximity Communication, low-power on-chip networks, dense optical communication, and Sea-of-Anything interconnect, that can flatten this bandwidth hierarchy to relieve the memory bottleneck in a large-scale computer that we call "Hero."

ACM SIGGRAPH Computer Graphics, 1989

With widespread use of raster scan displays and the ever-increasing desire for faster interactivi... more With widespread use of raster scan displays and the ever-increasing desire for faster interactivity, higher image com-plexity, and higher resolution in displayed images, several techniques have been proposed for rasterizing primitive graphical objects. This paper characterizes ...

Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001, 2001

A five-step design process for asynchronous circuits helps simplify their logic and speed their o... more A five-step design process for asynchronous circuits helps simplify their logic and speed their operation. First, assume that all logic gates in the control will have nearly uniform delay. Second, use the uniform delay assumption to simplify control logic. Third, lay out the chip to get wire length data. Fourth, choose a specific delay and calculate transistor widths to apply

Scientific American, 2002

Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1998

A core problem in many pipelined circuit designs is data-dependent data flow. We describe a metho... more A core problem in many pipelined circuit designs is data-dependent data flow. We describe a methodology and a set of circuit modules to address this problem in the asynchronous domain. We call our methodology P**3, or "P cubed." Items flowing through a set of FIFO datapaths can be conditionally steered under the control of data carried by other FIFOs. We have used the P**3 methodology to design and implement a FIFO test chip that uses a data-dependent switch to delete marked data items conditionally. The circuit uses two on-chip FIFO rings as high-speed data sources. It was fabricated through MOSIS using their 0.6µ CMOS design rules. The peak data switch throughput was measured to be a minimum of 580 million data items per second at nominal Vdd of 3.3V.

Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999

... Bill Coates, Jo Ebergen, Jon Lexau, Scott Fairbanks, Ian Jones, Alex Ridgway, David Harris, I... more ... Bill Coates, Jo Ebergen, Jon Lexau, Scott Fairbanks, Ian Jones, Alex Ridgway, David Harris, Ivan Sutherland Sun Microsystems Laboratories, Palo Alto, USA Abstract ... “...their construction being as it were a wheel within a wheel.” Ezekiel, Chapter 1, verse 16. 1. Introduction ...

Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001, 2001

Page 1. FLEETzero: An Asynchronous Switching Experiment William S. Coates, Jon K. Lexau, Ian W. J... more Page 1. FLEETzero: An Asynchronous Switching Experiment William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, and Ivan E. Sutherland Sun Microsystems Laboratories, 901 San Antonio Road, Palo Alto, CA 94303-4900 Abstract ...

Solid-State Circuits IEEE International Conference, 2004

This work presents an electronic alignment mechanism for capacitively-coupled proximity communica... more This work presents an electronic alignment mechanism for capacitively-coupled proximity communication. On an experimental chip, position offsets of up to +/-100μm are electrically corrected to within 6.25μm. A 0.35μm experimental CMOS chip communicates at 1.35Gb/s with a BER ≤10-10.

ACM SIGGRAPH Computer Graphics, 1981

Interactive use of a display requires the capability to update the display rapidly. This paper de... more Interactive use of a display requires the capability to update the display rapidly. This paper describes an on.going project at Carnegie-Mellon University in which we are designing a frame buffer raster-scan display system which has the high performance typically required for ...

ACM Transactions on Graphics, 1983

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007

Proceedings of the IEEE, 1999

Asynchronous circuits are often perceived to operate slower than equivalent clocked circuits. We ... more Asynchronous circuits are often perceived to operate slower than equivalent clocked circuits. We demonstrate with fabricated chips that asynchronous circuits can be every bit as fast as clocked circuits. We describe two high-speed first-in-first-out (FIFO) circuits that we used to compare the performance of asynchronous FIFO's with that of conventionally clocked shift registers. The first FIFO circuit uses a pulse-like protocol, which we call the Asynchronous Symmetric Persistent Pulse Protocol (asP*), to advance data along a pipeline of conventional latches. Use of this protocol requires careful management of circuit delays. The second FIFO circuit uses a transition signaling protocol and special transition latches to store data. These transition latches are fast, but they are about 50% larger than conventional latches. Measurements obtained from chips fabricated in 0.6-m CMOS and from SPICE simulations show that the throughput of the first FIFO design matches that of a conventionally clocked shift register design, with a maximum throughput of 1.1 Giga data items per second. The throughput of the second design exceeds the performance of the asP* design and achieves a maximum throughput of 1.7 Giga data items per second. We have extensively tested the chips and have found them to operate reliably over a very wide range of conditions.

2015 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Lecture Notes in Computer Science, 2010

Abstract. This paper reports spreadsheet calculations intended to verify the timing of 6-4 GasP a... more Abstract. This paper reports spreadsheet calculations intended to verify the timing of 6-4 GasP asynchronous Network on Chip (NoC) control circuits. The Logical Effort model used in the spreadsheet estimates the delays of each logic gate in the GasP control. The calculations show how ...

CHI '05 extended abstracts on Human factors in computing systems - CHI '05, 2005

The activity centered around the TX-2 computer at Lincoln Laboratory in the 1960's laid the found... more The activity centered around the TX-2 computer at Lincoln Laboratory in the 1960's laid the foundation for much of HCI. Through the use of archival film footage, and live presentations by some of the key protagonists, this panel is intended to contribute to a more general awareness of this work, its historical importance to HCI, and its relevance to research today.

IEEE Transactions on Computers, 2000

Communications of the ACM, 1974

A new family of clipping algorithms is described. These algorithms are able to clip polygons agai... more A new family of clipping algorithms is described. These algorithms are able to clip polygons against irregular convex plane-faced volumes in three dimensions, removing the parts of the polygon which lie outside the volume. In two dimensions the algorithms permit clipping against irregular convex windows.Polygons to be clipped are represented as an ordered sequence of vertices without repetition of first

... Basic Limitations in Microcircuit Fabrication Technology Ivan E. Sutherland, Carver A. Mead, ... more ... Basic Limitations in Microcircuit Fabrication Technology Ivan E. Sutherland, Carver A. Mead, and Thomas E. Everhart - REIDUtCED • ? ... Basic Limitations in Microcircuit Fabrication TechnologyIvan E. Sutherland, Carver A. Mead, and Thomas E. Everhart A Report prepared foi ...

13th Symposium on High Performance Interconnects (HOTI'05), 2005

Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwi... more Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwidth when compared to their flop/s of instruction execution rate. The resulting bottleneck limits the bytes/flop that a processor may access from the full memory footprint of a machine and can hinder overall performance. This paper discusses physical and functional views of memory hierarchies and examines existing ratios of bandwidth to execution rate versus memory capacity (or bytes/flop versus capacity ) found in a number of large-scale computers. The paper then explores a set of technologies, Proximity Communication, low-power on-chip networks, dense optical communication, and Sea-of-Anything interconnect, that can flatten this bandwidth hierarchy to relieve the memory bottleneck in a large-scale computer that we call "Hero."

ACM SIGGRAPH Computer Graphics, 1989

With widespread use of raster scan displays and the ever-increasing desire for faster interactivi... more With widespread use of raster scan displays and the ever-increasing desire for faster interactivity, higher image com-plexity, and higher resolution in displayed images, several techniques have been proposed for rasterizing primitive graphical objects. This paper characterizes ...

Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001, 2001

A five-step design process for asynchronous circuits helps simplify their logic and speed their o... more A five-step design process for asynchronous circuits helps simplify their logic and speed their operation. First, assume that all logic gates in the control will have nearly uniform delay. Second, use the uniform delay assumption to simplify control logic. Third, lay out the chip to get wire length data. Fourth, choose a specific delay and calculate transistor widths to apply

Scientific American, 2002

Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1998

A core problem in many pipelined circuit designs is data-dependent data flow. We describe a metho... more A core problem in many pipelined circuit designs is data-dependent data flow. We describe a methodology and a set of circuit modules to address this problem in the asynchronous domain. We call our methodology P**3, or "P cubed." Items flowing through a set of FIFO datapaths can be conditionally steered under the control of data carried by other FIFOs. We have used the P**3 methodology to design and implement a FIFO test chip that uses a data-dependent switch to delete marked data items conditionally. The circuit uses two on-chip FIFO rings as high-speed data sources. It was fabricated through MOSIS using their 0.6µ CMOS design rules. The peak data switch throughput was measured to be a minimum of 580 million data items per second at nominal Vdd of 3.3V.

Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999

... Bill Coates, Jo Ebergen, Jon Lexau, Scott Fairbanks, Ian Jones, Alex Ridgway, David Harris, I... more ... Bill Coates, Jo Ebergen, Jon Lexau, Scott Fairbanks, Ian Jones, Alex Ridgway, David Harris, Ivan Sutherland Sun Microsystems Laboratories, Palo Alto, USA Abstract ... “...their construction being as it were a wheel within a wheel.” Ezekiel, Chapter 1, verse 16. 1. Introduction ...

Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001, 2001

Page 1. FLEETzero: An Asynchronous Switching Experiment William S. Coates, Jon K. Lexau, Ian W. J... more Page 1. FLEETzero: An Asynchronous Switching Experiment William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, and Ivan E. Sutherland Sun Microsystems Laboratories, 901 San Antonio Road, Palo Alto, CA 94303-4900 Abstract ...

Solid-State Circuits IEEE International Conference, 2004

This work presents an electronic alignment mechanism for capacitively-coupled proximity communica... more This work presents an electronic alignment mechanism for capacitively-coupled proximity communication. On an experimental chip, position offsets of up to +/-100μm are electrically corrected to within 6.25μm. A 0.35μm experimental CMOS chip communicates at 1.35Gb/s with a BER ≤10-10.

ACM SIGGRAPH Computer Graphics, 1981

Interactive use of a display requires the capability to update the display rapidly. This paper de... more Interactive use of a display requires the capability to update the display rapidly. This paper describes an on.going project at Carnegie-Mellon University in which we are designing a frame buffer raster-scan display system which has the high performance typically required for ...

ACM Transactions on Graphics, 1983

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007

Proceedings of the IEEE, 1999

Asynchronous circuits are often perceived to operate slower than equivalent clocked circuits. We ... more Asynchronous circuits are often perceived to operate slower than equivalent clocked circuits. We demonstrate with fabricated chips that asynchronous circuits can be every bit as fast as clocked circuits. We describe two high-speed first-in-first-out (FIFO) circuits that we used to compare the performance of asynchronous FIFO's with that of conventionally clocked shift registers. The first FIFO circuit uses a pulse-like protocol, which we call the Asynchronous Symmetric Persistent Pulse Protocol (asP*), to advance data along a pipeline of conventional latches. Use of this protocol requires careful management of circuit delays. The second FIFO circuit uses a transition signaling protocol and special transition latches to store data. These transition latches are fast, but they are about 50% larger than conventional latches. Measurements obtained from chips fabricated in 0.6-m CMOS and from SPICE simulations show that the throughput of the first FIFO design matches that of a conventionally clocked shift register design, with a maximum throughput of 1.1 Giga data items per second. The throughput of the second design exceeds the performance of the asP* design and achieves a maximum throughput of 1.7 Giga data items per second. We have extensively tested the chips and have found them to operate reliably over a very wide range of conditions.