J. Yantchev - Academia.edu (original) (raw)
Papers by J. Yantchev
This paper presents the ARC tool --- a formal verification tool for CSP currently under developme... more This paper presents the ARC tool --- a formal verification tool for CSP currently under development. The internal workings of the tool are described using a practically oriented approach. The semantics of a CSP process are translated into a corresponding LTS represented by OBDDs, and the latter is then checked by exhaustive state-space search. This approach and some other implementation enhancements allow checking of processes with up to 10 40 states. We also present a number of examples and compare the performance of ARC with that of other verification tools. 1 Introduction Formal methods play an increasingly important role in system design and engineering, especially in the area of safety-critical systems, such as control and monitoring equipment, communications, etc. Their role is no longer confined to being a uniform, rigorous design language; they are now used for verifying the desired properties of the system under development. However powerful a formal method may be, handlin...
Topics in Atmospheric and Oceanic Sciences, 1990
We now face an era in which large scale parallelism in computer equipment will become increasingl... more We now face an era in which large scale parallelism in computer equipment will become increasingly common. This paper addresses that issue; it notes the drive that arises from VLSI technology and sets out the requirements for systems support. Some of the factors that are be considered include the support for heterogeneous systems, or systems that comprise many processor types, including vector or SIMD components; the provision of multiple programming paradigms; and the use of object orientated methodologies.
Lecture Notes in Computer Science, 1989
In this paper we have defined a virtual systems architecture (VSA), which combines both data para... more In this paper we have defined a virtual systems architecture (VSA), which combines both data parallel and process parallel models of computation. Data manipulations strategies for the efficient implementation of the VSA have been considered for various data types and algorithms, which show that a packet based virtual array implementation is required. We introduce a packet routing scheme the mad postman that is shown to have considerably better latency properties than previously published results and considered synchronous cellula automata to implement this scheme. In general, the mad postman is most advantageous to use in lower dimension networks, for example 2-D meshes, where latency is usually higher due to higher network diameter. In such networks the efficiency of the mad postman routing will be higher due to the smaller number of dead address digits generated per each packet. Such networks match form to function, and in current implementation technologies (i.e VLSI chips and PCBs), they will therefore provide cheaper hardware, thus allowing for a higher cost/performance ratio to be achieved.
The 16th Annual International Symposium on Computer Architecture
In order to provide an arbitrary and fully dynamic connectivity in a network of processors, trans... more In order to provide an arbitrary and fully dynamic connectivity in a network of processors, transport mechanisms must be implemented, which provide the propagation of data from processor to processor, based on addresses contained within a packet of data. Such data transport mechanisms must satisfy a number of requirements-deadlock and livelock freedom, good hot-spot performance, high throughput and low latency. This paper proposes a solution to these problems, which allows deadlock free, adaptive, high throughput packet routing to be implemented on networks of processors. Examples are given which illustrate the technique for 2-D array and toroidal networks. An implementation of this scheme on arrays of transputers is described. The scheme also serves as a basis for a very low latency routing strategy named the mud postman. a detailed implementation of which is described here as well.
IEE Proceedings E Computers and Digital Techniques, 1989
In order to provide an arbitrary and fully dynamic connectivity in a network of processors, trans... more In order to provide an arbitrary and fully dynamic connectivity in a network of processors, transport mechanisms must be implemented, which provide the propagation of data from processor to processor, based on addresses contained within a packet of data. Such data transport mechanisms must satisfy a number of requirements, namely deadlock and livelock freedom, good hot-spot performance, high throughput and low latency. The paper proposes a solution to these problems, which allows deadlock free, adaptive, high throughput packet routing to be implemented on networks of processors. Examples are given which illustrate the technique for two-dimensional (2D) array and toroidal networks. The implementation of this scheme on arrays of transputers is considered. The scheme also serves as a basis for very-low latency routing strategy introduced. >
Lecture Notes in Computer Science, 1991
Proceedings of the Fifth Distributed Memory Computing Conference, 1990., 1990
The very low latency of the mad postman message routing strategy, coupled with a programmable or ... more The very low latency of the mad postman message routing strategy, coupled with a programmable or data driven routing node allows an efficient implementation of synchronisation, point-to-point and broadcast communications within the same routing network. These communication mechanisms are essential for most massively concurrent applications and direct support for them will significantly reduce the overheads of intertask communication and synchronisation. The aim is to make the communication resources in distributed memory computers as flexible and extensible as processing/memory presently is.
The Sixth Distributed Memory Computing Conference, 1991. Proceedings, 1991
Lecture Notes in Computer Science, 1997
This paper presents a novel reachability analysis technique which, while still maintaining a set ... more This paper presents a novel reachability analysis technique which, while still maintaining a set of reached states, significantly reduces the size of this set through excluding a specific subset of those states, referred to as pseudo-root states. Pseudo-root states are states which are not reachable from the unexplored state space of the finite model. Such states may be safely discarded from state storage. The modified reachability analysis algorithm identifies and discards pseudo-root states at each iteration of the state search. For a set of three example problems, the presented algorithm results in 2 to 16 fold improvements in space requirements, while increasing the run time at most twice.
Proceedings of 1996 IEEE Second International Conference on Algorithms and Architectures for Parallel Processing, ICA/sup 3/PP '96, 1996
This paper presents the design and implementation of ARC | a tool for automated veri cation of co... more This paper presents the design and implementation of ARC | a tool for automated veri cation of concurrent systems. The tool is based on the untimed CSP language, its semantic models and theory of re nement. We alleviate the combinatorial explosion problem using Ordered Binary Decision Diagrams (OBDDs) for the internal representation of complex data structures | sets and labeled transition systems (LTS). The semantically complex external choice operator is translated into the corresponding LTS using an optimized algorithm. This and some other implementation improvements allow verifying systems with up to 10 33 states, which is consistent with the capabilities of other OBDD-based approaches. Compared to two existing CSP tools, FDR and MRC, ARC has fewer language restrictions and is more memory e cient. A performance comparison based on the nschedulers and dining philosophers problems suggests that the checking algorithm of ARC is, in most cases, faster than those of the other tools. Keywords| Concurrent systems, veri cation, process algebras, CSP, OBDD
Proceedings of 19th Conference on Local Computer Networks, 1994
The asynchronous transfer mode ATM is expected to be the multiplexing and switching technique for... more The asynchronous transfer mode ATM is expected to be the multiplexing and switching technique for future broadband integrated service digital networks BISDNs which can transport almost all types of tra c including bursty data tra c and continuous voice video frames. However, this capability cannot be realized without a proper congestion-control scheme. This paper discusses the suitability of the real-time channel approach 1 for congestion control in ATM networks. A new message-transmission scheme is proposed which is suitable for ATM networks and has a numb e r o f a d v antages over existing schemes. The achievable quality o f service with this scheme would make A TM networks capable of supporting real-time services which h a ve been promised but not yet successfully realized.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
An asynchronous arbiter dynamically allocates a resource in response to requests from processes. ... more An asynchronous arbiter dynamically allocates a resource in response to requests from processes. Glitch-free operation when two requests arrive concurrently is possible in MOS technologies. Multiway arbitration using a request-grant-release-acknowledge protocol can be achieved by connecting together two-way arbiters (mutual exclusion and tree arbiter elements). We have devised a fast and compact design for the tree arbiter element which offers
the Second Australasian Parallel and Real-Time …, 1995
To provide predictable delays, the path(s) used by real-time packets must be known a priori. In p... more To provide predictable delays, the path(s) used by real-time packets must be known a priori. In point-to-point networks, a connection-oriented protocol such as virtual channels is used to meet this requirement 4] 12]. Faults in such networks due to node or link failures can lead ...
Current algorithms for schedulability analyses of the worst case delay and worst case buffer requ... more Current algorithms for schedulability analyses of the worst case delay and worst case buffer requirements for real-time network traffic have made one of two assumptions. 1) The networks are rate controlled (ie the source traffic pattern is reconstructed at each node) or 2) Traffic from multiple ...
Australian Computer Science Communications, 1995
Providing guaranteed timely delivery of real-time messages in point-to-point networks requires th... more Providing guaranteed timely delivery of real-time messages in point-to-point networks requires the reservation of network resources such as bu er space and bandwidth based on worst case tra c char-acteristics (eg maximum source rate, maximum transmission delay). For ...
The 16th Annual International Symposium on Computer Architecture, 1989
IEE Proceedings E Computers and Digital Techniques, 1989
This paper presents the ARC tool --- a formal verification tool for CSP currently under developme... more This paper presents the ARC tool --- a formal verification tool for CSP currently under development. The internal workings of the tool are described using a practically oriented approach. The semantics of a CSP process are translated into a corresponding LTS represented by OBDDs, and the latter is then checked by exhaustive state-space search. This approach and some other implementation enhancements allow checking of processes with up to 10 40 states. We also present a number of examples and compare the performance of ARC with that of other verification tools. 1 Introduction Formal methods play an increasingly important role in system design and engineering, especially in the area of safety-critical systems, such as control and monitoring equipment, communications, etc. Their role is no longer confined to being a uniform, rigorous design language; they are now used for verifying the desired properties of the system under development. However powerful a formal method may be, handlin...
Topics in Atmospheric and Oceanic Sciences, 1990
We now face an era in which large scale parallelism in computer equipment will become increasingl... more We now face an era in which large scale parallelism in computer equipment will become increasingly common. This paper addresses that issue; it notes the drive that arises from VLSI technology and sets out the requirements for systems support. Some of the factors that are be considered include the support for heterogeneous systems, or systems that comprise many processor types, including vector or SIMD components; the provision of multiple programming paradigms; and the use of object orientated methodologies.
Lecture Notes in Computer Science, 1989
In this paper we have defined a virtual systems architecture (VSA), which combines both data para... more In this paper we have defined a virtual systems architecture (VSA), which combines both data parallel and process parallel models of computation. Data manipulations strategies for the efficient implementation of the VSA have been considered for various data types and algorithms, which show that a packet based virtual array implementation is required. We introduce a packet routing scheme the mad postman that is shown to have considerably better latency properties than previously published results and considered synchronous cellula automata to implement this scheme. In general, the mad postman is most advantageous to use in lower dimension networks, for example 2-D meshes, where latency is usually higher due to higher network diameter. In such networks the efficiency of the mad postman routing will be higher due to the smaller number of dead address digits generated per each packet. Such networks match form to function, and in current implementation technologies (i.e VLSI chips and PCBs), they will therefore provide cheaper hardware, thus allowing for a higher cost/performance ratio to be achieved.
The 16th Annual International Symposium on Computer Architecture
In order to provide an arbitrary and fully dynamic connectivity in a network of processors, trans... more In order to provide an arbitrary and fully dynamic connectivity in a network of processors, transport mechanisms must be implemented, which provide the propagation of data from processor to processor, based on addresses contained within a packet of data. Such data transport mechanisms must satisfy a number of requirements-deadlock and livelock freedom, good hot-spot performance, high throughput and low latency. This paper proposes a solution to these problems, which allows deadlock free, adaptive, high throughput packet routing to be implemented on networks of processors. Examples are given which illustrate the technique for 2-D array and toroidal networks. An implementation of this scheme on arrays of transputers is described. The scheme also serves as a basis for a very low latency routing strategy named the mud postman. a detailed implementation of which is described here as well.
IEE Proceedings E Computers and Digital Techniques, 1989
In order to provide an arbitrary and fully dynamic connectivity in a network of processors, trans... more In order to provide an arbitrary and fully dynamic connectivity in a network of processors, transport mechanisms must be implemented, which provide the propagation of data from processor to processor, based on addresses contained within a packet of data. Such data transport mechanisms must satisfy a number of requirements, namely deadlock and livelock freedom, good hot-spot performance, high throughput and low latency. The paper proposes a solution to these problems, which allows deadlock free, adaptive, high throughput packet routing to be implemented on networks of processors. Examples are given which illustrate the technique for two-dimensional (2D) array and toroidal networks. The implementation of this scheme on arrays of transputers is considered. The scheme also serves as a basis for very-low latency routing strategy introduced. >
Lecture Notes in Computer Science, 1991
Proceedings of the Fifth Distributed Memory Computing Conference, 1990., 1990
The very low latency of the mad postman message routing strategy, coupled with a programmable or ... more The very low latency of the mad postman message routing strategy, coupled with a programmable or data driven routing node allows an efficient implementation of synchronisation, point-to-point and broadcast communications within the same routing network. These communication mechanisms are essential for most massively concurrent applications and direct support for them will significantly reduce the overheads of intertask communication and synchronisation. The aim is to make the communication resources in distributed memory computers as flexible and extensible as processing/memory presently is.
The Sixth Distributed Memory Computing Conference, 1991. Proceedings, 1991
Lecture Notes in Computer Science, 1997
This paper presents a novel reachability analysis technique which, while still maintaining a set ... more This paper presents a novel reachability analysis technique which, while still maintaining a set of reached states, significantly reduces the size of this set through excluding a specific subset of those states, referred to as pseudo-root states. Pseudo-root states are states which are not reachable from the unexplored state space of the finite model. Such states may be safely discarded from state storage. The modified reachability analysis algorithm identifies and discards pseudo-root states at each iteration of the state search. For a set of three example problems, the presented algorithm results in 2 to 16 fold improvements in space requirements, while increasing the run time at most twice.
Proceedings of 1996 IEEE Second International Conference on Algorithms and Architectures for Parallel Processing, ICA/sup 3/PP '96, 1996
This paper presents the design and implementation of ARC | a tool for automated veri cation of co... more This paper presents the design and implementation of ARC | a tool for automated veri cation of concurrent systems. The tool is based on the untimed CSP language, its semantic models and theory of re nement. We alleviate the combinatorial explosion problem using Ordered Binary Decision Diagrams (OBDDs) for the internal representation of complex data structures | sets and labeled transition systems (LTS). The semantically complex external choice operator is translated into the corresponding LTS using an optimized algorithm. This and some other implementation improvements allow verifying systems with up to 10 33 states, which is consistent with the capabilities of other OBDD-based approaches. Compared to two existing CSP tools, FDR and MRC, ARC has fewer language restrictions and is more memory e cient. A performance comparison based on the nschedulers and dining philosophers problems suggests that the checking algorithm of ARC is, in most cases, faster than those of the other tools. Keywords| Concurrent systems, veri cation, process algebras, CSP, OBDD
Proceedings of 19th Conference on Local Computer Networks, 1994
The asynchronous transfer mode ATM is expected to be the multiplexing and switching technique for... more The asynchronous transfer mode ATM is expected to be the multiplexing and switching technique for future broadband integrated service digital networks BISDNs which can transport almost all types of tra c including bursty data tra c and continuous voice video frames. However, this capability cannot be realized without a proper congestion-control scheme. This paper discusses the suitability of the real-time channel approach 1 for congestion control in ATM networks. A new message-transmission scheme is proposed which is suitable for ATM networks and has a numb e r o f a d v antages over existing schemes. The achievable quality o f service with this scheme would make A TM networks capable of supporting real-time services which h a ve been promised but not yet successfully realized.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
An asynchronous arbiter dynamically allocates a resource in response to requests from processes. ... more An asynchronous arbiter dynamically allocates a resource in response to requests from processes. Glitch-free operation when two requests arrive concurrently is possible in MOS technologies. Multiway arbitration using a request-grant-release-acknowledge protocol can be achieved by connecting together two-way arbiters (mutual exclusion and tree arbiter elements). We have devised a fast and compact design for the tree arbiter element which offers
the Second Australasian Parallel and Real-Time …, 1995
To provide predictable delays, the path(s) used by real-time packets must be known a priori. In p... more To provide predictable delays, the path(s) used by real-time packets must be known a priori. In point-to-point networks, a connection-oriented protocol such as virtual channels is used to meet this requirement 4] 12]. Faults in such networks due to node or link failures can lead ...
Current algorithms for schedulability analyses of the worst case delay and worst case buffer requ... more Current algorithms for schedulability analyses of the worst case delay and worst case buffer requirements for real-time network traffic have made one of two assumptions. 1) The networks are rate controlled (ie the source traffic pattern is reconstructed at each node) or 2) Traffic from multiple ...
Australian Computer Science Communications, 1995
Providing guaranteed timely delivery of real-time messages in point-to-point networks requires th... more Providing guaranteed timely delivery of real-time messages in point-to-point networks requires the reservation of network resources such as bu er space and bandwidth based on worst case tra c char-acteristics (eg maximum source rate, maximum transmission delay). For ...
The 16th Annual International Symposium on Computer Architecture, 1989
IEE Proceedings E Computers and Digital Techniques, 1989