Jae-Woong Nah - Academia.edu (original) (raw)
Papers by Jae-Woong Nah
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018
Innovations in healthcare, diagnostics, sensors and data analysis with Artificial Intelligence (A... more Innovations in healthcare, diagnostics, sensors and data analysis with Artificial Intelligence (AI) learning / recommendations offer opportunities for improved personalized healthcare, lower costs and benefits to the medical industry. The age of personalized human health monitoring has begun. Human health monitoring using fluidic diagnostic monitoring, noninvasive sensors, wearables (electronic health sensors), implanted health sensors, sound, visual images, and combinations of these data trends offer individuals personalized healthcare guidance. The data, analytics and recommendations from these personalized solutions are beginning to aide our early detection and understanding of health risks from chronic diseases and overall health / wellness. Examples include: cardiovascular disease, diabetes, oncology / cancer, kidney disease, elder care, Parkinson / Huntington Diseases, and many other healthcare applications. Rapid advancements of innovative healthcare diagnostic tools, health and environmental sensors along with data trending and analysis using AI systems or platforms can provide industry disruptions in healthcare. AI systems already aid health professionals and individuals with knowledge and recommendations that offer the promise of improved quality of life and lower healthcare costs. Examples such as: (1) earlier chronic disease detection and potential for disease progression delay or prevention, (2) understanding individual behavior, medication treatments and effectiveness of the treatments on activities of daily living and (3) personalized care based on your DNA, medical diagnostics and your healthcare trends relative to your healthcare needs and options to manage your quality of life. In this paper, we describe both new technologies and advancements to heterogeneous integration technology tools, materials and processes that provide differentiating electronics for future healthcare diagnostic tools and sensors. These new technologies are being applied to targeted applications in healthcare diagnostics and sensor monitoring for precision diagnostic data, smaller product size and much lower costs. Data streams can leverage AI to provide smart personalized healthcare guidance or solutions that compliment existing technology and data to partners such as healthcare professionals, patients and clients. In many applications, we leverage industry available technology or benefit from these new technology advancements to provide for the best system solution. Examples of these new and advancing technologies include: (1) Precision handling thinned wafers with large die, small die, multi-die, sub-components, components and substrates technologies, (2) Injection molded solder (IMS) technology for wafers (TSV and / or interconnection) and substrates, (3) Precision micro-component, die, multi-die substrate and multi-component assembly / integration technology for healthcare, IoT and AI Systems, (4) Precision laser micro-machining, cutting and welding technology, (5) Flexible multi-channel, micro-fluidic systems for smart sensing, point of care (POC) diagnostics, and AI and (6) Small form factor micro-systems and energy solutions / technologies that support future healthcare, IoT, and AI linked computing solutions. Examples of key challenges and advantages of these technologies for the targeted applications are shared relative to current industry standard solutions. Highlights on future demonstrations in progress at the time of writing this paper are targeted for our 2018 ECTC presentation and other future technical publications.
Journal of Applied Physics, Jul 1, 2005
The electromigration of flip chip solder joints consisting of 97Pb–3Sn and 37Pb–63Sn composite so... more The electromigration of flip chip solder joints consisting of 97Pb–3Sn and 37Pb–63Sn composite solders was studied under high current densities at room temperature. The mean time to failure and failure modes were found to be strongly dependent on the change in current density. The composite solder joints did not fail after 1month stressed at 4.07×104A∕cm2, but failed after just 10h of current stressing at 4.58×104A∕cm2. At a slightly higher current stressing of 5.00×104A∕cm2, the composite solder joints failed after only 0.6h due to melting. Precipitation and growth of Cu6Sn5 at the cathode caused the Cu under bump metallurgy to be quickly consumed and resulted in void formation at the contact area. The void reduced the contact area and displaced the electrical path, affecting the current crowding and Joule heating inside the solder bump. Significant Joule heating inside solder bumps can cause melting of the solder and quick failure. The effect of void propagation on current crowding and Joule heating was confirmed by simulation.
The electromigration in flip chip joints of Cu column bump with two different kinds of solder bum... more The electromigration in flip chip joints of Cu column bump with two different kinds of solder bumps; eutectic SnPb or eutectic SnAg was studied. The Cu columns were 50 mum thick and 50 mum diameter for eutectic SnPb solders and 80 mum thick and 85 mum diameter for eutectic SnAg solders. We observed that these flip chip joints did not
ABSTRACT We propose in this work an analysis method to study electromigration degradation through... more ABSTRACT We propose in this work an analysis method to study electromigration degradation through void size evolution at the failure time. Electrical aging tests are performed to characterize electromigration (EM) failure phenomenon on Cu lines. We followed the impact of various applied stressing currents on void sizes at the time of failure through the resistance step increase (Rstep). Two major findings emerge from this study. First, the voids size distributions at the failure time show a bimodal behavior symptomatic of different voids sizes and locations. Secondly, the proportion of higher void size values increases with the stress current. In addition to the comprehension of electromigration void growth mechanisms; this simple method is particularly useful during process development to track voids occurring under via.
Applied Physics Letters, Oct 2, 2006
The effect of electromigration on ductile-to-brittle transition in flip chip solder joints has be... more The effect of electromigration on ductile-to-brittle transition in flip chip solder joints has been studied using one-dimensional bamboo-type samples of eutectic 95.5Sn–3.8Ag–0.7Cu solder joined by Cu wires at two ends. Both electrical current and tensile stress were applied to the samples either in serial or in parallel. In serial tests, the strain rate was 6×10−3. In parallel test, the creep stress was 7MPa. The current density applied was (1–5)×103A∕cm2. The working temperature was 100–150°C. In both tests, the authors observed the ductile-to-brittle transition in which the fracture migrates from the middle to the cathode interface of the joint with increasing current density and time. The transition is explained by the polarity effect of electromigration, especially the accumulation of vacancies at the cathode interface.
In this paper, we will describe a new low cost solder bumping technology for use on wafers. The w... more In this paper, we will describe a new low cost solder bumping technology for use on wafers. The wafer IMS (injection molded solder) process can form fine pitch solder bumps on wafers, while offering greater solder alloy flexibility. This method is also applicable to form uniform solder bump heights when a wafer has different size and shape of I/O pads. The wafer IMS bumping process uses a solder injection head that melts the desired bulk solder alloy composition and then dispenses the molten solder into resist material cavities on wafers within a nitrogen environment. The injected molten solder contacts and wets to the metal pads without flux, thus forming intermetallic compounds at the solder/pad interface. After stripping the resist material, solder bumps exhibit straight side walls and round tops as the solders have solidified inside the cavities of this resist film. This particular geometry is unique and offers a ready-for-substrate bonding condition without an additional reflow step. In the case of using Cu pillars, one resist material is used for both Cu electroplating and molten solder injection. After patterning the resist material, the Cu pillars are electroplated to the desired height, and the remaining cavities of resist material are filled by the injection of molten solder. The final bump height is defined by the thickness of the resist material. Therefore, any non-uniformity of Cu pillar height across a wafer is masked by the final solder bump uniformity. A prototype tool for wafer IMS bumping technology has been developed and solder bumping has successfully been demonstrated with Sn-3.0Ag-0.5Cu solder on 200mm wafers. The test wafer employed interconnects pads of four different diameters and three different shapes. Other solder compositions have also been tried successfully.
Flip-chip assembly with self-alignment down to sub-micron accuracy opens the door for low-cost as... more Flip-chip assembly with self-alignment down to sub-micron accuracy opens the door for low-cost assembly of micro-photonic chips. The surface tension of melted solder can be used to bring chips into alignment. The use of lithographically defined mechanical structures to stop the solder induced movement provides sub-micron alignment accuracy. However, several factors can impact the solder realignment yield. In this paper, we investigate the various yield limiting contributors and show that sensitivity to solder volume is the dominating factor. Variation in the amount of solder strongly impacts the lateral and vertical force induced by the solder, resulting in two small a process window for manufacturability. We show through models and experiments a design-based solution that dramatically improves the process window and yield. By the addition of local solder "reservoirs" we create a self-balanced system to improve solder plating tolerances from just a few percent to nearly a factor of two.
Cost can hinder the societal impact of a technology 2 Cost is not just a commercial concern. It d... more Cost can hinder the societal impact of a technology 2 Cost is not just a commercial concern. It defines the accessibility of a technology. Today's challenge in optics: accessibility reduce cost by 10-100X major impact
The packaging of photonic devices remains a hindering challenge to the deployment of integrated p... more The packaging of photonic devices remains a hindering challenge to the deployment of integrated photonic modules. This is never as true as for silicon photonic modules where the cost efficiency and scalability of chip fabrication in microelectronic production facilities is far ahead of current photonic packaging technology. More often than not, photonic modules are still packaged today with legacy manual processes and high-precision active alignment. Automation of these manual processes can provide gains in yield and scalability. Thus, specialized automated equipment has been developed for photonic packaging, is now commercially available, and is providing an incremental improvement in cost and scalability. However, to bring the cost and scalability of photonic packaging on par with silicon chip fabrication, we feel a more disruptive approach is required. Hence, in recent years, we have developed photonic packaging in standard, highthroughput microelectronic packaging facilities. This approach relies on the concepts already responsible for the attractiveness of silicon photonic chip fabrication: (1) moving complexity from die-level packaging processes to waferlevel planar fabrication, and (2) leveraging the scale of existing microelectronic facilities for photonic fabrication. We have demonstrated such direction with peak coupling performance of 1.3 dB from standard cleaved fiber to chip and 1.1 dB from chip to chip.
Optical Fiber Communication Conference, 2015
We demonstrate silicon photonic packaging that can be fully exercised in existing microelectronic... more We demonstrate silicon photonic packaging that can be fully exercised in existing microelectronic packaging facilities. We show low optical loss and point towards notably improved assembly cost and scalability in both volume and optical port-count.
Optical Fiber Technology, Aug 1, 2018
Abstract Silicon photonics can enable optical circuits of unprecedented complexity and cost effic... more Abstract Silicon photonics can enable optical circuits of unprecedented complexity and cost efficiency. It employs lithography to effectively pre-assemble optical devices on wafers fabricated in existing microelectronic facilities with decades of cost and reliability optimization. Unfortunately, the packaging of photonic chips still employs legacy approaches, which limit the device’s cost efficiency and scalability. To address this challenge, we have developed a novel approach to photonic packaging centered on shifting complexity from chip-level assembly to wafer-level planar fabrication. Self-alignment structures and large-mode converters are integrated on chip to enable photonic packaging in standard, automated, high-throughput microelectronic assembly tools. We demonstrate solutions to interfacing standard optical fibers to chips and to interfacing photonic chips to other photonic chips. We show wide spectral bandwidth and a peak transmission of −1.3 dB from a standard fiber patch cable to chip and −1.1 dB from chip to chip. We believe this new direction can help silicon photonics reach its full potential.
Self-aligned flip-chip assembly with sub-micron accuracy is of particular importance to low-cost ... more Self-aligned flip-chip assembly with sub-micron accuracy is of particular importance to low-cost manufacturing of single-mode opto-electronic components. The concept of alignment via surface tension force of melted solder has been proposed over two decades ago and appears simple. Yet, its effective working into manufacturing requires solving a few fundamental issues. In prior work, we introduced the concept of solder reservoirs which provide a solder volume self-balancing mechanism to notably enhance self-alignment yield. In this paper, we show that the effectiveness of reservoirs is impeded when the solder wetting of pads or the solder mobility between pads and reservoirs is limited. We therefore studied a wide variety of metal stacks and identified candidates for substantial wetting and solder mobility improvement. We ranked the metal stacks for solder mobility using traditional wetting angles as well as speed of wetting along narrow tracks. First test parts, manufactured with the improved metal stacks, show the expected benefit in increased yield for chip alignment.
We demonstrate experimentally a flip-chip assembly with submicron three-dimensional alignment acc... more We demonstrate experimentally a flip-chip assembly with submicron three-dimensional alignment accuracy. We employ solder surface tension to push the flipped chip into lithographically defined alignment stops. During reflow, surface tension forces of the melted solder can move a chip by more than a hundred microns. We use these motions to obtain self-alignment by constraining the motions to lithographically defined mechanical stops and chip edge butting. This approach is particularly useful in InP laser to Si photonic assemblies, where sub-micron alignment is required for low optical connection loss. In this report, our test vehicles comprise silicon photonic chips and laser placeholder chips made of silicon as well. To enable self-alignment of edgeemitting single-mode lasers, a significant realignment range is needed to overcome the laser cleaving tolerance of +/-15 microns and the low +/-10 microns placement accuracy of high-throughput pick-and-place tools. We employ in-situ infrared (IR) microscopy to look through the assembled chips during solder induced realignment. We show that the selfalignment of the chips starts at the moment the solders melt. Cross sectional analysis is used to confirm the alignment accuracy and contact on the lithographic stops. We discuss process window considerations related to standoff height and solder volume.
Self-alignment via solder-surface tension in flip-chip bonding opens the door to low-cost, high-t... more Self-alignment via solder-surface tension in flip-chip bonding opens the door to low-cost, high-throughput assembly of components with sub-micron accuracy. This is especially impactful to integrated photonics as used for high speed optical communication and sensors [1,2]. Assembly yield hinges on the details of solder-induced forces and on the geometry of the melted solder surface. Low curvature of melted solder is best to balance solder forces for optimal re-alignment yield but leads to shallow contact angles and solder de-wetting on traditional solder pads. We introduce and demonstrate the concept of recessed solder pads with shallow angled edges. Such geometry enables arbitrarily-low curvature of the molten solder surface and even flat or slightly concave shapes. The solder stays anchored at the angled edges of recessed pads and can be made to flow in long and narrow conduits. Both aspects are key to widening the fabrication and process window for the solder-induced chip-alignment technology.
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018
Innovations in healthcare, diagnostics, sensors and data analysis with Artificial Intelligence (A... more Innovations in healthcare, diagnostics, sensors and data analysis with Artificial Intelligence (AI) learning / recommendations offer opportunities for improved personalized healthcare, lower costs and benefits to the medical industry. The age of personalized human health monitoring has begun. Human health monitoring using fluidic diagnostic monitoring, noninvasive sensors, wearables (electronic health sensors), implanted health sensors, sound, visual images, and combinations of these data trends offer individuals personalized healthcare guidance. The data, analytics and recommendations from these personalized solutions are beginning to aide our early detection and understanding of health risks from chronic diseases and overall health / wellness. Examples include: cardiovascular disease, diabetes, oncology / cancer, kidney disease, elder care, Parkinson / Huntington Diseases, and many other healthcare applications. Rapid advancements of innovative healthcare diagnostic tools, health and environmental sensors along with data trending and analysis using AI systems or platforms can provide industry disruptions in healthcare. AI systems already aid health professionals and individuals with knowledge and recommendations that offer the promise of improved quality of life and lower healthcare costs. Examples such as: (1) earlier chronic disease detection and potential for disease progression delay or prevention, (2) understanding individual behavior, medication treatments and effectiveness of the treatments on activities of daily living and (3) personalized care based on your DNA, medical diagnostics and your healthcare trends relative to your healthcare needs and options to manage your quality of life. In this paper, we describe both new technologies and advancements to heterogeneous integration technology tools, materials and processes that provide differentiating electronics for future healthcare diagnostic tools and sensors. These new technologies are being applied to targeted applications in healthcare diagnostics and sensor monitoring for precision diagnostic data, smaller product size and much lower costs. Data streams can leverage AI to provide smart personalized healthcare guidance or solutions that compliment existing technology and data to partners such as healthcare professionals, patients and clients. In many applications, we leverage industry available technology or benefit from these new technology advancements to provide for the best system solution. Examples of these new and advancing technologies include: (1) Precision handling thinned wafers with large die, small die, multi-die, sub-components, components and substrates technologies, (2) Injection molded solder (IMS) technology for wafers (TSV and / or interconnection) and substrates, (3) Precision micro-component, die, multi-die substrate and multi-component assembly / integration technology for healthcare, IoT and AI Systems, (4) Precision laser micro-machining, cutting and welding technology, (5) Flexible multi-channel, micro-fluidic systems for smart sensing, point of care (POC) diagnostics, and AI and (6) Small form factor micro-systems and energy solutions / technologies that support future healthcare, IoT, and AI linked computing solutions. Examples of key challenges and advantages of these technologies for the targeted applications are shared relative to current industry standard solutions. Highlights on future demonstrations in progress at the time of writing this paper are targeted for our 2018 ECTC presentation and other future technical publications.
Journal of Applied Physics, Jul 1, 2005
The electromigration of flip chip solder joints consisting of 97Pb–3Sn and 37Pb–63Sn composite so... more The electromigration of flip chip solder joints consisting of 97Pb–3Sn and 37Pb–63Sn composite solders was studied under high current densities at room temperature. The mean time to failure and failure modes were found to be strongly dependent on the change in current density. The composite solder joints did not fail after 1month stressed at 4.07×104A∕cm2, but failed after just 10h of current stressing at 4.58×104A∕cm2. At a slightly higher current stressing of 5.00×104A∕cm2, the composite solder joints failed after only 0.6h due to melting. Precipitation and growth of Cu6Sn5 at the cathode caused the Cu under bump metallurgy to be quickly consumed and resulted in void formation at the contact area. The void reduced the contact area and displaced the electrical path, affecting the current crowding and Joule heating inside the solder bump. Significant Joule heating inside solder bumps can cause melting of the solder and quick failure. The effect of void propagation on current crowding and Joule heating was confirmed by simulation.
The electromigration in flip chip joints of Cu column bump with two different kinds of solder bum... more The electromigration in flip chip joints of Cu column bump with two different kinds of solder bumps; eutectic SnPb or eutectic SnAg was studied. The Cu columns were 50 mum thick and 50 mum diameter for eutectic SnPb solders and 80 mum thick and 85 mum diameter for eutectic SnAg solders. We observed that these flip chip joints did not
ABSTRACT We propose in this work an analysis method to study electromigration degradation through... more ABSTRACT We propose in this work an analysis method to study electromigration degradation through void size evolution at the failure time. Electrical aging tests are performed to characterize electromigration (EM) failure phenomenon on Cu lines. We followed the impact of various applied stressing currents on void sizes at the time of failure through the resistance step increase (Rstep). Two major findings emerge from this study. First, the voids size distributions at the failure time show a bimodal behavior symptomatic of different voids sizes and locations. Secondly, the proportion of higher void size values increases with the stress current. In addition to the comprehension of electromigration void growth mechanisms; this simple method is particularly useful during process development to track voids occurring under via.
Applied Physics Letters, Oct 2, 2006
The effect of electromigration on ductile-to-brittle transition in flip chip solder joints has be... more The effect of electromigration on ductile-to-brittle transition in flip chip solder joints has been studied using one-dimensional bamboo-type samples of eutectic 95.5Sn–3.8Ag–0.7Cu solder joined by Cu wires at two ends. Both electrical current and tensile stress were applied to the samples either in serial or in parallel. In serial tests, the strain rate was 6×10−3. In parallel test, the creep stress was 7MPa. The current density applied was (1–5)×103A∕cm2. The working temperature was 100–150°C. In both tests, the authors observed the ductile-to-brittle transition in which the fracture migrates from the middle to the cathode interface of the joint with increasing current density and time. The transition is explained by the polarity effect of electromigration, especially the accumulation of vacancies at the cathode interface.
In this paper, we will describe a new low cost solder bumping technology for use on wafers. The w... more In this paper, we will describe a new low cost solder bumping technology for use on wafers. The wafer IMS (injection molded solder) process can form fine pitch solder bumps on wafers, while offering greater solder alloy flexibility. This method is also applicable to form uniform solder bump heights when a wafer has different size and shape of I/O pads. The wafer IMS bumping process uses a solder injection head that melts the desired bulk solder alloy composition and then dispenses the molten solder into resist material cavities on wafers within a nitrogen environment. The injected molten solder contacts and wets to the metal pads without flux, thus forming intermetallic compounds at the solder/pad interface. After stripping the resist material, solder bumps exhibit straight side walls and round tops as the solders have solidified inside the cavities of this resist film. This particular geometry is unique and offers a ready-for-substrate bonding condition without an additional reflow step. In the case of using Cu pillars, one resist material is used for both Cu electroplating and molten solder injection. After patterning the resist material, the Cu pillars are electroplated to the desired height, and the remaining cavities of resist material are filled by the injection of molten solder. The final bump height is defined by the thickness of the resist material. Therefore, any non-uniformity of Cu pillar height across a wafer is masked by the final solder bump uniformity. A prototype tool for wafer IMS bumping technology has been developed and solder bumping has successfully been demonstrated with Sn-3.0Ag-0.5Cu solder on 200mm wafers. The test wafer employed interconnects pads of four different diameters and three different shapes. Other solder compositions have also been tried successfully.
Flip-chip assembly with self-alignment down to sub-micron accuracy opens the door for low-cost as... more Flip-chip assembly with self-alignment down to sub-micron accuracy opens the door for low-cost assembly of micro-photonic chips. The surface tension of melted solder can be used to bring chips into alignment. The use of lithographically defined mechanical structures to stop the solder induced movement provides sub-micron alignment accuracy. However, several factors can impact the solder realignment yield. In this paper, we investigate the various yield limiting contributors and show that sensitivity to solder volume is the dominating factor. Variation in the amount of solder strongly impacts the lateral and vertical force induced by the solder, resulting in two small a process window for manufacturability. We show through models and experiments a design-based solution that dramatically improves the process window and yield. By the addition of local solder "reservoirs" we create a self-balanced system to improve solder plating tolerances from just a few percent to nearly a factor of two.
Cost can hinder the societal impact of a technology 2 Cost is not just a commercial concern. It d... more Cost can hinder the societal impact of a technology 2 Cost is not just a commercial concern. It defines the accessibility of a technology. Today's challenge in optics: accessibility reduce cost by 10-100X major impact
The packaging of photonic devices remains a hindering challenge to the deployment of integrated p... more The packaging of photonic devices remains a hindering challenge to the deployment of integrated photonic modules. This is never as true as for silicon photonic modules where the cost efficiency and scalability of chip fabrication in microelectronic production facilities is far ahead of current photonic packaging technology. More often than not, photonic modules are still packaged today with legacy manual processes and high-precision active alignment. Automation of these manual processes can provide gains in yield and scalability. Thus, specialized automated equipment has been developed for photonic packaging, is now commercially available, and is providing an incremental improvement in cost and scalability. However, to bring the cost and scalability of photonic packaging on par with silicon chip fabrication, we feel a more disruptive approach is required. Hence, in recent years, we have developed photonic packaging in standard, highthroughput microelectronic packaging facilities. This approach relies on the concepts already responsible for the attractiveness of silicon photonic chip fabrication: (1) moving complexity from die-level packaging processes to waferlevel planar fabrication, and (2) leveraging the scale of existing microelectronic facilities for photonic fabrication. We have demonstrated such direction with peak coupling performance of 1.3 dB from standard cleaved fiber to chip and 1.1 dB from chip to chip.
Optical Fiber Communication Conference, 2015
We demonstrate silicon photonic packaging that can be fully exercised in existing microelectronic... more We demonstrate silicon photonic packaging that can be fully exercised in existing microelectronic packaging facilities. We show low optical loss and point towards notably improved assembly cost and scalability in both volume and optical port-count.
Optical Fiber Technology, Aug 1, 2018
Abstract Silicon photonics can enable optical circuits of unprecedented complexity and cost effic... more Abstract Silicon photonics can enable optical circuits of unprecedented complexity and cost efficiency. It employs lithography to effectively pre-assemble optical devices on wafers fabricated in existing microelectronic facilities with decades of cost and reliability optimization. Unfortunately, the packaging of photonic chips still employs legacy approaches, which limit the device’s cost efficiency and scalability. To address this challenge, we have developed a novel approach to photonic packaging centered on shifting complexity from chip-level assembly to wafer-level planar fabrication. Self-alignment structures and large-mode converters are integrated on chip to enable photonic packaging in standard, automated, high-throughput microelectronic assembly tools. We demonstrate solutions to interfacing standard optical fibers to chips and to interfacing photonic chips to other photonic chips. We show wide spectral bandwidth and a peak transmission of −1.3 dB from a standard fiber patch cable to chip and −1.1 dB from chip to chip. We believe this new direction can help silicon photonics reach its full potential.
Self-aligned flip-chip assembly with sub-micron accuracy is of particular importance to low-cost ... more Self-aligned flip-chip assembly with sub-micron accuracy is of particular importance to low-cost manufacturing of single-mode opto-electronic components. The concept of alignment via surface tension force of melted solder has been proposed over two decades ago and appears simple. Yet, its effective working into manufacturing requires solving a few fundamental issues. In prior work, we introduced the concept of solder reservoirs which provide a solder volume self-balancing mechanism to notably enhance self-alignment yield. In this paper, we show that the effectiveness of reservoirs is impeded when the solder wetting of pads or the solder mobility between pads and reservoirs is limited. We therefore studied a wide variety of metal stacks and identified candidates for substantial wetting and solder mobility improvement. We ranked the metal stacks for solder mobility using traditional wetting angles as well as speed of wetting along narrow tracks. First test parts, manufactured with the improved metal stacks, show the expected benefit in increased yield for chip alignment.
We demonstrate experimentally a flip-chip assembly with submicron three-dimensional alignment acc... more We demonstrate experimentally a flip-chip assembly with submicron three-dimensional alignment accuracy. We employ solder surface tension to push the flipped chip into lithographically defined alignment stops. During reflow, surface tension forces of the melted solder can move a chip by more than a hundred microns. We use these motions to obtain self-alignment by constraining the motions to lithographically defined mechanical stops and chip edge butting. This approach is particularly useful in InP laser to Si photonic assemblies, where sub-micron alignment is required for low optical connection loss. In this report, our test vehicles comprise silicon photonic chips and laser placeholder chips made of silicon as well. To enable self-alignment of edgeemitting single-mode lasers, a significant realignment range is needed to overcome the laser cleaving tolerance of +/-15 microns and the low +/-10 microns placement accuracy of high-throughput pick-and-place tools. We employ in-situ infrared (IR) microscopy to look through the assembled chips during solder induced realignment. We show that the selfalignment of the chips starts at the moment the solders melt. Cross sectional analysis is used to confirm the alignment accuracy and contact on the lithographic stops. We discuss process window considerations related to standoff height and solder volume.
Self-alignment via solder-surface tension in flip-chip bonding opens the door to low-cost, high-t... more Self-alignment via solder-surface tension in flip-chip bonding opens the door to low-cost, high-throughput assembly of components with sub-micron accuracy. This is especially impactful to integrated photonics as used for high speed optical communication and sensors [1,2]. Assembly yield hinges on the details of solder-induced forces and on the geometry of the melted solder surface. Low curvature of melted solder is best to balance solder forces for optimal re-alignment yield but leads to shallow contact angles and solder de-wetting on traditional solder pads. We introduce and demonstrate the concept of recessed solder pads with shallow angled edges. Such geometry enables arbitrarily-low curvature of the molten solder surface and even flat or slightly concave shapes. The solder stays anchored at the angled edges of recessed pads and can be made to flow in long and narrow conduits. Both aspects are key to widening the fabrication and process window for the solder-induced chip-alignment technology.