Javier Resano - Academia.edu (original) (raw)

Papers by Javier Resano

Research paper thumbnail of A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware

Computing Research Repository, 2007

Due to the emergence of highly dynamic multimedia applications there is a need for flexible platf... more Due to the emergence of highly dynamic multimedia applications there is a need for flexible platforms and run-time scheduling support for embedded systems. Dynamic Reconfigurable Hardware (DRHW) is a promising candidate to provide this flexibility but, currently, not sufficient run-time scheduling support to deal with the run-time reconfigurations exists. Moreover, executing at run-time a complex scheduling heuristic to provide this

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Research paper thumbnail of Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015

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Research paper thumbnail of Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems

Lecture Notes in Computer Science, 2003

Dynamically Reconfigurable Hardware (DRHW) can take advantage of its reconfiguration capability t... more Dynamically Reconfigurable Hardware (DRHW) can take advantage of its reconfiguration capability to adapt at run-time its performance and its energy consumption. However, due to the lack of programming support for dynamic task placement on these platforms, little previous work has been presented studying these run-time performance/power trade-offs. To cope with the task placement problem we have adopted an interconnection-network-based DRHW

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Research paper thumbnail of Application of task concurrency management on dynamically reconfigurable hardware platforms

11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003., 2003

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Research paper thumbnail of Inst. for Appl. Microelectron.(IUMA), Univ. of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain

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Research paper thumbnail of FPGA Design of the N-FINDR Algorithm for Spaceborne Hyperspectral Missions

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Research paper thumbnail of Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware

Proceedings of the 41st annual conference on Design automation - DAC '04, 2004

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Research paper thumbnail of A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements

Lecture Notes in Computer Science, 2003

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Research paper thumbnail of Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors

Microprocessors and Microsystems, 2015

ABSTRACT

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Research paper thumbnail of A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware

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Research paper thumbnail of A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead

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Research paper thumbnail of FPGA support for satellite computations of hyper spectral images

... Carlos Gonzalez, Daniel Mozos Javier Resano ... [2] M. Goretti "Digi... more ... Carlos Gonzalez, Daniel Mozos Javier Resano ... [2] M. Goretti "Digital circuits ... [3] D. Valencia, A. Plaza, Miguel A. Vega-Rodriguez, and RM Perez, "FPGA Design and Implementation of a Fast Pixel Purity Index Algorithm for Endmember Extraction in Hyperspectral Imagery", Proc. ...

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Research paper thumbnail of Mini workshop - Real world engineering projects: Discovery-based curriculum modules for first-year students

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Research paper thumbnail of FPGA implementation of endmember extraction algorithms from hyperspectral imagery: Pixel purity index versus N-FINDR

Endmember extraction is an important task for remotely sensed hyperspectral data exploitation. It... more Endmember extraction is an important task for remotely sensed hyperspectral data exploitation. It comprises the identification of spectral signatures corresponding to macroscopically pure components in the scene, so that mixed pixels (resulting from limited spatial resolution, mixing phenomena happening at different scales, etc.) can be decomposed into combinations of pure component spectra weighted by an estimation of the proportion (abundance)

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Research paper thumbnail of A replacement technique to maximize task reuse in reconfigurable systems

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Research paper thumbnail of FPGA implementation of abundance estimation for spectral unmixing of hyperspectral data using the image space reconstruction algorithm

One of the most popular and widely used techniques for analyzing remotely sensed hyperspectral da... more One of the most popular and widely used techniques for analyzing remotely sensed hyperspectral data is spectral unmixing, which relies on two stages: (i) identification of pure spectral signatures (endmembers) in the data, and (ii) estimation of the abundance of each endmember in each (possibly mixed) pixel. Due to the high dimensionality of the hyperspectral data, spectral unmixing is a

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Research paper thumbnail of A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems

2008 International Conference on Reconfigurable Computing and FPGAs, 2008

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Research paper thumbnail of An FPGA-based specific processor for Blokus Duo

2013 International Conference on Field-Programmable Technology (FPT), 2013

ABSTRACT

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Research paper thumbnail of An initial specific processor for Sudoku solving

2009 International Conference on Field-Programmable Technology, 2009

In this article, we present a design of a Sudoku solver submitted to the FPT Design Competition. ... more In this article, we present a design of a Sudoku solver submitted to the FPT Design Competition. Using only the on-chip resources of a XC2VP30 Virtex-II Pro FPGA we have designed a specific processor that can solve Sudokus from order 3 to 11. This processor applies a Branch&Bound approach to explore the solution space. However, this solution space is too

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Research paper thumbnail of FPGA implementation of a strong Reversi player

2010 International Conference on Field-Programmable Technology, 2010

In this article, we present a design of a Reversi player submitted to the FPT'10 Design Comp... more In this article, we present a design of a Reversi player submitted to the FPT'10 Design Competition and implemented on a XC2VP30 Virtex-II Pro FPGA. Our player applies several techniques to explore the solution space attempting to look as many moves forward as possible for the given time, and uses several metrics to evaluate the quality of a given board. The most important metric is the mobility, basically our player attempts to maximise its available moves whereas minimising the opponent moves. With these techniques our player easily defeats the competition software opponent.

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Research paper thumbnail of A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware

Computing Research Repository, 2007

Due to the emergence of highly dynamic multimedia applications there is a need for flexible platf... more Due to the emergence of highly dynamic multimedia applications there is a need for flexible platforms and run-time scheduling support for embedded systems. Dynamic Reconfigurable Hardware (DRHW) is a promising candidate to provide this flexibility but, currently, not sufficient run-time scheduling support to deal with the run-time reconfigurations exists. Moreover, executing at run-time a complex scheduling heuristic to provide this

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Research paper thumbnail of Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015

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Research paper thumbnail of Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems

Lecture Notes in Computer Science, 2003

Dynamically Reconfigurable Hardware (DRHW) can take advantage of its reconfiguration capability t... more Dynamically Reconfigurable Hardware (DRHW) can take advantage of its reconfiguration capability to adapt at run-time its performance and its energy consumption. However, due to the lack of programming support for dynamic task placement on these platforms, little previous work has been presented studying these run-time performance/power trade-offs. To cope with the task placement problem we have adopted an interconnection-network-based DRHW

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Research paper thumbnail of Application of task concurrency management on dynamically reconfigurable hardware platforms

11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003., 2003

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Research paper thumbnail of Inst. for Appl. Microelectron.(IUMA), Univ. of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain

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Research paper thumbnail of FPGA Design of the N-FINDR Algorithm for Spaceborne Hyperspectral Missions

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware

Proceedings of the 41st annual conference on Design automation - DAC '04, 2004

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Research paper thumbnail of A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements

Lecture Notes in Computer Science, 2003

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Research paper thumbnail of Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors

Microprocessors and Microsystems, 2015

ABSTRACT

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Research paper thumbnail of A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware

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Research paper thumbnail of A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead

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Research paper thumbnail of FPGA support for satellite computations of hyper spectral images

... Carlos Gonzalez, Daniel Mozos Javier Resano ... [2] M. Goretti "Digi... more ... Carlos Gonzalez, Daniel Mozos Javier Resano ... [2] M. Goretti "Digital circuits ... [3] D. Valencia, A. Plaza, Miguel A. Vega-Rodriguez, and RM Perez, "FPGA Design and Implementation of a Fast Pixel Purity Index Algorithm for Endmember Extraction in Hyperspectral Imagery", Proc. ...

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Research paper thumbnail of Mini workshop - Real world engineering projects: Discovery-based curriculum modules for first-year students

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Research paper thumbnail of FPGA implementation of endmember extraction algorithms from hyperspectral imagery: Pixel purity index versus N-FINDR

Endmember extraction is an important task for remotely sensed hyperspectral data exploitation. It... more Endmember extraction is an important task for remotely sensed hyperspectral data exploitation. It comprises the identification of spectral signatures corresponding to macroscopically pure components in the scene, so that mixed pixels (resulting from limited spatial resolution, mixing phenomena happening at different scales, etc.) can be decomposed into combinations of pure component spectra weighted by an estimation of the proportion (abundance)

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Research paper thumbnail of A replacement technique to maximize task reuse in reconfigurable systems

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Research paper thumbnail of FPGA implementation of abundance estimation for spectral unmixing of hyperspectral data using the image space reconstruction algorithm

One of the most popular and widely used techniques for analyzing remotely sensed hyperspectral da... more One of the most popular and widely used techniques for analyzing remotely sensed hyperspectral data is spectral unmixing, which relies on two stages: (i) identification of pure spectral signatures (endmembers) in the data, and (ii) estimation of the abundance of each endmember in each (possibly mixed) pixel. Due to the high dimensionality of the hyperspectral data, spectral unmixing is a

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Research paper thumbnail of A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems

2008 International Conference on Reconfigurable Computing and FPGAs, 2008

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Research paper thumbnail of An FPGA-based specific processor for Blokus Duo

2013 International Conference on Field-Programmable Technology (FPT), 2013

ABSTRACT

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Research paper thumbnail of An initial specific processor for Sudoku solving

2009 International Conference on Field-Programmable Technology, 2009

In this article, we present a design of a Sudoku solver submitted to the FPT Design Competition. ... more In this article, we present a design of a Sudoku solver submitted to the FPT Design Competition. Using only the on-chip resources of a XC2VP30 Virtex-II Pro FPGA we have designed a specific processor that can solve Sudokus from order 3 to 11. This processor applies a Branch&Bound approach to explore the solution space. However, this solution space is too

Bookmarks Related papers MentionsView impact

Research paper thumbnail of FPGA implementation of a strong Reversi player

2010 International Conference on Field-Programmable Technology, 2010

In this article, we present a design of a Reversi player submitted to the FPT'10 Design Comp... more In this article, we present a design of a Reversi player submitted to the FPT'10 Design Competition and implemented on a XC2VP30 Virtex-II Pro FPGA. Our player applies several techniques to explore the solution space attempting to look as many moves forward as possible for the given time, and uses several metrics to evaluate the quality of a given board. The most important metric is the mobility, basically our player attempts to maximise its available moves whereas minimising the opponent moves. With these techniques our player easily defeats the competition software opponent.

Bookmarks Related papers MentionsView impact