Javier Salcedo - Academia.edu (original) (raw)

Papers by Javier Salcedo

Research paper thumbnail of A sinh resistor and its application to tanh linearization

IEEE Journal of Solid-State Circuits, 2005

We present a novel and simple subthreshold tunable resistor (sinh) which exhibits a sinh-characte... more We present a novel and simple subthreshold tunable resistor (sinh) which exhibits a sinh-characteristic. This compact 8-transistor circuit generates an output current that is proportional to the sinh of its input differential voltage and has an offset-free characteristic, i.e., zero current at zero differential voltage, like a real resistor. In a 1.5-m CMOS chip implementation, we achieved a common-mode rejection ratio (CMRR) of 46 dB. As an example application, we use the expansive properties of our sinh to linearize the compressive properties of a tanh differential pair by degeneration and cancel all nonlinearities up to fifth order. We demonstrate good agreement between theory and experimental results.

Research paper thumbnail of On-chip electrostatic discharge protection for CMOS gas sensor systems-on-a-chip (SoC)

Microelectronics Reliability, 2006

An on-chip electrostatic discharge (ESD) protection scheme is demonstrated for an emerging techno... more An on-chip electrostatic discharge (ESD) protection scheme is demonstrated for an emerging technology of microelectromechanical systems (MEMS)-based embedded sensor (ES) system-on-a-chip (SoC). The ESD protection scheme is implemented using ground-...

Research paper thumbnail of TCAD Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications

IEEE Transactions on Electron Devices, 2007

Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical expe... more Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical experience and know-how. A technology computer-aided design (TCAD) methodology aimed to assist in the design and implementation of robust ESD devices is developed and presented. The methodology provides a systematic and practical means for the evaluation and optimization of ESD devices in a simulation environment. Advanced siliconcontrolled-rectifier devices are considered to illustrate the approach, and experimental data measured from these devices are also included in support of the TCAD development.

Research paper thumbnail of Analysis of Safe Operating Area of NLDMOS and PLDMOS Transistors Subject to Transient Stresses

IEEE Transactions on Electron Devices, 2010

Transient safe operating area (TSOA) of n-type and p-type laterally diffused metal-oxide-semicond... more Transient safe operating area (TSOA) of n-type and p-type laterally diffused metal-oxide-semiconductor (LDMOS) subject to transient stresses is presented for electrostatic discharge applications. LDMOS devices connected in the gate-grounded and gate-biased configurations are stressed with 1-, 2-, 5-, 10-, and 100-ns duration transmission line pulses, and a methodology to develop an effective and accurate TSOA based on these measurements is discussed. Two-dimensional technology computer-aided design simulations are also used to discuss critical physical mechanisms governing the current conduction during the transients and the condition that finally leads to device failure beyond the TSOA. Index Terms-Laterally diffused metal-oxide-semiconductor (LDMOS), transient safe operating area (TSOA), transmission line pulsing (TLP), very fast transmission line pulse (VFTLP).

Research paper thumbnail of Prediction and Modeling of Thin Gate Oxide Breakdown Subject to Arbitrary Transient Stresses

IEEE Transactions on Electron Devices, 2010

A reliable dielectric breakdown model under transient stresses via an extension of the power law ... more A reliable dielectric breakdown model under transient stresses via an extension of the power law is demonstrated. The model, which is based on the percolation model and the assumption of no significant detrapping, is successfully used in ramped voltage stress breakdown analysis. A demonstration of the model's validity consists of applying repetitive time-variant voltage waveforms-pulses, sine waves, ramps, and noise-until breakdown and, consequently, comparing prediction to reality. The breakdown distribution is initially derived from DC measurements, with the model predicting both the center and the shape of the distribution. Index Terms-Charged device model (CDM), gate oxide breakdown (GOB), power law (PL), time-dependent dielectric breakdown (TDDB), very fast transmission line pulse (VFTLP).

Research paper thumbnail of Comments on “A sinh Resistor and Its Application to tanh Linearization&#8221

IEEE Journal of Solid-State Circuits, 2006

Research paper thumbnail of ESD Protection Device With Dual-Polarity Conduction and High Blocking Voltage Realized in CMOS Process

IEEE Electron Device Letters, 2014

Electrostatic discharge (ESD) protection devices fabricated in a low-voltage CMOS process for com... more Electrostatic discharge (ESD) protection devices fabricated in a low-voltage CMOS process for communication interface applications typically provide relatively small blocking voltage, thus limiting the interface operating voltage range for which the ESD device can be used. This letter introduces a CMOS-based silicon controlled rectifier with a large blocking voltage beyond ±20 V and a high trigger current. Such a high blocking voltage is achieved by selectively defining native-buffer regions in critical blocking junctions of the device. Experimental characterization of the ESD robustness and standing operation are presented to validate the new device for low capacitance, high-voltage-tolerant communication interface ESD protection applications.

Research paper thumbnail of Bidirectional Devices for Automotive-Grade Electrostatic Discharge Applications

IEEE Electron Device Letters, 2012

ABSTRACT High bidirectional holding-voltage clamps are introduced for applications operating in h... more ABSTRACT High bidirectional holding-voltage clamps are introduced for applications operating in harsh environments. The clamps' terminals are formed with complementary doped 3-D "T" pattern and island active regions. Transmission-line-pulsed current in the ranges of ±0.15 and ±0.39 mA/μm2 is demonstrated for ±40- and ±25-V holding-voltage clamps, respectively. The high bidirectional holding voltage is optimized without increasing spacing between the terminals of the devices, achieving a compact clamp architecture successfully codesigned with advanced transceiver circuits.

Research paper thumbnail of High-Robustness and Low-Capacitance Silicon-Controlled Rectifier for High-Speed I/O ESD Protection

IEEE Electron Device Letters, 2013

ABSTRACT A high-robustness and low-capacitance clamp for on-chip electrostatic discharge (ESD) pr... more ABSTRACT A high-robustness and low-capacitance clamp for on-chip electrostatic discharge (ESD) protection is developed. The low capacitance is obtained by mitigating the capacitance associated with the lightly doped n-well/p-well junction. In addition to minimizing the capacitance, the high ESD robustness is achieved by optimizing independently within the same structure a silicon-controlled rectifier and a diode for the forward and reverse conduction processes, respectively. The new clamp with an area of 50 × 10 μm2 is able to handle an ESD current in excess of 1.5 A, whereas the capacitance at zero bias is kept at 94 fF.

Research paper thumbnail of Snapback and Postsnapback Saturation of Pseudomorphic High-Electron Mobility Transistor Subject to Transient Overstress

IEEE Electron Device Letters, 2010

The snapback and postsnapback saturation characteristics in a pseudomorphic high-electron mobilit... more The snapback and postsnapback saturation characteristics in a pseudomorphic high-electron mobility transistor (PHEMT) subject to electrostatic discharge (ESD) transient overstress are studied. This is undertaken, for the first time, via transmission line pulsing (TLP)-like 2-D device simulations and benchmarked against TLP measurements. Physical mechanisms underlying the postsnapback behavior and ESD-induced failure are identified and discussed by analyzing TLP-like simulation results rather than extrapolating dc-like numerical simulation data.

Research paper thumbnail of Correlation of Human Metal Model and Transmission Line Pulsing Testing

IEEE Electron Device Letters, 2011

ABSTRACT Passing voltage levels measured from the human metal model tester are correlated with th... more ABSTRACT Passing voltage levels measured from the human metal model tester are correlated with the failure current levels ob- tained from the transmission line pulsing (TLP) tester for electro- static discharge protection devices fabricated in 0.18- and 0.35-μm MOS technologies. Various relevant TLP parameters, including the holding voltage and ON-state resistance, are accounted for in the improved correlation formula developed in this study. Index Terms—Electrostatic discharge (ESD), human body model (HBM), human metal model (HMM), transmission line pulsing (TLP).

Research paper thumbnail of A novel dual-polarity device with symmetrical/asymmetrical S-type I-V characteristics for ESD protection design

IEEE Electron Device Letters, 2006

A novel and compact device with adjustable forward and reverse conductions and symmetrical/asymme... more A novel and compact device with adjustable forward and reverse conductions and symmetrical/asymmetrical I-V characteristics for ESD (electrostatic discharge) applications is presented. The device allows for the dual-polarity conduction with the proper selection of blocking junction configurations. This design enables high-level ESD protections for various mixed-signal integrated circuits operating under a wide range of symmetrical and asymmetrical bias conditions.

Research paper thumbnail of Device for Protecting High Frequency and High Data Rate Interface Applications in FinFET Process Technologies

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Research paper thumbnail of SCR device for ESD protection in sub-micron triple well silicided CMOS processes

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004.

Abstract A high-holding-low-trigger-voltage-silicon-controlled-rectifier (HHLVTSCR) is fabricated... more Abstract A high-holding-low-trigger-voltage-silicon-controlled-rectifier (HHLVTSCR) is fabricated in a sub-micron triple well CMOS technology in complementary nand p-types. The HHLVTSCRs occupy less area than typical electrostatic discharge (ESD) protection ...

Research paper thumbnail of Integrating Solid State Protection with a RF-MEMS Switch for Achieving ESD Robustness

2019 IEEE 69th Electronic Components and Technology Conference (ECTC)

The RF-MEMS (MicroElectroMechanical System) switch brings together the benefit of 0 Hz/DC precisi... more The RF-MEMS (MicroElectroMechanical System) switch brings together the benefit of 0 Hz/DC precision and wideband RF performance in a small, surface-mountable form factor. The ESD (Electrostatic Discharge) sensitivity of this device can be a barrier for the adoption of RF-MEMS switches in certain applications, as sensitivity of this type of device to damage during assembly and end-application handling can be pervasive. This paper addresses this limitation in RF-MEMS applications, while preserving the benefits of the RF-MEMS performance, by integrating in a SIP (system-in-a-package) optimized RF solid-state ESD protection elements along with the RF switch. This is demonstrated with a device achieving insertion loss of -0.5 dB at 6 GHz with a -3 dB bandwidth of up to 13 GHz. Isolation performance of -20 dB is also demonstrated at 6 GHz. The integrated RF-MEMS SIP achieves industry leading ESD compliance levels of 3,000V HBM (Human Body Model) and 1,250V FICDM (Field-Induced Charged Device Model).

Research paper thumbnail of Electrostatic Discharge Protection Device for Digital Circuits and for Applications with Input / Output Bipolar Voltage Much Higher than the Core Circuit Power Supply 10-23-2007

Research paper thumbnail of Electrostatic Discharge Protection Device for Digital Circuits and for Applications with Input/Output Bipolar Voltage Much Higher than the Core Circuit Power Supply

I lllll llllllll Il l lllll lllll lllll lllll lllll 111111111111111111111111111111111 c12) United... more I lllll llllllll Il l lllll lllll lllll lllll lllll 111111111111111111111111111111111 c12) United States Patent Salcedo et al.

Research paper thumbnail of A Novel Product-Level Human Metal Model Characterization Methodology

IEEE Transactions on Device and Materials Reliability

ABSTRACT A new methodology for characterizing product-level failures due to the human metal model... more ABSTRACT A new methodology for characterizing product-level failures due to the human metal model (HMM) stress is proposed and developed. This characterization framework is superior to the conventional leakage current-based approach, and it enables early wafer-level assessment of integrated circuits' HMM robustness. The new method is demonstrated in two amplifiers and is benchmarked versus the conventional leakage current method and the industry standard system-level IEC gun testing.

Research paper thumbnail of Novel structure embedded with dual-diodes and silicon controlled rectifier for high speed I/O applications

2016 IEEE International Nanoelectronics Conference (INEC), 2016

Design trade-offs of a novel structure embedded with a silicon controlled rectifier and dual-diod... more Design trade-offs of a novel structure embedded with a silicon controlled rectifier and dual-diode (DD-SCR) for high speed I/O applications are presented. A metal-bounded DD-SCR exhibiting a high failure current (It2), small on-state resistance (Ron), low voltage overshoot and low parasitic capacitance is introduced as an optimal device for such applications in advanced CMOS processes. Comprehensive characterizations including capacitance and current vs. voltage measured using transmission line pulsing (TLP) and very-fast TLP (VFTLP) are undertaken to demonstrate the DD-SCR performance.

Research paper thumbnail of Investigation of forward transient characteristics of vertical GaN-on-GaN p-n diodes

2016 IEEE International Nanoelectronics Conference (INEC), 2016

Transient characteristics of vertical GaN diodes fabricated on bulk GaN substrates are investigat... more Transient characteristics of vertical GaN diodes fabricated on bulk GaN substrates are investigated. When forward biasing the diodes using discrete pulses, the results yield quasi-static I-V curves with two different on-resistances and two turn-on stages. Transient waveforms measured at different voltages are then used to explain the observed behavior and underlying physics. A relatively large overshoot voltage is also observed at the very beginning of the transient voltage waveform, indicating that a relatively long time is required to transition the GaN diode from the high to low resistance state.

Research paper thumbnail of A sinh resistor and its application to tanh linearization

IEEE Journal of Solid-State Circuits, 2005

We present a novel and simple subthreshold tunable resistor (sinh) which exhibits a sinh-characte... more We present a novel and simple subthreshold tunable resistor (sinh) which exhibits a sinh-characteristic. This compact 8-transistor circuit generates an output current that is proportional to the sinh of its input differential voltage and has an offset-free characteristic, i.e., zero current at zero differential voltage, like a real resistor. In a 1.5-m CMOS chip implementation, we achieved a common-mode rejection ratio (CMRR) of 46 dB. As an example application, we use the expansive properties of our sinh to linearize the compressive properties of a tanh differential pair by degeneration and cancel all nonlinearities up to fifth order. We demonstrate good agreement between theory and experimental results.

Research paper thumbnail of On-chip electrostatic discharge protection for CMOS gas sensor systems-on-a-chip (SoC)

Microelectronics Reliability, 2006

An on-chip electrostatic discharge (ESD) protection scheme is demonstrated for an emerging techno... more An on-chip electrostatic discharge (ESD) protection scheme is demonstrated for an emerging technology of microelectromechanical systems (MEMS)-based embedded sensor (ES) system-on-a-chip (SoC). The ESD protection scheme is implemented using ground-...

Research paper thumbnail of TCAD Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications

IEEE Transactions on Electron Devices, 2007

Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical expe... more Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical experience and know-how. A technology computer-aided design (TCAD) methodology aimed to assist in the design and implementation of robust ESD devices is developed and presented. The methodology provides a systematic and practical means for the evaluation and optimization of ESD devices in a simulation environment. Advanced siliconcontrolled-rectifier devices are considered to illustrate the approach, and experimental data measured from these devices are also included in support of the TCAD development.

Research paper thumbnail of Analysis of Safe Operating Area of NLDMOS and PLDMOS Transistors Subject to Transient Stresses

IEEE Transactions on Electron Devices, 2010

Transient safe operating area (TSOA) of n-type and p-type laterally diffused metal-oxide-semicond... more Transient safe operating area (TSOA) of n-type and p-type laterally diffused metal-oxide-semiconductor (LDMOS) subject to transient stresses is presented for electrostatic discharge applications. LDMOS devices connected in the gate-grounded and gate-biased configurations are stressed with 1-, 2-, 5-, 10-, and 100-ns duration transmission line pulses, and a methodology to develop an effective and accurate TSOA based on these measurements is discussed. Two-dimensional technology computer-aided design simulations are also used to discuss critical physical mechanisms governing the current conduction during the transients and the condition that finally leads to device failure beyond the TSOA. Index Terms-Laterally diffused metal-oxide-semiconductor (LDMOS), transient safe operating area (TSOA), transmission line pulsing (TLP), very fast transmission line pulse (VFTLP).

Research paper thumbnail of Prediction and Modeling of Thin Gate Oxide Breakdown Subject to Arbitrary Transient Stresses

IEEE Transactions on Electron Devices, 2010

A reliable dielectric breakdown model under transient stresses via an extension of the power law ... more A reliable dielectric breakdown model under transient stresses via an extension of the power law is demonstrated. The model, which is based on the percolation model and the assumption of no significant detrapping, is successfully used in ramped voltage stress breakdown analysis. A demonstration of the model's validity consists of applying repetitive time-variant voltage waveforms-pulses, sine waves, ramps, and noise-until breakdown and, consequently, comparing prediction to reality. The breakdown distribution is initially derived from DC measurements, with the model predicting both the center and the shape of the distribution. Index Terms-Charged device model (CDM), gate oxide breakdown (GOB), power law (PL), time-dependent dielectric breakdown (TDDB), very fast transmission line pulse (VFTLP).

Research paper thumbnail of Comments on “A sinh Resistor and Its Application to tanh Linearization&#8221

IEEE Journal of Solid-State Circuits, 2006

Research paper thumbnail of ESD Protection Device With Dual-Polarity Conduction and High Blocking Voltage Realized in CMOS Process

IEEE Electron Device Letters, 2014

Electrostatic discharge (ESD) protection devices fabricated in a low-voltage CMOS process for com... more Electrostatic discharge (ESD) protection devices fabricated in a low-voltage CMOS process for communication interface applications typically provide relatively small blocking voltage, thus limiting the interface operating voltage range for which the ESD device can be used. This letter introduces a CMOS-based silicon controlled rectifier with a large blocking voltage beyond ±20 V and a high trigger current. Such a high blocking voltage is achieved by selectively defining native-buffer regions in critical blocking junctions of the device. Experimental characterization of the ESD robustness and standing operation are presented to validate the new device for low capacitance, high-voltage-tolerant communication interface ESD protection applications.

Research paper thumbnail of Bidirectional Devices for Automotive-Grade Electrostatic Discharge Applications

IEEE Electron Device Letters, 2012

ABSTRACT High bidirectional holding-voltage clamps are introduced for applications operating in h... more ABSTRACT High bidirectional holding-voltage clamps are introduced for applications operating in harsh environments. The clamps' terminals are formed with complementary doped 3-D "T" pattern and island active regions. Transmission-line-pulsed current in the ranges of ±0.15 and ±0.39 mA/μm2 is demonstrated for ±40- and ±25-V holding-voltage clamps, respectively. The high bidirectional holding voltage is optimized without increasing spacing between the terminals of the devices, achieving a compact clamp architecture successfully codesigned with advanced transceiver circuits.

Research paper thumbnail of High-Robustness and Low-Capacitance Silicon-Controlled Rectifier for High-Speed I/O ESD Protection

IEEE Electron Device Letters, 2013

ABSTRACT A high-robustness and low-capacitance clamp for on-chip electrostatic discharge (ESD) pr... more ABSTRACT A high-robustness and low-capacitance clamp for on-chip electrostatic discharge (ESD) protection is developed. The low capacitance is obtained by mitigating the capacitance associated with the lightly doped n-well/p-well junction. In addition to minimizing the capacitance, the high ESD robustness is achieved by optimizing independently within the same structure a silicon-controlled rectifier and a diode for the forward and reverse conduction processes, respectively. The new clamp with an area of 50 × 10 μm2 is able to handle an ESD current in excess of 1.5 A, whereas the capacitance at zero bias is kept at 94 fF.

Research paper thumbnail of Snapback and Postsnapback Saturation of Pseudomorphic High-Electron Mobility Transistor Subject to Transient Overstress

IEEE Electron Device Letters, 2010

The snapback and postsnapback saturation characteristics in a pseudomorphic high-electron mobilit... more The snapback and postsnapback saturation characteristics in a pseudomorphic high-electron mobility transistor (PHEMT) subject to electrostatic discharge (ESD) transient overstress are studied. This is undertaken, for the first time, via transmission line pulsing (TLP)-like 2-D device simulations and benchmarked against TLP measurements. Physical mechanisms underlying the postsnapback behavior and ESD-induced failure are identified and discussed by analyzing TLP-like simulation results rather than extrapolating dc-like numerical simulation data.

Research paper thumbnail of Correlation of Human Metal Model and Transmission Line Pulsing Testing

IEEE Electron Device Letters, 2011

ABSTRACT Passing voltage levels measured from the human metal model tester are correlated with th... more ABSTRACT Passing voltage levels measured from the human metal model tester are correlated with the failure current levels ob- tained from the transmission line pulsing (TLP) tester for electro- static discharge protection devices fabricated in 0.18- and 0.35-μm MOS technologies. Various relevant TLP parameters, including the holding voltage and ON-state resistance, are accounted for in the improved correlation formula developed in this study. Index Terms—Electrostatic discharge (ESD), human body model (HBM), human metal model (HMM), transmission line pulsing (TLP).

Research paper thumbnail of A novel dual-polarity device with symmetrical/asymmetrical S-type I-V characteristics for ESD protection design

IEEE Electron Device Letters, 2006

A novel and compact device with adjustable forward and reverse conductions and symmetrical/asymme... more A novel and compact device with adjustable forward and reverse conductions and symmetrical/asymmetrical I-V characteristics for ESD (electrostatic discharge) applications is presented. The device allows for the dual-polarity conduction with the proper selection of blocking junction configurations. This design enables high-level ESD protections for various mixed-signal integrated circuits operating under a wide range of symmetrical and asymmetrical bias conditions.

Research paper thumbnail of Device for Protecting High Frequency and High Data Rate Interface Applications in FinFET Process Technologies

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Research paper thumbnail of SCR device for ESD protection in sub-micron triple well silicided CMOS processes

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004.

Abstract A high-holding-low-trigger-voltage-silicon-controlled-rectifier (HHLVTSCR) is fabricated... more Abstract A high-holding-low-trigger-voltage-silicon-controlled-rectifier (HHLVTSCR) is fabricated in a sub-micron triple well CMOS technology in complementary nand p-types. The HHLVTSCRs occupy less area than typical electrostatic discharge (ESD) protection ...

Research paper thumbnail of Integrating Solid State Protection with a RF-MEMS Switch for Achieving ESD Robustness

2019 IEEE 69th Electronic Components and Technology Conference (ECTC)

The RF-MEMS (MicroElectroMechanical System) switch brings together the benefit of 0 Hz/DC precisi... more The RF-MEMS (MicroElectroMechanical System) switch brings together the benefit of 0 Hz/DC precision and wideband RF performance in a small, surface-mountable form factor. The ESD (Electrostatic Discharge) sensitivity of this device can be a barrier for the adoption of RF-MEMS switches in certain applications, as sensitivity of this type of device to damage during assembly and end-application handling can be pervasive. This paper addresses this limitation in RF-MEMS applications, while preserving the benefits of the RF-MEMS performance, by integrating in a SIP (system-in-a-package) optimized RF solid-state ESD protection elements along with the RF switch. This is demonstrated with a device achieving insertion loss of -0.5 dB at 6 GHz with a -3 dB bandwidth of up to 13 GHz. Isolation performance of -20 dB is also demonstrated at 6 GHz. The integrated RF-MEMS SIP achieves industry leading ESD compliance levels of 3,000V HBM (Human Body Model) and 1,250V FICDM (Field-Induced Charged Device Model).

Research paper thumbnail of Electrostatic Discharge Protection Device for Digital Circuits and for Applications with Input / Output Bipolar Voltage Much Higher than the Core Circuit Power Supply 10-23-2007

Research paper thumbnail of Electrostatic Discharge Protection Device for Digital Circuits and for Applications with Input/Output Bipolar Voltage Much Higher than the Core Circuit Power Supply

I lllll llllllll Il l lllll lllll lllll lllll lllll 111111111111111111111111111111111 c12) United... more I lllll llllllll Il l lllll lllll lllll lllll lllll 111111111111111111111111111111111 c12) United States Patent Salcedo et al.

Research paper thumbnail of A Novel Product-Level Human Metal Model Characterization Methodology

IEEE Transactions on Device and Materials Reliability

ABSTRACT A new methodology for characterizing product-level failures due to the human metal model... more ABSTRACT A new methodology for characterizing product-level failures due to the human metal model (HMM) stress is proposed and developed. This characterization framework is superior to the conventional leakage current-based approach, and it enables early wafer-level assessment of integrated circuits' HMM robustness. The new method is demonstrated in two amplifiers and is benchmarked versus the conventional leakage current method and the industry standard system-level IEC gun testing.

Research paper thumbnail of Novel structure embedded with dual-diodes and silicon controlled rectifier for high speed I/O applications

2016 IEEE International Nanoelectronics Conference (INEC), 2016

Design trade-offs of a novel structure embedded with a silicon controlled rectifier and dual-diod... more Design trade-offs of a novel structure embedded with a silicon controlled rectifier and dual-diode (DD-SCR) for high speed I/O applications are presented. A metal-bounded DD-SCR exhibiting a high failure current (It2), small on-state resistance (Ron), low voltage overshoot and low parasitic capacitance is introduced as an optimal device for such applications in advanced CMOS processes. Comprehensive characterizations including capacitance and current vs. voltage measured using transmission line pulsing (TLP) and very-fast TLP (VFTLP) are undertaken to demonstrate the DD-SCR performance.

Research paper thumbnail of Investigation of forward transient characteristics of vertical GaN-on-GaN p-n diodes

2016 IEEE International Nanoelectronics Conference (INEC), 2016

Transient characteristics of vertical GaN diodes fabricated on bulk GaN substrates are investigat... more Transient characteristics of vertical GaN diodes fabricated on bulk GaN substrates are investigated. When forward biasing the diodes using discrete pulses, the results yield quasi-static I-V curves with two different on-resistances and two turn-on stages. Transient waveforms measured at different voltages are then used to explain the observed behavior and underlying physics. A relatively large overshoot voltage is also observed at the very beginning of the transient voltage waveform, indicating that a relatively long time is required to transition the GaN diode from the high to low resistance state.