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Papers by Jean-François Naviner

Research paper thumbnail of A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems

Journal of Low Power Electronics, 2012

ABSTRACT In this paper, we propose a methodology for simultaneously analyzing the ageing effects ... more ABSTRACT In this paper, we propose a methodology for simultaneously analyzing the ageing effects and process variations. Nominal ageing simulation and statistical methods are applied to reliability simulation of AMS integrated circuits and systems. Response surface modeling (RSM) is used to build direct relationship between process parameters and circuit/system performances. With Varied/fixed RSMs, designers can have reliability information of designed circuit/system. Also, this methodology has been developed with behavioral modeling for reliability consideration of large AMS circuits and systems (e.g., modulator, RF front-end). Conventional Monte-Carlo (MC) method is infeasible in these complex circuits and systems. The methodology is validated with a series of circuits and systems in 65 nm CMOS technology: simple current mirrors, a dynamic comparator and a 2nd order continuous-time analog-to-digital modulator. It is shown that this methodology can provide designers with reliability information graphically with a general perspective. It can achieve better simulation efficiency than traditional Monte-Carlo analysis, while still guaranteeing good simulation accuracy.

Research paper thumbnail of Decimation filter cascade for channel selection in multistandard receivers

2003 46th Midwest Symposium on Circuits and Systems, 2003

ABSTRACT

Research paper thumbnail of Reliability analysis of combinational circuits with the influences of noise and single-event transients

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2013

ABSTRACT Noise-immunity is an important design criterion with CMOS dimension scaling to nanometer... more ABSTRACT Noise-immunity is an important design criterion with CMOS dimension scaling to nanometers. Furthermore, nanometer circuits devices are also more prone to soft errors induced by single event transients (SETs). In this work, we set up a model to analyze the reliability induced by both SETs and noise. We derive the constraints for the reliability enhancement of logic circuits for allowing design circuits with both better noise-immunity and higher tolerance to soft errors. Simulation combining Hspice and Matlab are given to verify the proposed constraints.

Research paper thumbnail of A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology

Research paper thumbnail of A hybrid reliability assessment method and its support of sequential logic modelling

2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014

ABSTRACT This paper proposes a modified hybrid method for the reliability assessment of digital c... more ABSTRACT This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.

Research paper thumbnail of Single event transient mitigation through pulse quenching: Effectiveness at circuit level

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), 2013

ABSTRACT This paper exploits the pulse quenching effect in order to reduce circuit error rates du... more ABSTRACT This paper exploits the pulse quenching effect in order to reduce circuit error rates due to single event transients in combinational logic. Although the effect allows for substantial reduction in the sensitive area of a single cell, logical masking at circuit level has to be also considered. Our results show that pulse quenching has a limited effectiveness at circuit level. The results of the proposed approach can be used to drive a reliability-aware design flow.

Research paper thumbnail of Selective hardening against multiple faults employing a net-based reliability analysis

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013

ABSTRACT This paper proposes a methodology for selective hardening combinational cells in digital... more ABSTRACT This paper proposes a methodology for selective hardening combinational cells in digital circuits. Such analysis is performed by taking into account multiple faults induced by single event effects (charge sharing). Hardening costs and proximity biasing are also taken into account when choosing the cells selectively. The methodology is applied to a set of benchmark circuits and the results show a cost-effective improved reliability.

Research paper thumbnail of Automatic selective hardening against soft errors: A cost-based and regularity-aware approach

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012

ABSTRACT This paper proposes a methodology to automatically apply selective hardening into a circ... more ABSTRACT This paper proposes a methodology to automatically apply selective hardening into a circuit based on the net hardening concept. Analysis is performed in the profile of a hardening cost function, in order to automatically determine a stop point for the hardening process. Such analysis can be, sometimes, very time consuming, and even intractable for large circuits. In order to overcome such limitation, two approaches are presented and combined in this paper. The first one takes advantage of circuit regularity, while the second limits the scope of the analysis. A set of circuits from the ISCAS85 benchmarks is used as case study. Simulation results demonstrate the effectiveness of the proposed methodology, where substantial reductions of the required computation time are achieved.

Research paper thumbnail of Trade-off between antialiasing filter and analog-to-digital converters specifications in homodyne radio frequency receivers

IEEE 54th Vehicular Technology Conference. VTC Fall 2001. Proceedings (Cat. No.01CH37211), 2001

... 1998. [2] K. Boo-Huat Khoo, Programmable, High Dynclmic Range Sigma-Delta A/D Converter for M... more ... 1998. [2] K. Boo-Huat Khoo, Programmable, High Dynclmic Range Sigma-Delta A/D Converter for Multistandczrd Fully-Integrated CMOS RF Receiver, Master Thesis University of California at Berkeley. December 1998. ... [4] Jacky Porte, OCEANE (Outil pour la Conception et I ...

Research paper thumbnail of A track&hold-mixer for direct-conversion by subsampling

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999

ABSTRACT

Research paper thumbnail of Convertisseur analogique numérique basé sur la modulation sigma delta en combinaison avec l'entrelacement temporel

Research paper thumbnail of A switched-current sample and hold circuit for low frequency applications

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001

Abstract: A Sample and Hold circuit using the 0.6 pm technology for low frequency application is ... more Abstract: A Sample and Hold circuit using the 0.6 pm technology for low frequency application is presented. This circuit is based on a specific memory base cell that reduces the error caused by the output conductance. It works with a 3.3 V supply voltage, offers high-resolution and ...

Research paper thumbnail of From RF Specifications to Base Band Requirements for RF Receivers : The UMTS Standard Example

Research paper thumbnail of Trade-off Between Antialiasing Filter and ADC Specifications in Homodyne RF Receivers

Research paper thumbnail of Linearity specifications of antialiasing filters for homodyne radio receivers

Research paper thumbnail of A linear p-n Junction-Based Integrated Transducer

Research paper thumbnail of Reliability Analysis Based on Significance Reliability Analysis Based on Significance

Due to the expected increase of defects and errors in circuits based on deep submicron technologi... more Due to the expected increase of defects and errors in circuits based on deep submicron technologies, reliability has become an important design criterion. As reliability improvement is generally achieved by adding redundancy, identify and classify critical blocks of a circuit is a major concern. This work presents two new classification methods regarding the significance of a block with respect to the reliability of a circuit. One gives the criticality of each block for the circuit reliability and the other indicates which priority should be given to each block in a process of adding redundancy. Thus, the proposed methods provide key information for the designer who is looking for efficient solutions of reliability monitoring or reliability improvement. Keywords-Reliability Analysis, Sensitivity, Eligibility, Reliabil- ity Monitoring, Reliability Improvement.

Research paper thumbnail of An approach for efficient reliability improvement of digital circuits

Reliability analysis is expected to play a major role for the design process of nanoscale systems... more Reliability analysis is expected to play a major role for the design process of nanoscale systems. Having that in mind, we proposed a method for reliability evaluation, named effective reliability, that can tolerate errors based on a pertinent quality metric. In order to demonstrate the impact of the proposed approach, we designed an 8-bit ripple carry adder using reliability as a constraint. The resulting design had shown a significant saving in circuit area.

Research paper thumbnail of Selective Hardening Methodology Concerning Multiple Faults

Research paper thumbnail of A New Fault Generator Suitable for Reliability Analysis of Digital Circuits

This paper deals with fault injection issues for reliability analysis. We propose a fault generat... more This paper deals with fault injection issues for reliability analysis. We propose a fault generator IP suitable for hardware emulation of single and multiple simultaneous faults occurrence. The proposed IP is based on a very useful approach that allows the designer to control complexity and completeness of the fault injection process. We provide models for cost and performance estimation of the IP. Also, synthesis results of its implementation on FPGA are given.

Research paper thumbnail of A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems

Journal of Low Power Electronics, 2012

ABSTRACT In this paper, we propose a methodology for simultaneously analyzing the ageing effects ... more ABSTRACT In this paper, we propose a methodology for simultaneously analyzing the ageing effects and process variations. Nominal ageing simulation and statistical methods are applied to reliability simulation of AMS integrated circuits and systems. Response surface modeling (RSM) is used to build direct relationship between process parameters and circuit/system performances. With Varied/fixed RSMs, designers can have reliability information of designed circuit/system. Also, this methodology has been developed with behavioral modeling for reliability consideration of large AMS circuits and systems (e.g., modulator, RF front-end). Conventional Monte-Carlo (MC) method is infeasible in these complex circuits and systems. The methodology is validated with a series of circuits and systems in 65 nm CMOS technology: simple current mirrors, a dynamic comparator and a 2nd order continuous-time analog-to-digital modulator. It is shown that this methodology can provide designers with reliability information graphically with a general perspective. It can achieve better simulation efficiency than traditional Monte-Carlo analysis, while still guaranteeing good simulation accuracy.

Research paper thumbnail of Decimation filter cascade for channel selection in multistandard receivers

2003 46th Midwest Symposium on Circuits and Systems, 2003

ABSTRACT

Research paper thumbnail of Reliability analysis of combinational circuits with the influences of noise and single-event transients

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2013

ABSTRACT Noise-immunity is an important design criterion with CMOS dimension scaling to nanometer... more ABSTRACT Noise-immunity is an important design criterion with CMOS dimension scaling to nanometers. Furthermore, nanometer circuits devices are also more prone to soft errors induced by single event transients (SETs). In this work, we set up a model to analyze the reliability induced by both SETs and noise. We derive the constraints for the reliability enhancement of logic circuits for allowing design circuits with both better noise-immunity and higher tolerance to soft errors. Simulation combining Hspice and Matlab are given to verify the proposed constraints.

Research paper thumbnail of A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology

Research paper thumbnail of A hybrid reliability assessment method and its support of sequential logic modelling

2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014

ABSTRACT This paper proposes a modified hybrid method for the reliability assessment of digital c... more ABSTRACT This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.

Research paper thumbnail of Single event transient mitigation through pulse quenching: Effectiveness at circuit level

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), 2013

ABSTRACT This paper exploits the pulse quenching effect in order to reduce circuit error rates du... more ABSTRACT This paper exploits the pulse quenching effect in order to reduce circuit error rates due to single event transients in combinational logic. Although the effect allows for substantial reduction in the sensitive area of a single cell, logical masking at circuit level has to be also considered. Our results show that pulse quenching has a limited effectiveness at circuit level. The results of the proposed approach can be used to drive a reliability-aware design flow.

Research paper thumbnail of Selective hardening against multiple faults employing a net-based reliability analysis

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013

ABSTRACT This paper proposes a methodology for selective hardening combinational cells in digital... more ABSTRACT This paper proposes a methodology for selective hardening combinational cells in digital circuits. Such analysis is performed by taking into account multiple faults induced by single event effects (charge sharing). Hardening costs and proximity biasing are also taken into account when choosing the cells selectively. The methodology is applied to a set of benchmark circuits and the results show a cost-effective improved reliability.

Research paper thumbnail of Automatic selective hardening against soft errors: A cost-based and regularity-aware approach

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012

ABSTRACT This paper proposes a methodology to automatically apply selective hardening into a circ... more ABSTRACT This paper proposes a methodology to automatically apply selective hardening into a circuit based on the net hardening concept. Analysis is performed in the profile of a hardening cost function, in order to automatically determine a stop point for the hardening process. Such analysis can be, sometimes, very time consuming, and even intractable for large circuits. In order to overcome such limitation, two approaches are presented and combined in this paper. The first one takes advantage of circuit regularity, while the second limits the scope of the analysis. A set of circuits from the ISCAS85 benchmarks is used as case study. Simulation results demonstrate the effectiveness of the proposed methodology, where substantial reductions of the required computation time are achieved.

Research paper thumbnail of Trade-off between antialiasing filter and analog-to-digital converters specifications in homodyne radio frequency receivers

IEEE 54th Vehicular Technology Conference. VTC Fall 2001. Proceedings (Cat. No.01CH37211), 2001

... 1998. [2] K. Boo-Huat Khoo, Programmable, High Dynclmic Range Sigma-Delta A/D Converter for M... more ... 1998. [2] K. Boo-Huat Khoo, Programmable, High Dynclmic Range Sigma-Delta A/D Converter for Multistandczrd Fully-Integrated CMOS RF Receiver, Master Thesis University of California at Berkeley. December 1998. ... [4] Jacky Porte, OCEANE (Outil pour la Conception et I ...

Research paper thumbnail of A track&hold-mixer for direct-conversion by subsampling

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999

ABSTRACT

Research paper thumbnail of Convertisseur analogique numérique basé sur la modulation sigma delta en combinaison avec l'entrelacement temporel

Research paper thumbnail of A switched-current sample and hold circuit for low frequency applications

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001

Abstract: A Sample and Hold circuit using the 0.6 pm technology for low frequency application is ... more Abstract: A Sample and Hold circuit using the 0.6 pm technology for low frequency application is presented. This circuit is based on a specific memory base cell that reduces the error caused by the output conductance. It works with a 3.3 V supply voltage, offers high-resolution and ...

Research paper thumbnail of From RF Specifications to Base Band Requirements for RF Receivers : The UMTS Standard Example

Research paper thumbnail of Trade-off Between Antialiasing Filter and ADC Specifications in Homodyne RF Receivers

Research paper thumbnail of Linearity specifications of antialiasing filters for homodyne radio receivers

Research paper thumbnail of A linear p-n Junction-Based Integrated Transducer

Research paper thumbnail of Reliability Analysis Based on Significance Reliability Analysis Based on Significance

Due to the expected increase of defects and errors in circuits based on deep submicron technologi... more Due to the expected increase of defects and errors in circuits based on deep submicron technologies, reliability has become an important design criterion. As reliability improvement is generally achieved by adding redundancy, identify and classify critical blocks of a circuit is a major concern. This work presents two new classification methods regarding the significance of a block with respect to the reliability of a circuit. One gives the criticality of each block for the circuit reliability and the other indicates which priority should be given to each block in a process of adding redundancy. Thus, the proposed methods provide key information for the designer who is looking for efficient solutions of reliability monitoring or reliability improvement. Keywords-Reliability Analysis, Sensitivity, Eligibility, Reliabil- ity Monitoring, Reliability Improvement.

Research paper thumbnail of An approach for efficient reliability improvement of digital circuits

Reliability analysis is expected to play a major role for the design process of nanoscale systems... more Reliability analysis is expected to play a major role for the design process of nanoscale systems. Having that in mind, we proposed a method for reliability evaluation, named effective reliability, that can tolerate errors based on a pertinent quality metric. In order to demonstrate the impact of the proposed approach, we designed an 8-bit ripple carry adder using reliability as a constraint. The resulting design had shown a significant saving in circuit area.

Research paper thumbnail of Selective Hardening Methodology Concerning Multiple Faults

Research paper thumbnail of A New Fault Generator Suitable for Reliability Analysis of Digital Circuits

This paper deals with fault injection issues for reliability analysis. We propose a fault generat... more This paper deals with fault injection issues for reliability analysis. We propose a fault generator IP suitable for hardware emulation of single and multiple simultaneous faults occurrence. The proposed IP is based on a very useful approach that allows the designer to control complexity and completeness of the fault injection process. We provide models for cost and performance estimation of the IP. Also, synthesis results of its implementation on FPGA are given.