Jinian Bian - Academia.edu (original) (raw)

Papers by Jinian Bian

Research paper thumbnail of The PMS modeling method based on interactive Markov chain

The Proceedings of 2011 9th International Conference on Reliability, Maintainability and Safety, 2011

... [9] L. Xing, JB Dugan, “A Separable Ternary Decision Diagram Based Analysis of Generalized Ph... more ... [9] L. Xing, JB Dugan, “A Separable Ternary Decision Diagram Based Analysis of Generalized Phased-Mission Reliability,” IEEE Trans. on Reliability, vol. 53, no. 2, pp. 174-184, 2004. [10] Boudali Hichem, Crouzen Pepijn, Stoelinga Marielle, “Dynamic Fault Tree analysis using ...

Research paper thumbnail of An efficient tableau for reasoning over general linear time

Research paper thumbnail of Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow

ACM Transactions on Reconfigurable Technology and Systems

Dynamic Partially Reconfiguration (DPR) on FPGA has attracted significant research interest in re... more Dynamic Partially Reconfiguration (DPR) on FPGA has attracted significant research interest in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in the current DPR design flow, leveraging benefits from DPR requires specific design expertise with laborious manual design effort. Considering the complicated concurrency relations among various functions, it is challenging to select appropriate Partial Reconfiguration Modules (PR Modules) and cluster them into proper groups with a proper reconfiguration schedule so that the hardware modules can be swapped in and out correctly during the run time. Furthermore, the design of PR Modules also impacts reconfiguration latency and resource utilization greatly. In this paper, we propose a Maximum-Weight Independent Set model to formulate the PR Module selection and clustering problem so that the original manual exploration can be solved efficiently and ...

Research paper thumbnail of EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure

2007 44th ACM/IEEE Design Automation Conference, 2007

This paper presents an efficient algorithm to solve the satisfiability (SAT) problem for RTL desi... more This paper presents an efficient algorithm to solve the satisfiability (SAT) problem for RTL designs using a complete hybrid branch-and-bound strategy with conflict-driven learning. The main framework is the extended Davis-Putnam-Logemann-Loveland procedure (DPLL) which is a unified procedure combining Boolean logic and arithmetic operations. A hybrid two- literal-watching scheme and interval reasoning based on RTL predicates are used as the

Research paper thumbnail of RAW Introduction

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, 2011

Research paper thumbnail of Hideharu Amano Keio University Jeff Arnold Stretch Peter Athanas Virginia Tech Juergen Becker University of Karlsruhe

Hideharu Amano Keio University Jeff Arnold Stretch Peter Athanas Virginia Tech Juergen Becker Uni... more Hideharu Amano Keio University Jeff Arnold Stretch Peter Athanas Virginia Tech Juergen Becker University of Karlsruhe Paul Beckett Royal Melbourne Institute of Technology Neil Bergmann University of Queensland Jinian Bian Tsinghua University Christophe Bobda University of Erlangen Katherine Compton University of Wisconsin-Madison George Constantinides Imperial College Andre DeHon California Institute of Technology Oliver Diessel University of New South Wales Apostolos Dollas Technical University of Crete Tarek El-Ghazawi George Washington ...

Research paper thumbnail of Markov clustering based placement algorithm for island-style FPGAs

The 2010 International Conference on Green Circuits and Systems, 2010

Previous divide-and-conquer methods including partition-based and cluster-based placement algorit... more Previous divide-and-conquer methods including partition-based and cluster-based placement algorithms have shown the effectiveness of good quality-runtime trade off. This paper proposes a new cluster-based FPGA placement algorithm called CAP, which is based on a Markov clustering algorithm that defines a sequence of stochastic matrices by operating on a generating matrix from the input FPGA circuit netlist. The core of the

Research paper thumbnail of Scheduling with Resource Allocation for System-Level Synthesis

Journal of Software, 2007

In system-level synthesis, the allocation of resources is always decided by the designer or explo... more In system-level synthesis, the allocation of resources is always decided by the designer or explored in the outer-most loop. In this paper, a heuristic scheduling algorithm is proposed to find the resource allocation during its running process. It determines the appropriate number of required resource instances based on the system partition in scheduling, and generates the corresponding resource allocation, scheduling and assignment solution. Such an algorithm can simplify the system-level design exploration to a procedure of system partitioning, scheduling and evaluation, and can improve the exploration efficiency. Experimental results show the feasibility and validity of the approach.

Research paper thumbnail of PFGASAR-a genetic SAT solver combining partitioning and fuzzy strategies

Proceedings of the 28th Annual International Computer Software and Applications Conference, 2004. COMPSAC 2004., 2000

ABSTRACT

Research paper thumbnail of Bounded Model Checking for RTL Circuits Based on Algorithm Abstraction Refinement

Research paper thumbnail of Assertion-based performance analysis for OCP systems

Google, Inc. (search). ...

Research paper thumbnail of RTSAT: A hybrid satisfiability solver for RTL circuits

Research paper thumbnail of VHdbx: an X window system based high-level debugger for the VHDL simulation environment

Proceedings of 4th International Conference on Solid-State and IC Technology, 1995

In this paper we present a graphica1 high-level debugger for the VaDL simulation environment. The... more In this paper we present a graphica1 high-level debugger for the VaDL simulation environment. The features of the tool are its user friendly interface based on Motif under X Window system, a capability to high-levei debugging, a capability to support many methods to set breakpoints, selective enabling and disabling of breakpoints, single stepping and trace mode, a capability to display source code, simulation results, and graphical views such as schematic diagram and design hierarchical diagram synchronically, a capabiliq to view the current values of signals or variables and change them, a capability of visualization of simulation results, and a capability to view the waveform of results while simdating.

Research paper thumbnail of Signal state and delay calculation in switch-level networks for mixed-level simulation

1991 International Conference on Circuits and Systems, 1991

ABSTRACT

Research paper thumbnail of Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving

Lecture Notes in Computer Science, 2007

ABSTRACT

Research paper thumbnail of Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving

2006 10th International Conference on Computer Supported Cooperative Work in Design, 2006

... the forward semantics for STE, which will be discussed in subsection 3.2, information is only... more ... the forward semantics for STE, which will be discussed in subsection 3.2, information is only propagated in a forward fashion in the hybrid three-valued ... as shown in Table 2, which means that when the output node of an RTL opera-tor changes, the values of the inputs won't be ...

Research paper thumbnail of Cooperation of SMV and Jeda for the property checking of mixed control and data intensive designs

Proceedings of the Ninth International Conference on Computer Supported Cooperative Work in Design, 2005., 2005

ABSTRACT

Research paper thumbnail of Power optimization in data-path scheduling and binding with multiple supply voltages and threshold voltages by simulated annealing

Proceedings. 2005 International Conference on Communications, Circuits and Systems, 2005., 2000

Abstract We present a scheme to optimize power consumption in data-path scheduling and binding wi... more Abstract We present a scheme to optimize power consumption in data-path scheduling and binding with resources operating at multiple supply voltages and threshold voltages by simulated annealing. The proposed scheme considers both scheduling and binding ...

Research paper thumbnail of Parameterized function unit library for methodology of integrating high level synthesis and floor plan

2006 7th International Conference on Computer-Aided Industrial Design and Conceptual Design, 2006

... China .Tel.010-62777924 Email: jian-zhang05@mails.tsinghua.edu.cn, bianjn@tsinghua.edu. cn, w... more ... China .Tel.010-62777924 Email: jian-zhang05@mails.tsinghua.edu.cn, bianjn@tsinghua.edu. cn, wangyf00@mails.tsinghua.edu.cn ... Xue Hongxi Merging High-Level Synthesis with Layout Design for SOC Design CAID&CD-2001, pp.??-? 2001 [11] Abhishek Ranjan, Kiarash ...

Research paper thumbnail of A debug sub-system for embedded-system co-verification

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549), 2000

ABSTRACT

Research paper thumbnail of The PMS modeling method based on interactive Markov chain

The Proceedings of 2011 9th International Conference on Reliability, Maintainability and Safety, 2011

... [9] L. Xing, JB Dugan, “A Separable Ternary Decision Diagram Based Analysis of Generalized Ph... more ... [9] L. Xing, JB Dugan, “A Separable Ternary Decision Diagram Based Analysis of Generalized Phased-Mission Reliability,” IEEE Trans. on Reliability, vol. 53, no. 2, pp. 174-184, 2004. [10] Boudali Hichem, Crouzen Pepijn, Stoelinga Marielle, “Dynamic Fault Tree analysis using ...

Research paper thumbnail of An efficient tableau for reasoning over general linear time

Research paper thumbnail of Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow

ACM Transactions on Reconfigurable Technology and Systems

Dynamic Partially Reconfiguration (DPR) on FPGA has attracted significant research interest in re... more Dynamic Partially Reconfiguration (DPR) on FPGA has attracted significant research interest in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in the current DPR design flow, leveraging benefits from DPR requires specific design expertise with laborious manual design effort. Considering the complicated concurrency relations among various functions, it is challenging to select appropriate Partial Reconfiguration Modules (PR Modules) and cluster them into proper groups with a proper reconfiguration schedule so that the hardware modules can be swapped in and out correctly during the run time. Furthermore, the design of PR Modules also impacts reconfiguration latency and resource utilization greatly. In this paper, we propose a Maximum-Weight Independent Set model to formulate the PR Module selection and clustering problem so that the original manual exploration can be solved efficiently and ...

Research paper thumbnail of EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure

2007 44th ACM/IEEE Design Automation Conference, 2007

This paper presents an efficient algorithm to solve the satisfiability (SAT) problem for RTL desi... more This paper presents an efficient algorithm to solve the satisfiability (SAT) problem for RTL designs using a complete hybrid branch-and-bound strategy with conflict-driven learning. The main framework is the extended Davis-Putnam-Logemann-Loveland procedure (DPLL) which is a unified procedure combining Boolean logic and arithmetic operations. A hybrid two- literal-watching scheme and interval reasoning based on RTL predicates are used as the

Research paper thumbnail of RAW Introduction

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, 2011

Research paper thumbnail of Hideharu Amano Keio University Jeff Arnold Stretch Peter Athanas Virginia Tech Juergen Becker University of Karlsruhe

Hideharu Amano Keio University Jeff Arnold Stretch Peter Athanas Virginia Tech Juergen Becker Uni... more Hideharu Amano Keio University Jeff Arnold Stretch Peter Athanas Virginia Tech Juergen Becker University of Karlsruhe Paul Beckett Royal Melbourne Institute of Technology Neil Bergmann University of Queensland Jinian Bian Tsinghua University Christophe Bobda University of Erlangen Katherine Compton University of Wisconsin-Madison George Constantinides Imperial College Andre DeHon California Institute of Technology Oliver Diessel University of New South Wales Apostolos Dollas Technical University of Crete Tarek El-Ghazawi George Washington ...

Research paper thumbnail of Markov clustering based placement algorithm for island-style FPGAs

The 2010 International Conference on Green Circuits and Systems, 2010

Previous divide-and-conquer methods including partition-based and cluster-based placement algorit... more Previous divide-and-conquer methods including partition-based and cluster-based placement algorithms have shown the effectiveness of good quality-runtime trade off. This paper proposes a new cluster-based FPGA placement algorithm called CAP, which is based on a Markov clustering algorithm that defines a sequence of stochastic matrices by operating on a generating matrix from the input FPGA circuit netlist. The core of the

Research paper thumbnail of Scheduling with Resource Allocation for System-Level Synthesis

Journal of Software, 2007

In system-level synthesis, the allocation of resources is always decided by the designer or explo... more In system-level synthesis, the allocation of resources is always decided by the designer or explored in the outer-most loop. In this paper, a heuristic scheduling algorithm is proposed to find the resource allocation during its running process. It determines the appropriate number of required resource instances based on the system partition in scheduling, and generates the corresponding resource allocation, scheduling and assignment solution. Such an algorithm can simplify the system-level design exploration to a procedure of system partitioning, scheduling and evaluation, and can improve the exploration efficiency. Experimental results show the feasibility and validity of the approach.

Research paper thumbnail of PFGASAR-a genetic SAT solver combining partitioning and fuzzy strategies

Proceedings of the 28th Annual International Computer Software and Applications Conference, 2004. COMPSAC 2004., 2000

ABSTRACT

Research paper thumbnail of Bounded Model Checking for RTL Circuits Based on Algorithm Abstraction Refinement

Research paper thumbnail of Assertion-based performance analysis for OCP systems

Google, Inc. (search). ...

Research paper thumbnail of RTSAT: A hybrid satisfiability solver for RTL circuits

Research paper thumbnail of VHdbx: an X window system based high-level debugger for the VHDL simulation environment

Proceedings of 4th International Conference on Solid-State and IC Technology, 1995

In this paper we present a graphica1 high-level debugger for the VaDL simulation environment. The... more In this paper we present a graphica1 high-level debugger for the VaDL simulation environment. The features of the tool are its user friendly interface based on Motif under X Window system, a capability to high-levei debugging, a capability to support many methods to set breakpoints, selective enabling and disabling of breakpoints, single stepping and trace mode, a capability to display source code, simulation results, and graphical views such as schematic diagram and design hierarchical diagram synchronically, a capabiliq to view the current values of signals or variables and change them, a capability of visualization of simulation results, and a capability to view the waveform of results while simdating.

Research paper thumbnail of Signal state and delay calculation in switch-level networks for mixed-level simulation

1991 International Conference on Circuits and Systems, 1991

ABSTRACT

Research paper thumbnail of Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving

Lecture Notes in Computer Science, 2007

ABSTRACT

Research paper thumbnail of Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving

2006 10th International Conference on Computer Supported Cooperative Work in Design, 2006

... the forward semantics for STE, which will be discussed in subsection 3.2, information is only... more ... the forward semantics for STE, which will be discussed in subsection 3.2, information is only propagated in a forward fashion in the hybrid three-valued ... as shown in Table 2, which means that when the output node of an RTL opera-tor changes, the values of the inputs won't be ...

Research paper thumbnail of Cooperation of SMV and Jeda for the property checking of mixed control and data intensive designs

Proceedings of the Ninth International Conference on Computer Supported Cooperative Work in Design, 2005., 2005

ABSTRACT

Research paper thumbnail of Power optimization in data-path scheduling and binding with multiple supply voltages and threshold voltages by simulated annealing

Proceedings. 2005 International Conference on Communications, Circuits and Systems, 2005., 2000

Abstract We present a scheme to optimize power consumption in data-path scheduling and binding wi... more Abstract We present a scheme to optimize power consumption in data-path scheduling and binding with resources operating at multiple supply voltages and threshold voltages by simulated annealing. The proposed scheme considers both scheduling and binding ...

Research paper thumbnail of Parameterized function unit library for methodology of integrating high level synthesis and floor plan

2006 7th International Conference on Computer-Aided Industrial Design and Conceptual Design, 2006

... China .Tel.010-62777924 Email: jian-zhang05@mails.tsinghua.edu.cn, bianjn@tsinghua.edu. cn, w... more ... China .Tel.010-62777924 Email: jian-zhang05@mails.tsinghua.edu.cn, bianjn@tsinghua.edu. cn, wangyf00@mails.tsinghua.edu.cn ... Xue Hongxi Merging High-Level Synthesis with Layout Design for SOC Design CAID&CD-2001, pp.??-? 2001 [11] Abhishek Ranjan, Kiarash ...

Research paper thumbnail of A debug sub-system for embedded-system co-verification

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549), 2000

ABSTRACT