Joe Louis-Chandran - Academia.edu (original) (raw)
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University of Electronic Science and Technology of China
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Papers by Joe Louis-Chandran
IEEE Journal of Solid-State Circuits, 1998
An 800-MB/s/pin byte-wide interface DRAM is described that meets the bandwidth requirements for m... more An 800-MB/s/pin byte-wide interface DRAM is described that meets the bandwidth requirements for modern microprocessor systems. Clock recovery and I/O circuitry perform to specification across multiple DRAM manufacturers' processes. The clock-recovery circuitry is described in depth for areas that are sensitive to power-supply noise. I/O circuitry for preserving signal integrity in high-speed bussed systems are described. Design methodology that enables rapid simulation and verification of the design in each fabrication process are discussed. Logic that enables interleaved transactions with concurrent operation is detailed. Computer-aided-design tools for large aspect merged logic/memory are discussed. Last, measured results are summarized showing clock jitter, setup and hold timing, and period versus V dd V dd V dd operation.
2011 12th International Conference on Electronic Packaging Technology and High Density Packaging, 2011
Abstract Interests in advancing 3D design and integration have stimulated this study of connectin... more Abstract Interests in advancing 3D design and integration have stimulated this study of connecting two different silicon dies using an organic interposer. This paper reports some of the challenges encountered by the system and silicon designers during the process of 3D ...
Conference Record Southcon, Mar 29, 1994
An important concern whether designing a new process or maintaining an existing one is the cost o... more An important concern whether designing a new process or maintaining an existing one is the cost of production and hence the chip yield. In order to maximize chip yield, the most significant process parameters need to be identified so that variations in these critical parameters can be minimized resulting in the highest possible chip yield. Presented in this paper is
2011 12th International Conference on Electronic Packaging Technology and High Density Packaging, 2011
Abstract Interests in advancing 3D design and integration have stimulated this study of connectin... more Abstract Interests in advancing 3D design and integration have stimulated this study of connecting two different silicon dies using an organic interposer. This paper reports some of the challenges encountered by the system and silicon designers during the process of 3D ...
IEEE Journal of Solid-State Circuits, 1998
An 800-MB/s/pin byte-wide interface DRAM is described that meets the bandwidth requirements for m... more An 800-MB/s/pin byte-wide interface DRAM is described that meets the bandwidth requirements for modern microprocessor systems. Clock recovery and I/O circuitry perform to specification across multiple DRAM manufacturers' processes. The clock-recovery circuitry is described in depth for areas that are sensitive to power-supply noise. I/O circuitry for preserving signal integrity in high-speed bussed systems are described. Design methodology that enables rapid simulation and verification of the design in each fabrication process are discussed. Logic that enables interleaved transactions with concurrent operation is detailed. Computer-aided-design tools for large aspect merged logic/memory are discussed. Last, measured results are summarized showing clock jitter, setup and hold timing, and period versus V dd V dd V dd operation.
2011 12th International Conference on Electronic Packaging Technology and High Density Packaging, 2011
Abstract Interests in advancing 3D design and integration have stimulated this study of connectin... more Abstract Interests in advancing 3D design and integration have stimulated this study of connecting two different silicon dies using an organic interposer. This paper reports some of the challenges encountered by the system and silicon designers during the process of 3D ...
Conference Record Southcon, Mar 29, 1994
An important concern whether designing a new process or maintaining an existing one is the cost o... more An important concern whether designing a new process or maintaining an existing one is the cost of production and hence the chip yield. In order to maximize chip yield, the most significant process parameters need to be identified so that variations in these critical parameters can be minimized resulting in the highest possible chip yield. Presented in this paper is
2011 12th International Conference on Electronic Packaging Technology and High Density Packaging, 2011
Abstract Interests in advancing 3D design and integration have stimulated this study of connectin... more Abstract Interests in advancing 3D design and integration have stimulated this study of connecting two different silicon dies using an organic interposer. This paper reports some of the challenges encountered by the system and silicon designers during the process of 3D ...