K. Eric Harper - Academia.edu (original) (raw)
Papers by K. Eric Harper
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arXiv (Cornell University), Feb 16, 2016
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arXiv (Cornell University), Jan 9, 2014
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arXiv (Cornell University), Jan 15, 2016
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Int. CMG Conference, 2008
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2015 12th Working IEEE/IFIP Conference on Software Architecture, 2015
Architecture description can be modeled as a set of alternative choices and decisions, where the ... more Architecture description can be modeled as a set of alternative choices and decisions, where the rationale and tradeoffs for each decision are documented and understood as needed to inform subsequent decisions. Each decision, based on ISO/IEC/IEEE 42010, pertains to one or more stakeholder concerns. These concerns combined with the system environment and scenarios provide architecture design context that clarifies the motivation for decisions. Subsequent authors have introduced the notion of an influencing decision force, using a many-to-many relationship with concern, to provide further context for decisions. For both concerns and forces it is left to the architect to identify the nature of this context. This paper proposes a systematic process for identifying and documenting design context in support of architectural decisions. For our work decision force is used as a central unifying aspect of the architecture framework metamodel. We extend the decision Forces Viewpoint to capture detailed design context descriptions, and add features for tagging the architecture description elements to facilitate identification of commonality, classification, and specialization. Initial feedback from industry stakeholders indicates this approach should be explored further.
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Proceedings of the 10th international ACM Sigsoft conference on Quality of software architectures - QoSA '14, 2014
Wide availability of multicore CPUs makes concurrency a critical design factor for the software a... more Wide availability of multicore CPUs makes concurrency a critical design factor for the software architecture and execution models of industrial controllers, especially with messages passing between tasks running on different cores. To improve performance, we refactored a standardized shared memory IPC mechanism implemented with traditional kernel locks to use lock-free algorithms. Prototyping the changes made it possible to determine the speed-up when the locks were removed, but we could neither easily confirm whether the IPC performance would suffice for the communication patterns in our real-time system, nor could we tell how well the implementation would scale to CPUs with more cores than our test machine. In this paper we report on our experience with using a queuing petri net performance model to predict the impact of memory contention in a multi-core CPU on architecture level performance. We instantiated our model with benchmark data and prototype measurements. The results from our model simulation provide valuable feedback for design decisions and point at potential bottlenecks. Comparison of the prototype's performance with our model simulation results increases credibility of our work. This paper supports other practitioners who consider applying performance modeling to quantify the quality of their architectures.
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2014 IEEE/IFIP Conference on Software Architecture, 2014
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2015 IEEE First International Conference on Big Data Computing Service and Applications, 2015
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2016 19th International ACM SIGSOFT Symposium on Component-Based Software Engineering (CBSE), 2016
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ArXiv, 2016
The Industrial Internet market is targeted to grow by trillions of US dollars by the year 2030, d... more The Industrial Internet market is targeted to grow by trillions of US dollars by the year 2030, driven by adoption, deployment and integration of billions of intelligent devices and their associated data. This digital expansion faces a number of significant challenges, including reliable data management, security and privacy. Realizing the benefits from this evolution is made more difficult because a typical industrial plant includes multiple vendors and legacy technology stacks. Aggregating all the raw data to a single data center before performing analysis increases response times, raising performance concerns in traditional markets and requiring a compromise between data duplication and data access performance. Similar to the way microservices can integrate disparate information technologies without imposing monolithic cross-cutting architecture impacts, we propose microdatabases to manage the data heterogeneity of the Industrial Internet while allowing records to be captured and...
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ArXiv, 2016
A single vendor cannot provide complete IIoT end-to-end solutions because cooperation is required... more A single vendor cannot provide complete IIoT end-to-end solutions because cooperation is required from multiple parties. Interoperability is a key architectural quality. Composability of capabilities, information and configuration is the prerequisite for interoperability, supported by a data storage infrastructure and defined set of interfaces to build applications. Secure collection, transport and storage of data and algorithms are expectations for collaborative participation in any IIoT solution. Participants require control of their data ownership and confidentiality. We propose an Internet of Things, Services and People (IoTSP) application development and management framework which includes components for data storage, algorithm design and packaging, and computation execution. Applications use clusters of platform services, organized in tiers, and local access to data to reduce complexity and enhance reliable data exchange. Since communication is less reliable across tiers, data...
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ArXiv, 2014
Data race conditions in multi-tasking software applications are prevented by serializing access t... more Data race conditions in multi-tasking software applications are prevented by serializing access to shared memory resources, ensuring data consistency and deterministic behavior. Traditionally tasks acquire and release locks to synchronize operations on shared memory. Unfortunately, lock management can add significant processing overhead especially for multicore deployments where tasks on different cores convoy in queues waiting to acquire a lock. Implementing more than one lock introduces the risk of deadlock and using spinlocks constrains which cores a task can run on. The better alternative is to eliminate locks and validate that real-time properties are met, which is not directly considered in many embedded applications. Removing the locks is non-trivial and packaging lock-free algorithms for developers reduces the possibility of concurrency defects. This paper details how a multicore communication API implementation is enhanced to support lock-free messaging and the impact this ...
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Cmg, 2008
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Wide availability of multicore CPUs makes concurrency a critical design factor for the software a... more Wide availability of multicore CPUs makes concurrency a
critical design factor for the software architecture and execution models of industrial controllers, especially with messages passing between tasks running on diff erent cores. To
improve performance, we refactored a standardized shared
memory IPC mechanism implemented with traditional kernel
locks to use lock-free algorithms. Prototyping the changes
made it possible to determine the speed-up when the locks
were removed, but we could neither easily con rm whether
the IPC performance would suffice for the communication
patterns in our real-time system, nor could we tell how well
the implementation would scale to CPUs with more cores
than our test machine. In this paper we report on our experience with using a queuing petri net performance model
to predict the impact of memory contention in a multi-core
CPU on architecture level performance. We instantiated our
model with benchmark data and prototype measurements.
The results from our model simulation provide valuable feedback for design decisions and point at potential bottlenecks. Comparison of the prototype's performance with our model simulation results increases credibility of our work. This paper supports other practitioners who consider applying
performance modeling to quantify the quality of their architectures.
Bookmarks Related papers MentionsView impact
Architecture description can be modeled as a set of alternative choices and decisions, where the ... more Architecture description can be modeled as a set of alternative choices and decisions, where the rationale and tradeoffs for each decision are documented and understood as needed to inform subsequent decisions. Each decision, based on ISO/IEC/IEEE 42010, pertains to one or more stakeholder concerns. These concerns combined with the system environment and scenarios provide architecture design context that clarifies the motivation for decisions. Subsequent authors have introduced the notion of an influencing decision force, using a many-to-many relationship with concern, to provide further context for decisions. For both concerns and forces it is left to the architect to identify the nature of this context. This paper proposes a systematic process for identifying and documenting design context in support of architectural decisions. For our work decision force is used as a central unifying aspect of the architecture framework metamodel. We extend the decision Forces Viewpoint to capture detailed design context descriptions, and add features for tagging the architecture description elements to facilitate identification of commonality, classification, and specialization. Initial feedback from industry stakeholders indicates this approach should be explored further.
Bookmarks Related papers MentionsView impact
Decreasing cost and increasing capabilities of instrumentation, networks and data repositories ha... more Decreasing cost and increasing capabilities of instrumentation, networks and data repositories have pervaded the industrial automation and power markets and opened the door for large scale collection and analysis of data. There are a variety of technology stacks that can be applied to these types of activities. However, no single infrastructure or architecture fits all the scenarios. With limited data science training and experience, it is difficult and time consuming for highly specialized domain experts to choose the optimal approach. In this paper, we introduce an architectural pattern for the design of a flexible core analytics platform which is extensible using different pipelines. The pipeline pattern provides an accelerated start to implementing industrial analytics applications. The platform enables domain experts to compose pipelines in series and in parallel at scale with the right quality attribute trade-offs to deliver significant business value. Our use of the proposed platform is illustrated with real-world industrial applications, which necessitate various data handling and processing capabilities. These examples show the importance of the platform to non-data experts: reducing the learning curve for applying data science, providing a systematic rating process for choosing the pipeline types, and lowering the barriers for industrial businesses to leverage analytics.
Bookmarks Related papers MentionsView impact
Data race conditions in multi-tasking software applications are prevented by serializing access t... more Data race conditions in multi-tasking software applications are prevented by serializing access to shared memory resources, ensuring data consistency and deterministic behavior. Traditionally tasks acquire and release locks to synchronize operations on shared memory. Unfortunately, lock management can add significant processing overhead especially for multicore deployments where tasks on different cores convoy in queues waiting to acquire a lock. Implementing more than one lock introduces the risk of deadlock and using spinlocks constrains which cores a task can run on. The better alternative is to eliminate locks and validate that real-time properties are met, which is not directly considered in many embedded applications. Removing the locks is non-trivial and packaging lock-free algorithms for developers reduces the possibility of concurrency defects. This paper details how a multicore communication API implementation is enhanced to support lock-free messaging and the impact this has on data exchange latency between tasks. Throughput and latency are compared on Windows and Linux between lock-based and lock-free implementations for data exchange of messages, packets, and scalars. A model of the lock-free exchange predicts performance at the system architecture level and provides a stop criterion for the refactoring. The results show that migration from single to multicore hardware architectures degrades lock-based performance, and increases lock-free performance.
Bookmarks Related papers MentionsView impact
Bookmarks Related papers MentionsView impact
arXiv (Cornell University), Feb 16, 2016
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arXiv (Cornell University), Jan 9, 2014
Bookmarks Related papers MentionsView impact
arXiv (Cornell University), Jan 15, 2016
Bookmarks Related papers MentionsView impact
Int. CMG Conference, 2008
Bookmarks Related papers MentionsView impact
Bookmarks Related papers MentionsView impact
2015 12th Working IEEE/IFIP Conference on Software Architecture, 2015
Architecture description can be modeled as a set of alternative choices and decisions, where the ... more Architecture description can be modeled as a set of alternative choices and decisions, where the rationale and tradeoffs for each decision are documented and understood as needed to inform subsequent decisions. Each decision, based on ISO/IEC/IEEE 42010, pertains to one or more stakeholder concerns. These concerns combined with the system environment and scenarios provide architecture design context that clarifies the motivation for decisions. Subsequent authors have introduced the notion of an influencing decision force, using a many-to-many relationship with concern, to provide further context for decisions. For both concerns and forces it is left to the architect to identify the nature of this context. This paper proposes a systematic process for identifying and documenting design context in support of architectural decisions. For our work decision force is used as a central unifying aspect of the architecture framework metamodel. We extend the decision Forces Viewpoint to capture detailed design context descriptions, and add features for tagging the architecture description elements to facilitate identification of commonality, classification, and specialization. Initial feedback from industry stakeholders indicates this approach should be explored further.
Bookmarks Related papers MentionsView impact
Proceedings of the 10th international ACM Sigsoft conference on Quality of software architectures - QoSA '14, 2014
Wide availability of multicore CPUs makes concurrency a critical design factor for the software a... more Wide availability of multicore CPUs makes concurrency a critical design factor for the software architecture and execution models of industrial controllers, especially with messages passing between tasks running on different cores. To improve performance, we refactored a standardized shared memory IPC mechanism implemented with traditional kernel locks to use lock-free algorithms. Prototyping the changes made it possible to determine the speed-up when the locks were removed, but we could neither easily confirm whether the IPC performance would suffice for the communication patterns in our real-time system, nor could we tell how well the implementation would scale to CPUs with more cores than our test machine. In this paper we report on our experience with using a queuing petri net performance model to predict the impact of memory contention in a multi-core CPU on architecture level performance. We instantiated our model with benchmark data and prototype measurements. The results from our model simulation provide valuable feedback for design decisions and point at potential bottlenecks. Comparison of the prototype's performance with our model simulation results increases credibility of our work. This paper supports other practitioners who consider applying performance modeling to quantify the quality of their architectures.
Bookmarks Related papers MentionsView impact
2014 IEEE/IFIP Conference on Software Architecture, 2014
Bookmarks Related papers MentionsView impact
2015 IEEE First International Conference on Big Data Computing Service and Applications, 2015
Bookmarks Related papers MentionsView impact
2016 19th International ACM SIGSOFT Symposium on Component-Based Software Engineering (CBSE), 2016
Bookmarks Related papers MentionsView impact
Bookmarks Related papers MentionsView impact
ArXiv, 2016
The Industrial Internet market is targeted to grow by trillions of US dollars by the year 2030, d... more The Industrial Internet market is targeted to grow by trillions of US dollars by the year 2030, driven by adoption, deployment and integration of billions of intelligent devices and their associated data. This digital expansion faces a number of significant challenges, including reliable data management, security and privacy. Realizing the benefits from this evolution is made more difficult because a typical industrial plant includes multiple vendors and legacy technology stacks. Aggregating all the raw data to a single data center before performing analysis increases response times, raising performance concerns in traditional markets and requiring a compromise between data duplication and data access performance. Similar to the way microservices can integrate disparate information technologies without imposing monolithic cross-cutting architecture impacts, we propose microdatabases to manage the data heterogeneity of the Industrial Internet while allowing records to be captured and...
Bookmarks Related papers MentionsView impact
ArXiv, 2016
A single vendor cannot provide complete IIoT end-to-end solutions because cooperation is required... more A single vendor cannot provide complete IIoT end-to-end solutions because cooperation is required from multiple parties. Interoperability is a key architectural quality. Composability of capabilities, information and configuration is the prerequisite for interoperability, supported by a data storage infrastructure and defined set of interfaces to build applications. Secure collection, transport and storage of data and algorithms are expectations for collaborative participation in any IIoT solution. Participants require control of their data ownership and confidentiality. We propose an Internet of Things, Services and People (IoTSP) application development and management framework which includes components for data storage, algorithm design and packaging, and computation execution. Applications use clusters of platform services, organized in tiers, and local access to data to reduce complexity and enhance reliable data exchange. Since communication is less reliable across tiers, data...
Bookmarks Related papers MentionsView impact
ArXiv, 2014
Data race conditions in multi-tasking software applications are prevented by serializing access t... more Data race conditions in multi-tasking software applications are prevented by serializing access to shared memory resources, ensuring data consistency and deterministic behavior. Traditionally tasks acquire and release locks to synchronize operations on shared memory. Unfortunately, lock management can add significant processing overhead especially for multicore deployments where tasks on different cores convoy in queues waiting to acquire a lock. Implementing more than one lock introduces the risk of deadlock and using spinlocks constrains which cores a task can run on. The better alternative is to eliminate locks and validate that real-time properties are met, which is not directly considered in many embedded applications. Removing the locks is non-trivial and packaging lock-free algorithms for developers reduces the possibility of concurrency defects. This paper details how a multicore communication API implementation is enhanced to support lock-free messaging and the impact this ...
Bookmarks Related papers MentionsView impact
Cmg, 2008
Bookmarks Related papers MentionsView impact
Wide availability of multicore CPUs makes concurrency a critical design factor for the software a... more Wide availability of multicore CPUs makes concurrency a
critical design factor for the software architecture and execution models of industrial controllers, especially with messages passing between tasks running on diff erent cores. To
improve performance, we refactored a standardized shared
memory IPC mechanism implemented with traditional kernel
locks to use lock-free algorithms. Prototyping the changes
made it possible to determine the speed-up when the locks
were removed, but we could neither easily con rm whether
the IPC performance would suffice for the communication
patterns in our real-time system, nor could we tell how well
the implementation would scale to CPUs with more cores
than our test machine. In this paper we report on our experience with using a queuing petri net performance model
to predict the impact of memory contention in a multi-core
CPU on architecture level performance. We instantiated our
model with benchmark data and prototype measurements.
The results from our model simulation provide valuable feedback for design decisions and point at potential bottlenecks. Comparison of the prototype's performance with our model simulation results increases credibility of our work. This paper supports other practitioners who consider applying
performance modeling to quantify the quality of their architectures.
Bookmarks Related papers MentionsView impact
Architecture description can be modeled as a set of alternative choices and decisions, where the ... more Architecture description can be modeled as a set of alternative choices and decisions, where the rationale and tradeoffs for each decision are documented and understood as needed to inform subsequent decisions. Each decision, based on ISO/IEC/IEEE 42010, pertains to one or more stakeholder concerns. These concerns combined with the system environment and scenarios provide architecture design context that clarifies the motivation for decisions. Subsequent authors have introduced the notion of an influencing decision force, using a many-to-many relationship with concern, to provide further context for decisions. For both concerns and forces it is left to the architect to identify the nature of this context. This paper proposes a systematic process for identifying and documenting design context in support of architectural decisions. For our work decision force is used as a central unifying aspect of the architecture framework metamodel. We extend the decision Forces Viewpoint to capture detailed design context descriptions, and add features for tagging the architecture description elements to facilitate identification of commonality, classification, and specialization. Initial feedback from industry stakeholders indicates this approach should be explored further.
Bookmarks Related papers MentionsView impact
Decreasing cost and increasing capabilities of instrumentation, networks and data repositories ha... more Decreasing cost and increasing capabilities of instrumentation, networks and data repositories have pervaded the industrial automation and power markets and opened the door for large scale collection and analysis of data. There are a variety of technology stacks that can be applied to these types of activities. However, no single infrastructure or architecture fits all the scenarios. With limited data science training and experience, it is difficult and time consuming for highly specialized domain experts to choose the optimal approach. In this paper, we introduce an architectural pattern for the design of a flexible core analytics platform which is extensible using different pipelines. The pipeline pattern provides an accelerated start to implementing industrial analytics applications. The platform enables domain experts to compose pipelines in series and in parallel at scale with the right quality attribute trade-offs to deliver significant business value. Our use of the proposed platform is illustrated with real-world industrial applications, which necessitate various data handling and processing capabilities. These examples show the importance of the platform to non-data experts: reducing the learning curve for applying data science, providing a systematic rating process for choosing the pipeline types, and lowering the barriers for industrial businesses to leverage analytics.
Bookmarks Related papers MentionsView impact
Data race conditions in multi-tasking software applications are prevented by serializing access t... more Data race conditions in multi-tasking software applications are prevented by serializing access to shared memory resources, ensuring data consistency and deterministic behavior. Traditionally tasks acquire and release locks to synchronize operations on shared memory. Unfortunately, lock management can add significant processing overhead especially for multicore deployments where tasks on different cores convoy in queues waiting to acquire a lock. Implementing more than one lock introduces the risk of deadlock and using spinlocks constrains which cores a task can run on. The better alternative is to eliminate locks and validate that real-time properties are met, which is not directly considered in many embedded applications. Removing the locks is non-trivial and packaging lock-free algorithms for developers reduces the possibility of concurrency defects. This paper details how a multicore communication API implementation is enhanced to support lock-free messaging and the impact this has on data exchange latency between tasks. Throughput and latency are compared on Windows and Linux between lock-based and lock-free implementations for data exchange of messages, packets, and scalars. A model of the lock-free exchange predicts performance at the system architecture level and provides a stop criterion for the refactoring. The results show that migration from single to multicore hardware architectures degrades lock-based performance, and increases lock-free performance.
Bookmarks Related papers MentionsView impact