Keivan Navi - Academia.edu (original) (raw)

Papers by Keivan Navi

In this paper, a modified auto zeroed integrator is used to design and simulate a low-voltage hig... more In this paper, a modified auto zeroed integrator is used to design and simulate a low-voltage high-Q switched capacitor pseudo 2-path filter. The filter is a sixth–order Chebyshev band-pass filter operating at sampling frequency of 1MHz and center frequency of 250 kHz with a quality factor of 50. The proposed filter has both low-voltage and high speed properties of the auto zeroed integrators and accurate center frequency of N-path band-pass filters. The operating voltage is 1.5v with no use of voltage bootstrapper circuit. Simulation is done using HSPICE and 0.25µm CMOS technology.

Journal of Circuits System and Computers

In this paper, a new switched opamp is presented in order to improve the operation of auto zeroed... more In this paper, a new switched opamp is presented in order to improve the operation of auto zeroed switched capacitor circuit. This approach results in a considerable reduction in power consumption and a moderate speed improvement. Based on the above improvement, a 2nd order band-pass filter with center frequency of 833 kHz and quality factor of 8 is realized and compared to previous work The proposed switched opamp is also utilized in the structure of a novel z to –z2 block for the design of pseudo two-path band-pass filters. A 2nd order pseudo two-path band-pass filter with the same specification of the previous work is designed, simulated, and compared.

2006 2nd International Conference on Information & Communication Technologies, 2006

Implementation ofparallel multipliers with operands meeting IEEE 754 standard could involve a 27.... more Implementation ofparallel multipliers with operands meeting IEEE 754 standard could involve a 27.2 compression ofpartialproducts. In this paper we offer a new design which is suitable for low power and high speedprocessing environment, more than 41% of carryinlout wires are eliminated in our design. By using this new design, when cascading a chain of this kind of compressor we achieve evens more performance and less chip area. While the whole design is coded in VHDL language and the implementation gives comparable results to full custom designs. Realistic simulations using extracted timing parameters from the layout show that the propagation time of a critical path is almost 26% for sum and 29% for carry faster than the conventional 27.2 compressor.

2011 International Semiconductor Device Research Symposium (ISDRS), 2011

Quantum dots cellular automata is a new computing method in the nanotechnology that has considera... more Quantum dots cellular automata is a new computing method in the nanotechnology that has considerable features such as low power, small dimension and high speed switch. A QCA device stores logic based on the position of individual electrons. The fundamental logic elements in QCA are the majority ( ) and inverter gates ( ) that operate based on the Coulomb repulsion between electrons [1].

Arabian Journal for Science and Engineering, 2014

ABSTRACT Great attention is paid to develop the nanotechnology fabrication techniques but few att... more ABSTRACT Great attention is paid to develop the nanotechnology fabrication techniques but few attempts were done to develop special design techniques for the emerging nanotechnologies. In this paper a new design approach for the multi-input XOR suitable for nanotechnologies is presented. This approach uses the multi-input majority function as a building block. The proposed method causes significant improvement in the gate level. The proposed design approach is deployed to CNFET 5-input & 7-input XOR circuit. The results show good improvements in the speed and number of devices.

Journal of Nanotechnology, 2012

Quantum-dot Cellular Automata (QCA) is one of the most attractive technologies for computing at n... more Quantum-dot Cellular Automata (QCA) is one of the most attractive technologies for computing at nanoscale. The principle element in QCA is majority gate. In this paper, fault-tolerance properties of the majority gate is analyzed. This component is suitable for designing fault-tolerant QCA circuits. We analyze fault-tolerance properties of three-input majority gate in terms of misalignment, missing, and dislocation cells. In order to verify the functionality of the proposed component some physical proofs using kink energy (the difference in electrostatic energy between the two polarization states) and computer simulations using QCA Designer tool are provided. Our results clearly demonstrate that the redundant version of the majority gate is more robust than the standard style for this gate.

Applications of Digital Signal Processing, 2011

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), 2012

ABSTRACT This paper presents a fault tolerant routing algorithm for injured hypercube. The propos... more ABSTRACT This paper presents a fault tolerant routing algorithm for injured hypercube. The proposed routing algorithm backtracks from the faulty nodes using stacks of passed nodes embedded in the header of messages. When a node receives a new message, a set of possible destinations for the message is formed using the mentioned stack. This helps the receiving node to detect its adjacent faulty nodes and to prevent the message to pass through the corresponding links. In this way, the proposed algorithm efficiently works with any number of faulty nodes in the network. Deadlock freedom of the proposed routing algorithm is obtained by the lowest possible requirements i.e., one virtual channel per each physical channel. In order to evaluate the proposed routing algorithm, a 7-dimentional hypercube network is simulated in various conditions i.e., different traffic rates, different number of faulty nodes, and different message lengths. Simulation results confirm that the proposed routing algorithm in comparison with the previously proposed routings: 1) provides an average of 20% improvement in the performance of the network, and 2) increases the reliability of the network.

IEICE Transactions on Information and Systems, 2014

ABSTRACT

Journal of Computational Electronics, 2014

ABSTRACT By the inevitable scaling down of the feature size of the MOS transistors which are deep... more ABSTRACT By the inevitable scaling down of the feature size of the MOS transistors which are deeper in nanoranges, the CMOS technology has encountered many critical challenges and problems such as very high leakage currents, reduced gate control, high power density, increased circuit noise sensitivity and very high lithography costs. Quantum-dot cellular automata (QCA) owing to its high device density, extremely low power consumption and very high switching speed could be a feasible competitive alternative. In this paper, a novel 5-input majority gate, an important fundamental building block in QCA circuits, is designed in a symmetric form. In addition to the majority gate, a SR latch, a SR gate and an efficient one bit QCA full adder are implemented employing the new 5-input majority gate. In order to verify the functionality of the proposed designs, QCADesigner tool is used. The results demonstrate that the proposed SR latch and full adder perform equally well or in many cases better than previous circuits.

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), 2012

ABSTRACT Due to low power dissipation in computing, reversible logic is an attractive field of re... more ABSTRACT Due to low power dissipation in computing, reversible logic is an attractive field of research in quantum and optical computing. Since the conventional CMOS technology cannot be used for implementing reversible gates owing to its high power dissipation, employing novel technologies such as nano-scale ones are being deployed. In this paper we utilize Quantum-dot Cellular Automata (QCA) as a candidate technology for implementing reversible logic gates. This paper presents a new realization approach to reversible logic based on majority gates (MGs) and a new reversible gate is proposed as well. The gate will be compared with an existing MG-based structure in terms of delay, complexity and area. The results show that even though our gate requires more cells, it returns the outputs in less clock cycles and hence the design is faster.

ABSTRACT Compressors play an important role for partial products reduction in the multiplication ... more ABSTRACT Compressors play an important role for partial products reduction in the multiplication process. This paper presents a new implementation for the second phase of a 16 × 16-bit multiplier block using wide m:3 compressors such as 8:3, 9:3, and 10:3. Transistor-level and gate-level analysis are conducted to simulate, test, and implement the proposed structures in 90 nm CMOS technology. The proposed structure has 16% higher efficiency compared when only up to 7:3 counters are employed.

Dynamic logic is a well-known logic style which is widely used in digital electronics. A mixed dy... more Dynamic logic is a well-known logic style which is widely used in digital electronics. A mixed dynamic/static full adder cell is presented in this paper with the aim of reaching high efficiency. The midoutputs are obtained from a Multi-output dynamic module. Then, a multiplexer generates final outputs in the static part. Several conventional and state-of-the-art dynamic adders are also surveyed and compared in the paper. All circuits are simulated by HSPICE with 32 nm CNFET technology. The proposed design is the fastest dynamic adder cell. In addition, it has approximately 5% higher efficiency in terms of PDP than the second most high-performance cell, which is DDCVS.

ABSTRACT Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs... more ABSTRACT Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32 nm CNTFET technology at various realistic conditions such as different power supplies, load capacitors, frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even in the presence of PVT variations. In addition, new noise injection circuits for ternary logic are also presented to perform noise immunity analysis.

New ternary adders, which are fundamental components of ternary addition, are presented in this p... more New ternary adders, which are fundamental components of ternary addition, are presented in this paper. They are on the basis of a logic style which mostly generates binary signals. Therefore, static power dissipation reaches its minimum extent. Extensive different analyses are carried out to examine how efficient the new designs are. For instance, the ternary ripple adder constructed by the proposed ternary half and full adders consumes 2.33 W less power than the one implemented by the previous adder cells. It is almost twice faster as well. Due to their unique superior characteristics for ternary circuitry, carbon nanotube field-effect transistors are used to form the novel circuits, which are entirely suitable for practical applications.

Quantum-dot cellular automata (QCA) are a transistorless computation approach which encodes binar... more Quantum-dot cellular automata (QCA) are a transistorless computation approach which encodes binary information via configuration of charges among quantum dots. The fundamental QCA logic primitives are majority and inverter gates which can be utilized to design various QCA circuits. This study presents a novel approach to designing efficient QCA-based circuits based on Boolean expressions achieved from reconfiguration of five-input and three-input majority gates. Whereas the multiplexer and Exclusive-or are the most important fundamental logical circuits in digital systems, designing efficient and single layer structures without coplanar cross-over wiring is advantageous in QCA technology. In order to demonstrate the efficiency and usefulness of the proposed approach, simple and dense multiplexer and Exclusive-or structures are implemented. The proposed designs have significant improvement in terms of area, complexity, latency, and gate count in comparison to previous designs. The correct logical functionalities of presented structures have been authenticated using QCA designer tool.

In this paper, a modified auto zeroed integrator is used to design and simulate a low-voltage hig... more In this paper, a modified auto zeroed integrator is used to design and simulate a low-voltage high-Q switched capacitor pseudo 2-path filter. The filter is a sixth–order Chebyshev band-pass filter operating at sampling frequency of 1MHz and center frequency of 250 kHz with a quality factor of 50. The proposed filter has both low-voltage and high speed properties of the auto zeroed integrators and accurate center frequency of N-path band-pass filters. The operating voltage is 1.5v with no use of voltage bootstrapper circuit. Simulation is done using HSPICE and 0.25µm CMOS technology.

Journal of Circuits System and Computers

In this paper, a new switched opamp is presented in order to improve the operation of auto zeroed... more In this paper, a new switched opamp is presented in order to improve the operation of auto zeroed switched capacitor circuit. This approach results in a considerable reduction in power consumption and a moderate speed improvement. Based on the above improvement, a 2nd order band-pass filter with center frequency of 833 kHz and quality factor of 8 is realized and compared to previous work The proposed switched opamp is also utilized in the structure of a novel z to –z2 block for the design of pseudo two-path band-pass filters. A 2nd order pseudo two-path band-pass filter with the same specification of the previous work is designed, simulated, and compared.

2006 2nd International Conference on Information & Communication Technologies, 2006

Implementation ofparallel multipliers with operands meeting IEEE 754 standard could involve a 27.... more Implementation ofparallel multipliers with operands meeting IEEE 754 standard could involve a 27.2 compression ofpartialproducts. In this paper we offer a new design which is suitable for low power and high speedprocessing environment, more than 41% of carryinlout wires are eliminated in our design. By using this new design, when cascading a chain of this kind of compressor we achieve evens more performance and less chip area. While the whole design is coded in VHDL language and the implementation gives comparable results to full custom designs. Realistic simulations using extracted timing parameters from the layout show that the propagation time of a critical path is almost 26% for sum and 29% for carry faster than the conventional 27.2 compressor.

2011 International Semiconductor Device Research Symposium (ISDRS), 2011

Quantum dots cellular automata is a new computing method in the nanotechnology that has considera... more Quantum dots cellular automata is a new computing method in the nanotechnology that has considerable features such as low power, small dimension and high speed switch. A QCA device stores logic based on the position of individual electrons. The fundamental logic elements in QCA are the majority ( ) and inverter gates ( ) that operate based on the Coulomb repulsion between electrons [1].

Arabian Journal for Science and Engineering, 2014

ABSTRACT Great attention is paid to develop the nanotechnology fabrication techniques but few att... more ABSTRACT Great attention is paid to develop the nanotechnology fabrication techniques but few attempts were done to develop special design techniques for the emerging nanotechnologies. In this paper a new design approach for the multi-input XOR suitable for nanotechnologies is presented. This approach uses the multi-input majority function as a building block. The proposed method causes significant improvement in the gate level. The proposed design approach is deployed to CNFET 5-input & 7-input XOR circuit. The results show good improvements in the speed and number of devices.

Journal of Nanotechnology, 2012

Quantum-dot Cellular Automata (QCA) is one of the most attractive technologies for computing at n... more Quantum-dot Cellular Automata (QCA) is one of the most attractive technologies for computing at nanoscale. The principle element in QCA is majority gate. In this paper, fault-tolerance properties of the majority gate is analyzed. This component is suitable for designing fault-tolerant QCA circuits. We analyze fault-tolerance properties of three-input majority gate in terms of misalignment, missing, and dislocation cells. In order to verify the functionality of the proposed component some physical proofs using kink energy (the difference in electrostatic energy between the two polarization states) and computer simulations using QCA Designer tool are provided. Our results clearly demonstrate that the redundant version of the majority gate is more robust than the standard style for this gate.

Applications of Digital Signal Processing, 2011

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), 2012

ABSTRACT This paper presents a fault tolerant routing algorithm for injured hypercube. The propos... more ABSTRACT This paper presents a fault tolerant routing algorithm for injured hypercube. The proposed routing algorithm backtracks from the faulty nodes using stacks of passed nodes embedded in the header of messages. When a node receives a new message, a set of possible destinations for the message is formed using the mentioned stack. This helps the receiving node to detect its adjacent faulty nodes and to prevent the message to pass through the corresponding links. In this way, the proposed algorithm efficiently works with any number of faulty nodes in the network. Deadlock freedom of the proposed routing algorithm is obtained by the lowest possible requirements i.e., one virtual channel per each physical channel. In order to evaluate the proposed routing algorithm, a 7-dimentional hypercube network is simulated in various conditions i.e., different traffic rates, different number of faulty nodes, and different message lengths. Simulation results confirm that the proposed routing algorithm in comparison with the previously proposed routings: 1) provides an average of 20% improvement in the performance of the network, and 2) increases the reliability of the network.

IEICE Transactions on Information and Systems, 2014

ABSTRACT

Journal of Computational Electronics, 2014

ABSTRACT By the inevitable scaling down of the feature size of the MOS transistors which are deep... more ABSTRACT By the inevitable scaling down of the feature size of the MOS transistors which are deeper in nanoranges, the CMOS technology has encountered many critical challenges and problems such as very high leakage currents, reduced gate control, high power density, increased circuit noise sensitivity and very high lithography costs. Quantum-dot cellular automata (QCA) owing to its high device density, extremely low power consumption and very high switching speed could be a feasible competitive alternative. In this paper, a novel 5-input majority gate, an important fundamental building block in QCA circuits, is designed in a symmetric form. In addition to the majority gate, a SR latch, a SR gate and an efficient one bit QCA full adder are implemented employing the new 5-input majority gate. In order to verify the functionality of the proposed designs, QCADesigner tool is used. The results demonstrate that the proposed SR latch and full adder perform equally well or in many cases better than previous circuits.

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), 2012

ABSTRACT Due to low power dissipation in computing, reversible logic is an attractive field of re... more ABSTRACT Due to low power dissipation in computing, reversible logic is an attractive field of research in quantum and optical computing. Since the conventional CMOS technology cannot be used for implementing reversible gates owing to its high power dissipation, employing novel technologies such as nano-scale ones are being deployed. In this paper we utilize Quantum-dot Cellular Automata (QCA) as a candidate technology for implementing reversible logic gates. This paper presents a new realization approach to reversible logic based on majority gates (MGs) and a new reversible gate is proposed as well. The gate will be compared with an existing MG-based structure in terms of delay, complexity and area. The results show that even though our gate requires more cells, it returns the outputs in less clock cycles and hence the design is faster.

ABSTRACT Compressors play an important role for partial products reduction in the multiplication ... more ABSTRACT Compressors play an important role for partial products reduction in the multiplication process. This paper presents a new implementation for the second phase of a 16 × 16-bit multiplier block using wide m:3 compressors such as 8:3, 9:3, and 10:3. Transistor-level and gate-level analysis are conducted to simulate, test, and implement the proposed structures in 90 nm CMOS technology. The proposed structure has 16% higher efficiency compared when only up to 7:3 counters are employed.

Dynamic logic is a well-known logic style which is widely used in digital electronics. A mixed dy... more Dynamic logic is a well-known logic style which is widely used in digital electronics. A mixed dynamic/static full adder cell is presented in this paper with the aim of reaching high efficiency. The midoutputs are obtained from a Multi-output dynamic module. Then, a multiplexer generates final outputs in the static part. Several conventional and state-of-the-art dynamic adders are also surveyed and compared in the paper. All circuits are simulated by HSPICE with 32 nm CNFET technology. The proposed design is the fastest dynamic adder cell. In addition, it has approximately 5% higher efficiency in terms of PDP than the second most high-performance cell, which is DDCVS.

ABSTRACT Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs... more ABSTRACT Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32 nm CNTFET technology at various realistic conditions such as different power supplies, load capacitors, frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even in the presence of PVT variations. In addition, new noise injection circuits for ternary logic are also presented to perform noise immunity analysis.

New ternary adders, which are fundamental components of ternary addition, are presented in this p... more New ternary adders, which are fundamental components of ternary addition, are presented in this paper. They are on the basis of a logic style which mostly generates binary signals. Therefore, static power dissipation reaches its minimum extent. Extensive different analyses are carried out to examine how efficient the new designs are. For instance, the ternary ripple adder constructed by the proposed ternary half and full adders consumes 2.33 W less power than the one implemented by the previous adder cells. It is almost twice faster as well. Due to their unique superior characteristics for ternary circuitry, carbon nanotube field-effect transistors are used to form the novel circuits, which are entirely suitable for practical applications.

Quantum-dot cellular automata (QCA) are a transistorless computation approach which encodes binar... more Quantum-dot cellular automata (QCA) are a transistorless computation approach which encodes binary information via configuration of charges among quantum dots. The fundamental QCA logic primitives are majority and inverter gates which can be utilized to design various QCA circuits. This study presents a novel approach to designing efficient QCA-based circuits based on Boolean expressions achieved from reconfiguration of five-input and three-input majority gates. Whereas the multiplexer and Exclusive-or are the most important fundamental logical circuits in digital systems, designing efficient and single layer structures without coplanar cross-over wiring is advantageous in QCA technology. In order to demonstrate the efficiency and usefulness of the proposed approach, simple and dense multiplexer and Exclusive-or structures are implemented. The proposed designs have significant improvement in terms of area, complexity, latency, and gate count in comparison to previous designs. The correct logical functionalities of presented structures have been authenticated using QCA designer tool.