Kunjan D. Shinde - Academia.edu (original) (raw)

Papers by Kunjan D. Shinde

Advances in Intelligent Systems and Computing, 2017

Hands and legs are the most important part of our mobility in day-today life. People will find di... more Hands and legs are the most important part of our mobility in day-today life. People will find difficulty in handling their daily activities if they have problems with their hands and legs (Physically challenged, accidental causes, and due to some health issues). Due to this incapability in movement causes several problems in their routine chores, and hence in order to provide a flexible mobility (stand-alone mobility to study, work, and day-today activities) in their life we came up this project "Low Cost, Reliable, Advance Control With Head Movements Wheel Chair for Physically Challenged People." In this project we are making use of Head Movements/tilts to control the Electronic Wheelchair for movements in all directions as per the need of the Physically challenged people, apart from head movements the wheelchair has certain propriety to another control signal (like Enable signal for Head control unit, Manual direction controls, emergency stop, power supply enable switch). Keywords Head movements controlled wheelchair ⋅ Low cost wheelchair using arduino UNO ⋅ Head tilts using accelerometer ⋅ 25 A current driver for high torque motors ⋅ Distance sensing based head movement control Reliable wheelchair for physically challenged people

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN), 2016

Adders forms a major part in various arithmetic logical operations. Parallel Prefix Adder have be... more Adders forms a major part in various arithmetic logical operations. Parallel Prefix Adder have been built up as the most essential and efficient circuit for binary addition. Their Particular structure and execution performance are very attractive for VLSI implementation. In these papers, we describe the design and performance of the Kogge Stone Parallel Prefix Adders and implemented using different design technique. CMOS (Complementary Metal Oxide Semiconductor) and GDI (Gate Diffusion Input) are the different design technique used. The design and simulation of logic gates is performed on CADENCE Design Suit 6.1.6 using virtuoso and ADE Environment at GPDK 180nm technology. The execution measurement considered for the performance of the KSA is delay, number of gate count/Transistor Count (area) and power. Simulation studies are done for 4-bit, 8-bit and 16-bit input data.

Adder in general is a digital block used to perform addition operation of given data and generate... more Adder in general is a digital block used to perform addition operation of given data and generates the results as sum and carry_out. This block is used in various platform for addition/subtraction/multiplication applications. There are several approaches to design and verify the functionality of the adder, based on which they may be classified on type of data it uses for addition, precession of the adder, algorithm used to implementation the adder structure. In this paper we are concentrating on the algorithm/method used to implement an adder structure while keeping the precision constant and considering the binary data for verification of the design. Use of conventional adders like ripple carry adder, carry save adder and carry look ahead adder are not used/implemented for industry and research applications, on the other hand the parallel prefix adders became popular with their fast carry generation network. The presented work gives a detailed analysis on the impact of various VLSI...

Full adder is the functional building block and basic component in several architectures found in... more Full adder is the functional building block and basic component in several architectures found in VLSI and DSP applications, Adder is a versatile component and mainly used in addition and multiplication as the basic processing element; Adder in a VLSI application is used in ALU design, Address generation in processors, Multipliers and so on. In DSP applications it is used code for conversion, Signed addition and Signed multiplication, Transformations and signal processing applications. This defines the need and importance of designing an adder block in effective way. Systolic array architectures consists of processing elements(PE), where the computation of the task is divided and given to PE’s and final result is obtained for these PE’s; In systolic array multiplier we have 1-bit full adder as the Processing element in the structure. In this paper we have considered three different types of 1-bit full adder design namely 54Transistor CMOS design, 28Transistor CMOS design and 10Trans...

Multipliers play a important role in current signal processing chips like DSP and general purpose... more Multipliers play a important role in current signal processing chips like DSP and general purpose processors and applications. In such high performance systems addition and multiplication operations are fundamental and most used arithmetic operations. Some case study shows that more than 70% of DSP algorithms and in microprocessor operations perform addition and multiplication. Hence these operations dominate the execution time. To meet the processing speed demand, the design of multipliers and adders plays a vital role. Low power consumption has consumption has became a major issue in design of multiplier. To reduce the power consumption, the components used in the design must be drastically reduced and in parallel it should not degrade the other performance metric. In this paper we are proposing a new architecture to design multiplier using parallel prefix adders. The Parallel Prefix Adder (PPA) have fast carry generation network and hence they are the fastest types of adder that ...

The logic gates are the fundamental building blocks of VLSI and embedded applications. These gate... more The logic gates are the fundamental building blocks of VLSI and embedded applications. These gates can be designed using several design techniques and implemented at different levels of architectures. This paper focuses on design and evaluate the performance of logic gates used in the Adders and Multiplier using various design technique like CMOS design GDI design and PTL design. These different design styles have pros and corns with reference to performance measure as Delay, Power consumption, Area and Gate Count. The design and simulation of logic gates is performed on CADENCE Design Suit 6.1.6 using Virtuoso and ADE Environment at GPDK 180nm technology. Comparative study between logic gates designed using CMOS, GDI and Degenerated PTL technique is presented in this paper, with performance measure as Number of transistor (Gate count), Power, Delay, Area and Power Delay Product.

An image stitching method panorama gives serious issues with respect to distortion when collabora... more An image stitching method panorama gives serious issues with respect to distortion when collaborating long similar sequential images. To solve the distortion enhanced approach is proposed in this work, adding the alteration of the way sequential referred image and adding a head an approach that can calculate the transformation matrix[3] for any image with in the sequence to put for alignment[11] with the referred image with in the same space of coordinate area. Apart from this the enhanced stitching approach selects the next preceding image automatically based on the matched output points with respect to number of SIFT[10] approach. With regular stitching methodology and enhanced stitching[8] methodology , by comparing these two our approach decreases the SIFT features ROI detected area of the referred image. Our practical results shows theenhanced approach cannotonly initiate the efficiency of stitching on image processing and also drastic reduction of thepanoramic distortion[10][1...

International journal of engineering research and technology, 2018

Digital computations and processing is involved in each and every embedded and non-embedded devic... more Digital computations and processing is involved in each and every embedded and non-embedded device, such applications and devices has arithmetic logic unit, adders are most important and essential block of these system, design and selection of adders plays a very important role, this paper presents a comparative study of five different adders like Ripple Carry Adder, Carry Skip Adder, Carry Lookahead Adder, Kogge Stone Adder, with performance metrics as delay and area. From the results it is clear that Kogge Stone Adder provides a less delay with a compromise in area. Keywords— Ripple Carry Adder, Carry Skip Adder, Carry Lookahead Adder, Kogge Stone Adder, Delay, No. of slices, No. of LUTs.

Advances in Intelligent Systems and Computing, 2016

Multipliers are the significant arithmetic units which are used in various VLSI and DSP applicati... more Multipliers are the significant arithmetic units which are used in various VLSI and DSP applications. Besides their crucial necessity, Multipliers are also a main source for power dissipation. Hence prior importance must be given to lessen power dissipation in order to satisfy the overall power budget for various digital circuits and systems. Multiplier performance is directly influenced by the adder cells employed, for multipliers designed using adders; therefore power dissipation problem can be solved by exploring and using better adder designs. In this paper various full adder designs are analyzed in terms of delay, power consumption and area, As the adder block is prime concern for array multiplier in order to propose an efficient Multiplier architecture. The design and implementation of full adder cells and multiplier is performed on CADENCE design suite at GPDK 180nm technology. The CMOS, GDI and Optimized full adder design is employed to implement array multiplier.

JNNCE Journal of Engineering and Management, 2021

2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2015

Many surveys done on software developments for quaternion computation identifies floating point m... more Many surveys done on software developments for quaternion computation identifies floating point matrix multiplier as the most time consuming process. The floating point matrix multiplier is a highly procedure oriented process and involves computation of many partial products and storing them for final result computation. For above reason we propose a parallel matrix multiplier design which accelerates the computational speed. In this design the nested loops of software based matrix multiplier are converted into parallel computing blocks on FPGA using modified Systolic array for matrix multiplication, which best matches the inherent parallelism of FPGA architecture. The architecture utilizes only 14% of the IO resource and is 100 times faster compared to software implementation when implemented on FPGA Spartan-6 of 12MHz clock.

2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2015

In wireless communication system the phase locked loop plays important role, specially Voltage Co... more In wireless communication system the phase locked loop plays important role, specially Voltage Controlled Oscillator. It is an electronic device which is used for the purpose of generating a signal. Applications range is very vast, which includes clock generation in various microprocessors to carrier synthesis in cellular telephones, requiring a large range of different oscillators/signal generation topologies and the performance parameters differs as the need changes. VCO can be designed and built using many circuit techniques. This paper presents one of the ways to design and implementation of CMOS voltage controlled oscillators (VCO) for pll. A VCO is an oscillator circuit, where the control voltage controls the oscillator output frequency. In this paper CSVCO is has been designed Cadence Design Suite using GPDK 90nm CMOS Technology with supply voltage 1.8v. Intern Virtuoso Analog Design Environment tool of Cadence have used to design and simulate schematic. Simulation results are calculated for all process corners, temperature (-40°C to +100°C).

2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2015

Digital computations and processing is involved in each and every embedded and non-embedded devic... more Digital computations and processing is involved in each and every embedded and non-embedded device, such applications and devices has arithmetic logic unit, adders are most important and essential block of these system, design and selection of adders plays a very important role, this paper presents a comparative study of five different adders like Ripple Carry Adder, Carry Skip Adder, Carry Lookahead Adder, Kogge Stone Adder, with performance metrics as delay and area. From the results it is clear that Kogge Stone Adder provides a less delay with a compromise in area.

2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), 2016

As the days go by, the innovation in the technology is growing faster and smaller chips with more... more As the days go by, the innovation in the technology is growing faster and smaller chips with more complexity in the design and implementation. Design of adders is prime importance in any given embedded application; hence the design of reliable and efficient adder on a VLSI based embedded application matters. In this paper we primarily deal with the construction of high speed adder circuits. Design and modeling of various adders like Ripple Carry Adder, Kogge Stone Adder, and Brent Kung Adder is done by using CMOS and GDI logic and comparative analysis is coated. The simulated results verify the functionality of high speed adders and performance parameters like Power, Delay and power-delay product is analyzed. With the results obtained and analysis made, gives a clear picture that KSA is the more efficient in speed and power parameters.

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014

The most fundamental computational process encountered in digital system is binary addition, to a... more The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed on Cadence Design Suit 6.1.5 using Virtuoso and ADE environment at GPDK 45nm technology with a unvaried width and length of PMOS and NMOS devices. The paper gives a compression of various design of 1 bit full adder with respect to number of transistors/ gate count, Delay, Power and Power Delay Product.

Advances in Intelligent Systems and Computing, 2017

Hands and legs are the most important part of our mobility in day-today life. People will find di... more Hands and legs are the most important part of our mobility in day-today life. People will find difficulty in handling their daily activities if they have problems with their hands and legs (Physically challenged, accidental causes, and due to some health issues). Due to this incapability in movement causes several problems in their routine chores, and hence in order to provide a flexible mobility (stand-alone mobility to study, work, and day-today activities) in their life we came up this project "Low Cost, Reliable, Advance Control With Head Movements Wheel Chair for Physically Challenged People." In this project we are making use of Head Movements/tilts to control the Electronic Wheelchair for movements in all directions as per the need of the Physically challenged people, apart from head movements the wheelchair has certain propriety to another control signal (like Enable signal for Head control unit, Manual direction controls, emergency stop, power supply enable switch). Keywords Head movements controlled wheelchair ⋅ Low cost wheelchair using arduino UNO ⋅ Head tilts using accelerometer ⋅ 25 A current driver for high torque motors ⋅ Distance sensing based head movement control Reliable wheelchair for physically challenged people

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN), 2016

Adders forms a major part in various arithmetic logical operations. Parallel Prefix Adder have be... more Adders forms a major part in various arithmetic logical operations. Parallel Prefix Adder have been built up as the most essential and efficient circuit for binary addition. Their Particular structure and execution performance are very attractive for VLSI implementation. In these papers, we describe the design and performance of the Kogge Stone Parallel Prefix Adders and implemented using different design technique. CMOS (Complementary Metal Oxide Semiconductor) and GDI (Gate Diffusion Input) are the different design technique used. The design and simulation of logic gates is performed on CADENCE Design Suit 6.1.6 using virtuoso and ADE Environment at GPDK 180nm technology. The execution measurement considered for the performance of the KSA is delay, number of gate count/Transistor Count (area) and power. Simulation studies are done for 4-bit, 8-bit and 16-bit input data.

Adder in general is a digital block used to perform addition operation of given data and generate... more Adder in general is a digital block used to perform addition operation of given data and generates the results as sum and carry_out. This block is used in various platform for addition/subtraction/multiplication applications. There are several approaches to design and verify the functionality of the adder, based on which they may be classified on type of data it uses for addition, precession of the adder, algorithm used to implementation the adder structure. In this paper we are concentrating on the algorithm/method used to implement an adder structure while keeping the precision constant and considering the binary data for verification of the design. Use of conventional adders like ripple carry adder, carry save adder and carry look ahead adder are not used/implemented for industry and research applications, on the other hand the parallel prefix adders became popular with their fast carry generation network. The presented work gives a detailed analysis on the impact of various VLSI...

Full adder is the functional building block and basic component in several architectures found in... more Full adder is the functional building block and basic component in several architectures found in VLSI and DSP applications, Adder is a versatile component and mainly used in addition and multiplication as the basic processing element; Adder in a VLSI application is used in ALU design, Address generation in processors, Multipliers and so on. In DSP applications it is used code for conversion, Signed addition and Signed multiplication, Transformations and signal processing applications. This defines the need and importance of designing an adder block in effective way. Systolic array architectures consists of processing elements(PE), where the computation of the task is divided and given to PE’s and final result is obtained for these PE’s; In systolic array multiplier we have 1-bit full adder as the Processing element in the structure. In this paper we have considered three different types of 1-bit full adder design namely 54Transistor CMOS design, 28Transistor CMOS design and 10Trans...

Multipliers play a important role in current signal processing chips like DSP and general purpose... more Multipliers play a important role in current signal processing chips like DSP and general purpose processors and applications. In such high performance systems addition and multiplication operations are fundamental and most used arithmetic operations. Some case study shows that more than 70% of DSP algorithms and in microprocessor operations perform addition and multiplication. Hence these operations dominate the execution time. To meet the processing speed demand, the design of multipliers and adders plays a vital role. Low power consumption has consumption has became a major issue in design of multiplier. To reduce the power consumption, the components used in the design must be drastically reduced and in parallel it should not degrade the other performance metric. In this paper we are proposing a new architecture to design multiplier using parallel prefix adders. The Parallel Prefix Adder (PPA) have fast carry generation network and hence they are the fastest types of adder that ...

The logic gates are the fundamental building blocks of VLSI and embedded applications. These gate... more The logic gates are the fundamental building blocks of VLSI and embedded applications. These gates can be designed using several design techniques and implemented at different levels of architectures. This paper focuses on design and evaluate the performance of logic gates used in the Adders and Multiplier using various design technique like CMOS design GDI design and PTL design. These different design styles have pros and corns with reference to performance measure as Delay, Power consumption, Area and Gate Count. The design and simulation of logic gates is performed on CADENCE Design Suit 6.1.6 using Virtuoso and ADE Environment at GPDK 180nm technology. Comparative study between logic gates designed using CMOS, GDI and Degenerated PTL technique is presented in this paper, with performance measure as Number of transistor (Gate count), Power, Delay, Area and Power Delay Product.

An image stitching method panorama gives serious issues with respect to distortion when collabora... more An image stitching method panorama gives serious issues with respect to distortion when collaborating long similar sequential images. To solve the distortion enhanced approach is proposed in this work, adding the alteration of the way sequential referred image and adding a head an approach that can calculate the transformation matrix[3] for any image with in the sequence to put for alignment[11] with the referred image with in the same space of coordinate area. Apart from this the enhanced stitching approach selects the next preceding image automatically based on the matched output points with respect to number of SIFT[10] approach. With regular stitching methodology and enhanced stitching[8] methodology , by comparing these two our approach decreases the SIFT features ROI detected area of the referred image. Our practical results shows theenhanced approach cannotonly initiate the efficiency of stitching on image processing and also drastic reduction of thepanoramic distortion[10][1...

International journal of engineering research and technology, 2018

Digital computations and processing is involved in each and every embedded and non-embedded devic... more Digital computations and processing is involved in each and every embedded and non-embedded device, such applications and devices has arithmetic logic unit, adders are most important and essential block of these system, design and selection of adders plays a very important role, this paper presents a comparative study of five different adders like Ripple Carry Adder, Carry Skip Adder, Carry Lookahead Adder, Kogge Stone Adder, with performance metrics as delay and area. From the results it is clear that Kogge Stone Adder provides a less delay with a compromise in area. Keywords— Ripple Carry Adder, Carry Skip Adder, Carry Lookahead Adder, Kogge Stone Adder, Delay, No. of slices, No. of LUTs.

Advances in Intelligent Systems and Computing, 2016

Multipliers are the significant arithmetic units which are used in various VLSI and DSP applicati... more Multipliers are the significant arithmetic units which are used in various VLSI and DSP applications. Besides their crucial necessity, Multipliers are also a main source for power dissipation. Hence prior importance must be given to lessen power dissipation in order to satisfy the overall power budget for various digital circuits and systems. Multiplier performance is directly influenced by the adder cells employed, for multipliers designed using adders; therefore power dissipation problem can be solved by exploring and using better adder designs. In this paper various full adder designs are analyzed in terms of delay, power consumption and area, As the adder block is prime concern for array multiplier in order to propose an efficient Multiplier architecture. The design and implementation of full adder cells and multiplier is performed on CADENCE design suite at GPDK 180nm technology. The CMOS, GDI and Optimized full adder design is employed to implement array multiplier.

JNNCE Journal of Engineering and Management, 2021

2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2015

Many surveys done on software developments for quaternion computation identifies floating point m... more Many surveys done on software developments for quaternion computation identifies floating point matrix multiplier as the most time consuming process. The floating point matrix multiplier is a highly procedure oriented process and involves computation of many partial products and storing them for final result computation. For above reason we propose a parallel matrix multiplier design which accelerates the computational speed. In this design the nested loops of software based matrix multiplier are converted into parallel computing blocks on FPGA using modified Systolic array for matrix multiplication, which best matches the inherent parallelism of FPGA architecture. The architecture utilizes only 14% of the IO resource and is 100 times faster compared to software implementation when implemented on FPGA Spartan-6 of 12MHz clock.

2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2015

In wireless communication system the phase locked loop plays important role, specially Voltage Co... more In wireless communication system the phase locked loop plays important role, specially Voltage Controlled Oscillator. It is an electronic device which is used for the purpose of generating a signal. Applications range is very vast, which includes clock generation in various microprocessors to carrier synthesis in cellular telephones, requiring a large range of different oscillators/signal generation topologies and the performance parameters differs as the need changes. VCO can be designed and built using many circuit techniques. This paper presents one of the ways to design and implementation of CMOS voltage controlled oscillators (VCO) for pll. A VCO is an oscillator circuit, where the control voltage controls the oscillator output frequency. In this paper CSVCO is has been designed Cadence Design Suite using GPDK 90nm CMOS Technology with supply voltage 1.8v. Intern Virtuoso Analog Design Environment tool of Cadence have used to design and simulate schematic. Simulation results are calculated for all process corners, temperature (-40°C to +100°C).

2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2015

Digital computations and processing is involved in each and every embedded and non-embedded devic... more Digital computations and processing is involved in each and every embedded and non-embedded device, such applications and devices has arithmetic logic unit, adders are most important and essential block of these system, design and selection of adders plays a very important role, this paper presents a comparative study of five different adders like Ripple Carry Adder, Carry Skip Adder, Carry Lookahead Adder, Kogge Stone Adder, with performance metrics as delay and area. From the results it is clear that Kogge Stone Adder provides a less delay with a compromise in area.

2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), 2016

As the days go by, the innovation in the technology is growing faster and smaller chips with more... more As the days go by, the innovation in the technology is growing faster and smaller chips with more complexity in the design and implementation. Design of adders is prime importance in any given embedded application; hence the design of reliable and efficient adder on a VLSI based embedded application matters. In this paper we primarily deal with the construction of high speed adder circuits. Design and modeling of various adders like Ripple Carry Adder, Kogge Stone Adder, and Brent Kung Adder is done by using CMOS and GDI logic and comparative analysis is coated. The simulated results verify the functionality of high speed adders and performance parameters like Power, Delay and power-delay product is analyzed. With the results obtained and analysis made, gives a clear picture that KSA is the more efficient in speed and power parameters.

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014

The most fundamental computational process encountered in digital system is binary addition, to a... more The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed on Cadence Design Suit 6.1.5 using Virtuoso and ADE environment at GPDK 45nm technology with a unvaried width and length of PMOS and NMOS devices. The paper gives a compression of various design of 1 bit full adder with respect to number of transistors/ gate count, Delay, Power and Power Delay Product.