Kwangsoo Han - Academia.edu (original) (raw)
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Motilal Nehru National Institute of Technology
International Journal of Engineering Research and Applications (IJERA)
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Papers by Kwangsoo Han
Proc. Great Lakes Symposium on VLSI, May 23, 2014
The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., cloc... more The clock trees of high-performance synchronous circuits have
many clock logic cells (e.g., clock gating cells, multiplexers
and dividers) in order to achieve aggressive clock gating and
required performance across a wide range of operating modes
and conditions. As a result, clock tree structures have become
very complex and difficult to optimize with automatic clock tree
synthesis (CTS) tools. In advanced process nodes, CTS becomes
even more challenging due to on-chip variation (OCV) effects. In
this paper, we present a new CTS methodology that optimizes clock
logic cell placements and buffer insertions in the top level of a clock
tree. We formulate the top-level clock tree optimization problem
as a linear program that minimizes a weighted sum of timing
slacks, clock uncertainty and wirelength. Experimental results in
a commercial 28nm FDSOI technology show that our method can
improve post-CTS worst negative slack across all modes/corners
by up to 320ps compared to a leading commercial provider’s CTS
flow.
Proc. Great Lakes Symposium on VLSI, May 23, 2014
The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., cloc... more The clock trees of high-performance synchronous circuits have
many clock logic cells (e.g., clock gating cells, multiplexers
and dividers) in order to achieve aggressive clock gating and
required performance across a wide range of operating modes
and conditions. As a result, clock tree structures have become
very complex and difficult to optimize with automatic clock tree
synthesis (CTS) tools. In advanced process nodes, CTS becomes
even more challenging due to on-chip variation (OCV) effects. In
this paper, we present a new CTS methodology that optimizes clock
logic cell placements and buffer insertions in the top level of a clock
tree. We formulate the top-level clock tree optimization problem
as a linear program that minimizes a weighted sum of timing
slacks, clock uncertainty and wirelength. Experimental results in
a commercial 28nm FDSOI technology show that our method can
improve post-CTS worst negative slack across all modes/corners
by up to 320ps compared to a leading commercial provider’s CTS
flow.