Lucidio Finol - Academia.edu (original) (raw)

Papers by Lucidio Finol

Research paper thumbnail of International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, April 22-25, 2019

Research paper thumbnail of Tuning circuit for an RC filter

Research paper thumbnail of Circuit and method for processing data

Research paper thumbnail of DC level shifting circuit for analog circuits

Research paper thumbnail of Radio Architecture with Dual Frequency Source Selection

Research paper thumbnail of Design, optimization and fabrication of a tanh/sinh-type bipolar transconductor with maximum linearity

Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)

We have designed, optimized and fabricated a bipolar transconductor with maximum static transfer ... more We have designed, optimized and fabricated a bipolar transconductor with maximum static transfer function linearity. The optimization was based on an analytic function that corresponds to the integral nonlinearity of the circuit. This transconductor is composed of two parallel-connected non-linear blocks: a hyperbolic tangent-type transconductor and hyperbolic sine-type transconductor. The transconductor was fabricated using 0.5 μm BiCMOS mixed-signal process. A minimum THD value of 0.2% was obtained with a 100 μs transconductance up to a maximum input voltage swing of 50 mV peak.

Research paper thumbnail of Building blocks for digital wireless communications in sub-micron technologies: an overview

Proceedings of the 1998 Second IEEE International Caracas Conference on Devices, Circuits and Systems. ICCDCS 98. On the 70th Anniversary of the MOSFET and 50th of the BJT. (Cat. No.98TH8350)

This paper presents an overview of both the basic building blocks and process technologies associ... more This paper presents an overview of both the basic building blocks and process technologies associated with silicon ICs for personal wireless communications. The technical challenges to achieve higher levels of RF monolithic integration at a low cost and with low power dissipation in battery-powered portable transceivers are presented. Specific emphasis will be given to applications in the 1 to 2

Research paper thumbnail of Design of an inphase and quadrature phase and amplitude imbalance compensation in quadrature receivers

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004.

ABSTRACT This paper presents a compensation technique for the amplitude and phase imbalance betwe... more ABSTRACT This paper presents a compensation technique for the amplitude and phase imbalance between the I and the Q components of a quadrature demodulator. The proposed scheme allows the implementation of a fully integrated self-aligned tuner for digital modulation systems such as QAM demodulation and receivers. It is based on a mixed signal analog/digital integrated circuit approach to automatically correct amplitude and phase imbalances resulting from mismatch of integrated circuit components. The approach presented uses the original signal information to create both a control signal for the amplitude and phase correction. It uses digital circuitry to compensate for mismatch errors, by means of an analog feedback mechanism, and perform high accuracy phase and amplitude quadrature correction.

Research paper thumbnail of Comments on “A sinh Resistor and Its Application to tanh Linearization&#8221

IEEE Journal of Solid-State Circuits, 2006

ABSTRACT

Research paper thumbnail of Design of an Inphase and Quadrature Phase and Amplitude Imbalance Compensation in Quadrature Receivers

This paper presents a compensation technique for the amplitude and phase imbalance between the I ... more This paper presents a compensation technique for the amplitude and phase imbalance between the I and the Q components of a quadrature demodulator. The proposed scheme allows the implementation of a fully integrated self-aligned tuner for digital modulation systems such as QAM demodulation and Zero-IF Receivers. It is based on a mixed signal analog/digital integrated circuit approach to automatically correct amplitude and phase imbalances resulting from mismatch of integrated circuit components. The approach presented uses the original digital signal information to create both a control signal for the amplitude and phase correction. It uses digital circuitry to compensate for mismatch errors, by means of an analog feedback mechanism, and perform high accuracy phase and amplitude quadrature correction.

Research paper thumbnail of Design of an Inphase and Quadrature Phase and Amplitude Imbalance Compensation in Quadrature Receivers

This paper presents a compensation technique for the amplitude and phase imbalance between the I ... more This paper presents a compensation technique for the amplitude and phase imbalance between the I and the Q components of a quadrature demodulator. The proposed scheme allows the implementation of a fully integrated self-aligned tuner for digital modulation systems such as QAM demodulation and Zero-IF Receivers. It is based on a mixed signal analog/digital integrated circuit approach to automatically correct amplitude and phase imbalances resulting from mismatch of integrated circuit components. The approach presented uses the original digital signal information to create both a control signal for the amplitude and phase correction. It uses digital circuitry to compensate for mismatch errors, by means of an analog feedback mechanism, and perform high accuracy phase and amplitude quadrature correction.

Research paper thumbnail of Design of an Inphase and Quadrature Phase and Amplitude Imbalance Compensation in Quadrature Receivers

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, Dominican Republic, Nov.3-5, 2004, 2004

This paper presents a compensation technique for the amplitude and phase imbalance between the I ... more This paper presents a compensation technique for the amplitude and phase imbalance between the I and the Q components of a quadrature demodulator. The proposed scheme allows the implementation of a fully integrated self-aligned tuner for digital modulation systems such as QAM demodulation and Zero-IF Receivers. It is based on a mixed signal analog/digital integrated circuit approach to automatically correct amplitude and phase imbalances resulting from mismatch of integrated circuit components. The approach presented uses the original digital signal information to create both a control signal for the amplitude and phase correction. It uses digital circuitry to compensate for mismatch errors, by means of an analog feedback mechanism, and perform high accuracy phase and amplitude quadrature correction.

Research paper thumbnail of Linearity in two optical receiver structures for high-frequency applications

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004., 2004

The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double ... more The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based on a wide-band PLL topology with a high reference frequency. This approach allows obtaining low phase noise, fast switching time, a low divider ratio and a reduction in the total chip area. Besides, the use of a novel charge-pump circuit with partial positive feedback and current reuse allows a further reduction in both chip area and power consumption, making the proposed structure suitable for high frequency and low-voltage phase-locked loops. Figure 10. Transient response of the synthesizer.

Research paper thumbnail of BiCMOS opto-electronic reception system for application in high-frequencies

Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA... more Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA) structures based on the common-gate topology, using negative feedback with the integration of a silicon photodiode, are discussed. Simulations were performed using BSIM3V3, modified BSIM3v3, and EKV models for high-frequency applications. Experimental and simulation results were performed for a 0.8 µm Si BiCMOS AMS process, using HSPICE and CADENCE simulators. Experimental results, obtained from Sparameters, show a transimpedance gain of 40 dB and a bandwidth of 1.9 GHz.

Research paper thumbnail of Multiplier and method for mixing signals

Research paper thumbnail of BiCMOS opto-electronic reception system for application in high-frequencies

14th International Conference on Electronics, Communications and Computers, 2004. CONIELECOMP 2004., 2004

Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA... more Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA) structures based on the common-gate topology, using negative feedback with the integration of a silicon photodiode, are discussed. Simulations were performed using BSIM3V3, modified BSIM3v3, and EKV models for high-frequency applications. Experimental and simulation results were performed for a 0.8 µm Si BiCMOS AMS process, using HSPICE and CADENCE simulators. Experimental results, obtained from Sparameters, show a transimpedance gain of 40 dB and a bandwidth of 1.9 GHz.

Research paper thumbnail of Linearity in two optical receiver structures for high-frequency applications

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004., 2004

The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double ... more The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based on a wide-band PLL topology with a high reference frequency. This approach allows obtaining low phase noise, fast switching time, a low divider ratio and a reduction in the total chip area. Besides, the use of a novel charge-pump circuit with partial positive feedback and current reuse allows a further reduction in both chip area and power consumption, making the proposed structure suitable for high frequency and low-voltage phase-locked loops.

Research paper thumbnail of BiCMOS opto-electronic reception system for application in high-frequencies

14th International Conference on Electronics, Communications and Computers, 2004. CONIELECOMP 2004., 2004

Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA... more Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA) structures based on the common-gate topology, using negative feedback with the integration of a silicon photodiode, are discussed. Simulations were performed using BSIM3V3, modified BSIM3v3, and EKV models for high-frequency applications. Experimental and simulation results were performed for a 0.8 µm Si BiCMOS AMS process, using HSPICE and CADENCE simulators. Experimental results, obtained from Sparameters, show a transimpedance gain of 40 dB and a bandwidth of 1.9 GHz.

Research paper thumbnail of International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, April 22-25, 2019

Research paper thumbnail of Tuning circuit for an RC filter

Research paper thumbnail of Circuit and method for processing data

Research paper thumbnail of DC level shifting circuit for analog circuits

Research paper thumbnail of Radio Architecture with Dual Frequency Source Selection

Research paper thumbnail of Design, optimization and fabrication of a tanh/sinh-type bipolar transconductor with maximum linearity

Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)

We have designed, optimized and fabricated a bipolar transconductor with maximum static transfer ... more We have designed, optimized and fabricated a bipolar transconductor with maximum static transfer function linearity. The optimization was based on an analytic function that corresponds to the integral nonlinearity of the circuit. This transconductor is composed of two parallel-connected non-linear blocks: a hyperbolic tangent-type transconductor and hyperbolic sine-type transconductor. The transconductor was fabricated using 0.5 μm BiCMOS mixed-signal process. A minimum THD value of 0.2% was obtained with a 100 μs transconductance up to a maximum input voltage swing of 50 mV peak.

Research paper thumbnail of Building blocks for digital wireless communications in sub-micron technologies: an overview

Proceedings of the 1998 Second IEEE International Caracas Conference on Devices, Circuits and Systems. ICCDCS 98. On the 70th Anniversary of the MOSFET and 50th of the BJT. (Cat. No.98TH8350)

This paper presents an overview of both the basic building blocks and process technologies associ... more This paper presents an overview of both the basic building blocks and process technologies associated with silicon ICs for personal wireless communications. The technical challenges to achieve higher levels of RF monolithic integration at a low cost and with low power dissipation in battery-powered portable transceivers are presented. Specific emphasis will be given to applications in the 1 to 2

Research paper thumbnail of Design of an inphase and quadrature phase and amplitude imbalance compensation in quadrature receivers

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004.

ABSTRACT This paper presents a compensation technique for the amplitude and phase imbalance betwe... more ABSTRACT This paper presents a compensation technique for the amplitude and phase imbalance between the I and the Q components of a quadrature demodulator. The proposed scheme allows the implementation of a fully integrated self-aligned tuner for digital modulation systems such as QAM demodulation and receivers. It is based on a mixed signal analog/digital integrated circuit approach to automatically correct amplitude and phase imbalances resulting from mismatch of integrated circuit components. The approach presented uses the original signal information to create both a control signal for the amplitude and phase correction. It uses digital circuitry to compensate for mismatch errors, by means of an analog feedback mechanism, and perform high accuracy phase and amplitude quadrature correction.

Research paper thumbnail of Comments on “A sinh Resistor and Its Application to tanh Linearization&#8221

IEEE Journal of Solid-State Circuits, 2006

ABSTRACT

Research paper thumbnail of Design of an Inphase and Quadrature Phase and Amplitude Imbalance Compensation in Quadrature Receivers

This paper presents a compensation technique for the amplitude and phase imbalance between the I ... more This paper presents a compensation technique for the amplitude and phase imbalance between the I and the Q components of a quadrature demodulator. The proposed scheme allows the implementation of a fully integrated self-aligned tuner for digital modulation systems such as QAM demodulation and Zero-IF Receivers. It is based on a mixed signal analog/digital integrated circuit approach to automatically correct amplitude and phase imbalances resulting from mismatch of integrated circuit components. The approach presented uses the original digital signal information to create both a control signal for the amplitude and phase correction. It uses digital circuitry to compensate for mismatch errors, by means of an analog feedback mechanism, and perform high accuracy phase and amplitude quadrature correction.

Research paper thumbnail of Design of an Inphase and Quadrature Phase and Amplitude Imbalance Compensation in Quadrature Receivers

This paper presents a compensation technique for the amplitude and phase imbalance between the I ... more This paper presents a compensation technique for the amplitude and phase imbalance between the I and the Q components of a quadrature demodulator. The proposed scheme allows the implementation of a fully integrated self-aligned tuner for digital modulation systems such as QAM demodulation and Zero-IF Receivers. It is based on a mixed signal analog/digital integrated circuit approach to automatically correct amplitude and phase imbalances resulting from mismatch of integrated circuit components. The approach presented uses the original digital signal information to create both a control signal for the amplitude and phase correction. It uses digital circuitry to compensate for mismatch errors, by means of an analog feedback mechanism, and perform high accuracy phase and amplitude quadrature correction.

Research paper thumbnail of Design of an Inphase and Quadrature Phase and Amplitude Imbalance Compensation in Quadrature Receivers

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, Dominican Republic, Nov.3-5, 2004, 2004

This paper presents a compensation technique for the amplitude and phase imbalance between the I ... more This paper presents a compensation technique for the amplitude and phase imbalance between the I and the Q components of a quadrature demodulator. The proposed scheme allows the implementation of a fully integrated self-aligned tuner for digital modulation systems such as QAM demodulation and Zero-IF Receivers. It is based on a mixed signal analog/digital integrated circuit approach to automatically correct amplitude and phase imbalances resulting from mismatch of integrated circuit components. The approach presented uses the original digital signal information to create both a control signal for the amplitude and phase correction. It uses digital circuitry to compensate for mismatch errors, by means of an analog feedback mechanism, and perform high accuracy phase and amplitude quadrature correction.

Research paper thumbnail of Linearity in two optical receiver structures for high-frequency applications

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004., 2004

The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double ... more The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based on a wide-band PLL topology with a high reference frequency. This approach allows obtaining low phase noise, fast switching time, a low divider ratio and a reduction in the total chip area. Besides, the use of a novel charge-pump circuit with partial positive feedback and current reuse allows a further reduction in both chip area and power consumption, making the proposed structure suitable for high frequency and low-voltage phase-locked loops. Figure 10. Transient response of the synthesizer.

Research paper thumbnail of BiCMOS opto-electronic reception system for application in high-frequencies

Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA... more Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA) structures based on the common-gate topology, using negative feedback with the integration of a silicon photodiode, are discussed. Simulations were performed using BSIM3V3, modified BSIM3v3, and EKV models for high-frequency applications. Experimental and simulation results were performed for a 0.8 µm Si BiCMOS AMS process, using HSPICE and CADENCE simulators. Experimental results, obtained from Sparameters, show a transimpedance gain of 40 dB and a bandwidth of 1.9 GHz.

Research paper thumbnail of Multiplier and method for mixing signals

Research paper thumbnail of BiCMOS opto-electronic reception system for application in high-frequencies

14th International Conference on Electronics, Communications and Computers, 2004. CONIELECOMP 2004., 2004

Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA... more Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA) structures based on the common-gate topology, using negative feedback with the integration of a silicon photodiode, are discussed. Simulations were performed using BSIM3V3, modified BSIM3v3, and EKV models for high-frequency applications. Experimental and simulation results were performed for a 0.8 µm Si BiCMOS AMS process, using HSPICE and CADENCE simulators. Experimental results, obtained from Sparameters, show a transimpedance gain of 40 dB and a bandwidth of 1.9 GHz.

Research paper thumbnail of Linearity in two optical receiver structures for high-frequency applications

Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004., 2004

The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double ... more The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based on a wide-band PLL topology with a high reference frequency. This approach allows obtaining low phase noise, fast switching time, a low divider ratio and a reduction in the total chip area. Besides, the use of a novel charge-pump circuit with partial positive feedback and current reuse allows a further reduction in both chip area and power consumption, making the proposed structure suitable for high frequency and low-voltage phase-locked loops.

Research paper thumbnail of BiCMOS opto-electronic reception system for application in high-frequencies

14th International Conference on Electronics, Communications and Computers, 2004. CONIELECOMP 2004., 2004

Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA... more Two opto-electronics integrated circuits (OEIC) are presented. CMOS transimpedance amplifier (TIA) structures based on the common-gate topology, using negative feedback with the integration of a silicon photodiode, are discussed. Simulations were performed using BSIM3V3, modified BSIM3v3, and EKV models for high-frequency applications. Experimental and simulation results were performed for a 0.8 µm Si BiCMOS AMS process, using HSPICE and CADENCE simulators. Experimental results, obtained from Sparameters, show a transimpedance gain of 40 dB and a bandwidth of 1.9 GHz.