Luís Vitório Cargnini - Academia.edu (original) (raw)
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Papers by Luís Vitório Cargnini
Abstract: Static random access memory (SRAM) is the most commonly employed semiconductor in the d... more Abstract: Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded syst...
... After, the TC is encoded using the error correcting code BCH. ... In [15], the authors presen... more ... After, the TC is encoded using the error correcting code BCH. ... In [15], the authors present a high level technique based on correcting codes to protect SRAM memories ... Their technique combines Reed Solomon code and Hamming code to assure reliability in presence of multiple ...
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2010 International Conference on Reconfigurable Computing and FPGAs, 2010
2011 21st International Conference on Field Programmable Logic and Applications, 2011
ABSTRACT Optimizing a processor for FPGA architectures is a challenging task. In this paper, we a... more ABSTRACT Optimizing a processor for FPGA architectures is a challenging task. In this paper, we attempt to bridge the performance gap between commercial and open-source processors by introducing various design and implementation strategies at the register transfer abstraction level, where most optimizations require several design trade-offs to ensure an efficient and proper use of available resources. Using an open-source processor as a case study, we demonstrate the effectiveness of the proposed methods through a set of synthesis and benchmark results.
2007 International Multi-Conference on Computing in the Global Information Technology (ICCGI'07), 2007
... ap-proach will lead to a smaller hardware and a expressive speed up, in contrast with computi... more ... ap-proach will lead to a smaller hardware and a expressive speed up, in contrast with computing algorithms (like Berlekamp-Massey, for instance) even in a HDL version. II. BOSE-CHAUDHURI-HOCQUENGHEM (BCH) In 1948 Claude Elwood Shannon published the paper ...
Parallel and Distributed …, 2011
... Lyonel Barthe, Luıs Vitório Cargnini, Pascal Benoit, Lionel Torres LIRMM, UMR 5506, CNRS Univ... more ... Lyonel Barthe, Luıs Vitório Cargnini, Pascal Benoit, Lionel Torres LIRMM, UMR 5506, CNRS University of Montpellier 2 161, rue Ada, 34392 Montpellier ... They are implemented using a dual-port synchronous RAM template, inferring, for instance, Block RAMs for Xilinx's FPGAs. ...
2013 IEEE Faible Tension Faible Consommation, 2013
Abstract: Static random access memory (SRAM) is the most commonly employed semiconductor in the d... more Abstract: Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded syst...
... After, the TC is encoded using the error correcting code BCH. ... In [15], the authors presen... more ... After, the TC is encoded using the error correcting code BCH. ... In [15], the authors present a high level technique based on correcting codes to protect SRAM memories ... Their technique combines Reed Solomon code and Hamming code to assure reliability in presence of multiple ...
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2010 International Conference on Reconfigurable Computing and FPGAs, 2010
2011 21st International Conference on Field Programmable Logic and Applications, 2011
ABSTRACT Optimizing a processor for FPGA architectures is a challenging task. In this paper, we a... more ABSTRACT Optimizing a processor for FPGA architectures is a challenging task. In this paper, we attempt to bridge the performance gap between commercial and open-source processors by introducing various design and implementation strategies at the register transfer abstraction level, where most optimizations require several design trade-offs to ensure an efficient and proper use of available resources. Using an open-source processor as a case study, we demonstrate the effectiveness of the proposed methods through a set of synthesis and benchmark results.
2007 International Multi-Conference on Computing in the Global Information Technology (ICCGI'07), 2007
... ap-proach will lead to a smaller hardware and a expressive speed up, in contrast with computi... more ... ap-proach will lead to a smaller hardware and a expressive speed up, in contrast with computing algorithms (like Berlekamp-Massey, for instance) even in a HDL version. II. BOSE-CHAUDHURI-HOCQUENGHEM (BCH) In 1948 Claude Elwood Shannon published the paper ...
Parallel and Distributed …, 2011
... Lyonel Barthe, Luıs Vitório Cargnini, Pascal Benoit, Lionel Torres LIRMM, UMR 5506, CNRS Univ... more ... Lyonel Barthe, Luıs Vitório Cargnini, Pascal Benoit, Lionel Torres LIRMM, UMR 5506, CNRS University of Montpellier 2 161, rue Ada, 34392 Montpellier ... They are implemented using a dual-port synchronous RAM template, inferring, for instance, Block RAMs for Xilinx's FPGAs. ...
2013 IEEE Faible Tension Faible Consommation, 2013
The present discloses a method for detection and correction of errors, based on the proposition o... more The present discloses a method for detection and correction of errors, based on the proposition of multidimensional error correcting code, presenting the first example of implementation of MECC called BCHMD, that employ the BCH or BCH algebraic in each dimension of the set of symbols in the encoder and decoder sides of the communication system, in the error correcting code stage. Especially the described method claimed by the present invention embraces bits in different dimensions, which improves performance, speed and capacity in the ECC.