Lynn Cai - Academia.edu (original) (raw)

Papers by Lynn Cai

Research paper thumbnail of Fuzzy classifications using fuzzy inference networks

IEEE transactions on systems, man, and cybernetics, Jun 1, 1998

Research paper thumbnail of A novel processing platform for post tape out flows

As the computational requirements for post tape out (PTO) flows increase at the 7nm and below tec... more As the computational requirements for post tape out (PTO) flows increase at the 7nm and below technology nodes, there is a need to increase the scalability of the computational tools in order to reduce the turn-around time (TAT) of the flows. Utilization of design hierarchy has been one proven method to provide sufficient partitioning to enable PTO processing. However, as the data is processed through the PTO flow, its effective hierarchy is reduced. The reduction is necessary to achieve the desired accuracy. Also, the sequential nature of the PTO flow is inherently non-scalable. To address these limitations, we are proposing a quasi-hierarchical solution that combines multiple levels of parallelism to increase the scalability of the entire PTO flow. In this paper, we describe the system and present experimental results demonstrating the runtime reduction through scalable processing with thousands of computational cores.

Research paper thumbnail of A fuzzy inference network for classification

1995 International Conference on Acoustics, Speech, and Signal Processing

A fuzzy inference network (FIN) is proposed. The proposed FIN preserves the advantages of both fu... more A fuzzy inference network (FIN) is proposed. The proposed FIN preserves the advantages of both fuzzy classification algorithm and neural networks. It can learn membership functions directly from training samples and classify patterns according to the membership values. As efficient self-organizing learning algorithm is also presented.

Research paper thumbnail of Supervised fuzzy inference network for invariant pattern recognition

Midwest Symposium on Circuits and Systems, 2000

A supervised fuzzy inference network (FIN) model and its learning algorithm for invariant pattern... more A supervised fuzzy inference network (FIN) model and its learning algorithm for invariant pattern recognition are presented in this paper. This fuzzy inference network is suitable for 2-D visual pattern recognition problems and has been tested with letter patterns of black and white pixel values. In contrast to most of the conventional pattern recognition systems, the proposed fuzzy inference network

Research paper thumbnail of Simultaneous layout, process, and model optimization within an integrated design-for-yield environment

SPIE Proceedings, 2006

Trends in the design feature shrinking that outrun the progress in the lithography technologies r... more Trends in the design feature shrinking that outrun the progress in the lithography technologies require critical efforts in the layout, process, and model development. Printing a layout is no longer a problem only for the lithographers; it has penetrated into the layout stage as well. Layout patterns are getting more aggressive, raising serious printability concerns. This requires very accurate models

Research paper thumbnail of A fuzzy neural classifier for pattern classificatoin

1993 IEEE International Symposium on Circuits and Systems

A novel fuzzy neural classifier (FNC) and its learning algorithm are proposed. This FNC can learn... more A novel fuzzy neural classifier (FNC) and its learning algorithm are proposed. This FNC can learn the membership function of each fuzzy class from training samples. The learning speed of the FNC is fast. Simulation results on the learning and estimation of the membership functions of one-dimensional samples are presented

Research paper thumbnail of Fuzzy classifications using fuzzy inference networks

IEEE Transactions on Systems, Man and Cybernetics, Part B (Cybernetics), 1998

Research paper thumbnail of A fuzzy neural network and its application to pattern recognition

IEEE Transactions on Fuzzy Systems, 1994

Research paper thumbnail of Low k 1 logic design using gridded design rules

Proceedings of SPIE, Mar 14, 2008

Research paper thumbnail of Defect printability analysis study using virtual stepper system in a production environment

Proceedings of SPIE, Jul 1, 2002

In this paper the simulation of wafer images for Attenuated Phase Shift Masks (ATTPSM) and repair... more In this paper the simulation of wafer images for Attenuated Phase Shift Masks (ATTPSM) and repaired binary masks are performed by Virtual Stepper System in a real production environment. In addition, the Automatic Defect Severity Scoring module in Virtual Stepper is also used to calculate the defect severity score for each defect. ADSS provides an overall score that quantifies the

Research paper thumbnail of Low k 1 logic design using gridded design rules

Research paper thumbnail of <title>Automated Defect Severity Analysis for Binary and PSM Mask Defects</title>

22nd Annual BACUS Symposium on Photomask Technology, 2002

Traditionally, mask defect analysis has been done through a visual inspection review. As the semi... more Traditionally, mask defect analysis has been done through a visual inspection review. As the semiconductor industry moves into smaller process generations and the complexity of mask exponentially increases, the traditional mask defect analysis method becomes very time consuming. The Automatic Defect Severity Scoring (ADSS) module of i-Virtual Stepper System from Numerical Technologies offers an extremely fast and highly accurate software solution for defect printability analysis of advanced masks such as OPC and phase-shifting masks in a real production environment. In a previous paper [1], we have introduced the ADSS concept and discussed some results for line-space patterns on OPC and non-OPC masks. In this paper, we will discuss the ADSS results for both line-space and contact patterns on attenuated phase-shifting masks (ATTPSM), together with some ADSS results for line-space patterns on binary masks. The ADSS results are compared to wafer results. The wafer exposures were performed using 248 nm imaging technology and inspection images were generated on a KLA-Tencor’s SLF27 system.

Research paper thumbnail of Simulation-based mask quality control in a production environment

Metrology, Inspection, and Process Control for Microlithography XVIII, 2004

Traditionally, mask defect analysis has been done through a visual inspection review. As the semi... more Traditionally, mask defect analysis has been done through a visual inspection review. As the semiconductor industry moves into smaller process generations and the complexity of mask exponentially increases, &amp;amp;amp;amp;amp;amp;quot;Mask&amp;amp;amp;amp;amp;amp;quot; issues have emerged as one of the main production problems due to their rising cost and long turn-around time. Mask-making specifications related to defects found on advanced masks also becomes more

Research paper thumbnail of Enhanced dispositioning of reticle defects using the Virtual Stepper with automated defect severity scoring

Photomask and Next-Generation Lithography Mask Technology VIII, 2001

Enhanced dispositioning of reticle defects using the Virtual Stepper with automated defect severi... more Enhanced dispositioning of reticle defects using the Virtual Stepper with automated defect severity scoring. [Proceedings of SPIE 4409, 467 (2001)]. Lynn Cai, Khoi A. Phan, Chris A. Spence, Linyong Pang, Kevin K. Chan. Abstract. ...

Research paper thumbnail of <title>Automatic defect severity scoring for 193-nm reticle defect inspection</title>

Optical Microlithography XIV, 2001

Sub-wavelength lithography requires knowledgeable application of resolution enhancement technique... more Sub-wavelength lithography requires knowledgeable application of resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and phase shift mask (PSM). Use of RETs, in turn, requires that new photomask specifications and special requirements for mask defect printability be taken into consideration. This is especially true, as the photomask's critical dimensions become more aggressive (400 nm moving toward 300 nm). Traditionally, mask defect analysis and subsequent defect disposition has been accomplished by first performing automated reticle inspection, and then by visual inspection ultimately dependent on operator judgement. As the semiconductor industry moves to more challenging process generations this methodology is no longer viable for assessing the impact of a defect on the printed wafer. New techniques for more accurate, production-worthy defect printability analysis and defect disposition procedures are required. Developed at Numerical Technologies, Inc. is the Virtual StepperTM System that offers a fast, accurate software solution for defect printability analysis based on state-of- the-art lithography simulation techniques for advanced masks production using OPC and PSM. The newly developed Virtual Stepper System feature, Automatic Defect Severity Scoring (ADSS) provides fully automated and accurate defect impact analysis capability by calculating a consistent Defect Severity Score (DSS) for each defect detected by an inspection tool. DSS is an overall score that quantifies the impact of a given defect on surrounding features and can be used as a comprehensive indicator of defect printability. Taken into consideration, are not only printing defects, but defects which cause critical dimension (CD) errors altering a given process window.

Research paper thumbnail of <title>Enhanced dispositioning of reticle defects for advanced masks using virtual stepper with automated defect severity scoring</title>

23rd Annual BACUS Symposium on Photomask Technology, 2003

As the semiconductor industry continues to scale down critical dimensions (CD), proximity effects... more As the semiconductor industry continues to scale down critical dimensions (CD), proximity effects get more and more severe. As such, aggressive Optical Proximity Correction (OPC) features like hammerheads, serifs and assist bars inevitably appear on fabricated masks. The great challenge, however -- to reliably assure the quality of these advanced masks -- is to be able to directly judge a

Research paper thumbnail of <title>Defect printability analysis study using virtual stepper system in a production environment</title>

Metrology, Inspection, and Process Control for Microlithography XVI, 2002

ABSTRACT

Research paper thumbnail of System and method of providing mask quality control

Research paper thumbnail of System and method of providing mask defect printability analysis

Research paper thumbnail of A novel processing platform for post tape out flows

Optical Microlithography XXXI, 2018

As the computational requirements for post tape out (PTO) flows increase at the 7nm and below tec... more As the computational requirements for post tape out (PTO) flows increase at the 7nm and below technology nodes, there is a need to increase the scalability of the computational tools in order to reduce the turn-around time (TAT) of the flows. Utilization of design hierarchy has been one proven method to provide sufficient partitioning to enable PTO processing. However, as the data is processed through the PTO flow, its effective hierarchy is reduced. The reduction is necessary to achieve the desired accuracy. Also, the sequential nature of the PTO flow is inherently non-scalable. To address these limitations, we are proposing a quasi-hierarchical solution that combines multiple levels of parallelism to increase the scalability of the entire PTO flow. In this paper, we describe the system and present experimental results demonstrating the runtime reduction through scalable processing with thousands of computational cores.

Research paper thumbnail of Fuzzy classifications using fuzzy inference networks

IEEE transactions on systems, man, and cybernetics, Jun 1, 1998

Research paper thumbnail of A novel processing platform for post tape out flows

As the computational requirements for post tape out (PTO) flows increase at the 7nm and below tec... more As the computational requirements for post tape out (PTO) flows increase at the 7nm and below technology nodes, there is a need to increase the scalability of the computational tools in order to reduce the turn-around time (TAT) of the flows. Utilization of design hierarchy has been one proven method to provide sufficient partitioning to enable PTO processing. However, as the data is processed through the PTO flow, its effective hierarchy is reduced. The reduction is necessary to achieve the desired accuracy. Also, the sequential nature of the PTO flow is inherently non-scalable. To address these limitations, we are proposing a quasi-hierarchical solution that combines multiple levels of parallelism to increase the scalability of the entire PTO flow. In this paper, we describe the system and present experimental results demonstrating the runtime reduction through scalable processing with thousands of computational cores.

Research paper thumbnail of A fuzzy inference network for classification

1995 International Conference on Acoustics, Speech, and Signal Processing

A fuzzy inference network (FIN) is proposed. The proposed FIN preserves the advantages of both fu... more A fuzzy inference network (FIN) is proposed. The proposed FIN preserves the advantages of both fuzzy classification algorithm and neural networks. It can learn membership functions directly from training samples and classify patterns according to the membership values. As efficient self-organizing learning algorithm is also presented.

Research paper thumbnail of Supervised fuzzy inference network for invariant pattern recognition

Midwest Symposium on Circuits and Systems, 2000

A supervised fuzzy inference network (FIN) model and its learning algorithm for invariant pattern... more A supervised fuzzy inference network (FIN) model and its learning algorithm for invariant pattern recognition are presented in this paper. This fuzzy inference network is suitable for 2-D visual pattern recognition problems and has been tested with letter patterns of black and white pixel values. In contrast to most of the conventional pattern recognition systems, the proposed fuzzy inference network

Research paper thumbnail of Simultaneous layout, process, and model optimization within an integrated design-for-yield environment

SPIE Proceedings, 2006

Trends in the design feature shrinking that outrun the progress in the lithography technologies r... more Trends in the design feature shrinking that outrun the progress in the lithography technologies require critical efforts in the layout, process, and model development. Printing a layout is no longer a problem only for the lithographers; it has penetrated into the layout stage as well. Layout patterns are getting more aggressive, raising serious printability concerns. This requires very accurate models

Research paper thumbnail of A fuzzy neural classifier for pattern classificatoin

1993 IEEE International Symposium on Circuits and Systems

A novel fuzzy neural classifier (FNC) and its learning algorithm are proposed. This FNC can learn... more A novel fuzzy neural classifier (FNC) and its learning algorithm are proposed. This FNC can learn the membership function of each fuzzy class from training samples. The learning speed of the FNC is fast. Simulation results on the learning and estimation of the membership functions of one-dimensional samples are presented

Research paper thumbnail of Fuzzy classifications using fuzzy inference networks

IEEE Transactions on Systems, Man and Cybernetics, Part B (Cybernetics), 1998

Research paper thumbnail of A fuzzy neural network and its application to pattern recognition

IEEE Transactions on Fuzzy Systems, 1994

Research paper thumbnail of Low k 1 logic design using gridded design rules

Proceedings of SPIE, Mar 14, 2008

Research paper thumbnail of Defect printability analysis study using virtual stepper system in a production environment

Proceedings of SPIE, Jul 1, 2002

In this paper the simulation of wafer images for Attenuated Phase Shift Masks (ATTPSM) and repair... more In this paper the simulation of wafer images for Attenuated Phase Shift Masks (ATTPSM) and repaired binary masks are performed by Virtual Stepper System in a real production environment. In addition, the Automatic Defect Severity Scoring module in Virtual Stepper is also used to calculate the defect severity score for each defect. ADSS provides an overall score that quantifies the

Research paper thumbnail of Low k 1 logic design using gridded design rules

Research paper thumbnail of <title>Automated Defect Severity Analysis for Binary and PSM Mask Defects</title>

22nd Annual BACUS Symposium on Photomask Technology, 2002

Traditionally, mask defect analysis has been done through a visual inspection review. As the semi... more Traditionally, mask defect analysis has been done through a visual inspection review. As the semiconductor industry moves into smaller process generations and the complexity of mask exponentially increases, the traditional mask defect analysis method becomes very time consuming. The Automatic Defect Severity Scoring (ADSS) module of i-Virtual Stepper System from Numerical Technologies offers an extremely fast and highly accurate software solution for defect printability analysis of advanced masks such as OPC and phase-shifting masks in a real production environment. In a previous paper [1], we have introduced the ADSS concept and discussed some results for line-space patterns on OPC and non-OPC masks. In this paper, we will discuss the ADSS results for both line-space and contact patterns on attenuated phase-shifting masks (ATTPSM), together with some ADSS results for line-space patterns on binary masks. The ADSS results are compared to wafer results. The wafer exposures were performed using 248 nm imaging technology and inspection images were generated on a KLA-Tencor’s SLF27 system.

Research paper thumbnail of Simulation-based mask quality control in a production environment

Metrology, Inspection, and Process Control for Microlithography XVIII, 2004

Traditionally, mask defect analysis has been done through a visual inspection review. As the semi... more Traditionally, mask defect analysis has been done through a visual inspection review. As the semiconductor industry moves into smaller process generations and the complexity of mask exponentially increases, &amp;amp;amp;amp;amp;amp;quot;Mask&amp;amp;amp;amp;amp;amp;quot; issues have emerged as one of the main production problems due to their rising cost and long turn-around time. Mask-making specifications related to defects found on advanced masks also becomes more

Research paper thumbnail of Enhanced dispositioning of reticle defects using the Virtual Stepper with automated defect severity scoring

Photomask and Next-Generation Lithography Mask Technology VIII, 2001

Enhanced dispositioning of reticle defects using the Virtual Stepper with automated defect severi... more Enhanced dispositioning of reticle defects using the Virtual Stepper with automated defect severity scoring. [Proceedings of SPIE 4409, 467 (2001)]. Lynn Cai, Khoi A. Phan, Chris A. Spence, Linyong Pang, Kevin K. Chan. Abstract. ...

Research paper thumbnail of <title>Automatic defect severity scoring for 193-nm reticle defect inspection</title>

Optical Microlithography XIV, 2001

Sub-wavelength lithography requires knowledgeable application of resolution enhancement technique... more Sub-wavelength lithography requires knowledgeable application of resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and phase shift mask (PSM). Use of RETs, in turn, requires that new photomask specifications and special requirements for mask defect printability be taken into consideration. This is especially true, as the photomask's critical dimensions become more aggressive (400 nm moving toward 300 nm). Traditionally, mask defect analysis and subsequent defect disposition has been accomplished by first performing automated reticle inspection, and then by visual inspection ultimately dependent on operator judgement. As the semiconductor industry moves to more challenging process generations this methodology is no longer viable for assessing the impact of a defect on the printed wafer. New techniques for more accurate, production-worthy defect printability analysis and defect disposition procedures are required. Developed at Numerical Technologies, Inc. is the Virtual StepperTM System that offers a fast, accurate software solution for defect printability analysis based on state-of- the-art lithography simulation techniques for advanced masks production using OPC and PSM. The newly developed Virtual Stepper System feature, Automatic Defect Severity Scoring (ADSS) provides fully automated and accurate defect impact analysis capability by calculating a consistent Defect Severity Score (DSS) for each defect detected by an inspection tool. DSS is an overall score that quantifies the impact of a given defect on surrounding features and can be used as a comprehensive indicator of defect printability. Taken into consideration, are not only printing defects, but defects which cause critical dimension (CD) errors altering a given process window.

Research paper thumbnail of <title>Enhanced dispositioning of reticle defects for advanced masks using virtual stepper with automated defect severity scoring</title>

23rd Annual BACUS Symposium on Photomask Technology, 2003

As the semiconductor industry continues to scale down critical dimensions (CD), proximity effects... more As the semiconductor industry continues to scale down critical dimensions (CD), proximity effects get more and more severe. As such, aggressive Optical Proximity Correction (OPC) features like hammerheads, serifs and assist bars inevitably appear on fabricated masks. The great challenge, however -- to reliably assure the quality of these advanced masks -- is to be able to directly judge a

Research paper thumbnail of <title>Defect printability analysis study using virtual stepper system in a production environment</title>

Metrology, Inspection, and Process Control for Microlithography XVI, 2002

ABSTRACT

Research paper thumbnail of System and method of providing mask quality control

Research paper thumbnail of System and method of providing mask defect printability analysis

Research paper thumbnail of A novel processing platform for post tape out flows

Optical Microlithography XXXI, 2018

As the computational requirements for post tape out (PTO) flows increase at the 7nm and below tec... more As the computational requirements for post tape out (PTO) flows increase at the 7nm and below technology nodes, there is a need to increase the scalability of the computational tools in order to reduce the turn-around time (TAT) of the flows. Utilization of design hierarchy has been one proven method to provide sufficient partitioning to enable PTO processing. However, as the data is processed through the PTO flow, its effective hierarchy is reduced. The reduction is necessary to achieve the desired accuracy. Also, the sequential nature of the PTO flow is inherently non-scalable. To address these limitations, we are proposing a quasi-hierarchical solution that combines multiple levels of parallelism to increase the scalability of the entire PTO flow. In this paper, we describe the system and present experimental results demonstrating the runtime reduction through scalable processing with thousands of computational cores.