M. Boulé - Academia.edu (original) (raw)

Papers by M. Boulé

2008 IEEE International High Level Design Validation and Test Workshop, 2008

Modern assertion languages, such as PSL and SVA, include many constructs that are best handled by... more Modern assertion languages, such as PSL and SVA, include many constructs that are best handled by rewriting to a small set of base cases. Since previous rewrite attempts have shown that the rules could be quite involved, sometimes counterintuitive, and that they can make a significant difference in the complexity of interpreting assertions, workable procedures for proving the correctness of these rules must be established. In this paper, we outline the methodology for computer-assisted proofs of a set of previously published rewrite rules for PSL properties. We show how to express PSL's syntax and semantics in the PVS theorem prover, and proceed to prove the correctness of a set of thirty rewrite rules. In doing so, we also demonstrate how to circumvent issues with PSL semantics regarding the never and eventually! operators.

Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09, 2009

To assist in dynamic assertion-based verification, we present a method to automatically build a t... more To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monitors and generators, we have extended the monitor generator tool MBAC to produce synthesizable on-line generators. We have tested the resulting generators in simulation and by emulation on an FPGA. The combination of multiple generators provides an efficient way to model the environment of modules within a DUT, facilitating an equivalent of software "unit testing" under real conditions, early in the design flow.

IET Computers & Digital Techniques, 2007

Although assertions are a great tool for aiding debugging in the design and implementation verifi... more Although assertions are a great tool for aiding debugging in the design and implementation verification stages, their use in silicon debug has been limited so far. A set of techniques for debugging with the assertions in either pre-silicon or post-silicon scenarios are discussed. Presented are features such as assertion threading, activity monitors, assertion and cover counters and completion mode assertions. The common goal of these checker enhancements is to provide better and more diversified ways to achieve visibility within the assertion circuits, which, in turn, lead to more efficient circuit debugging. Experimental results show that such modifications can be done with modest checker hardware overhead.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

Modern assertion languages such as property specification language (PSL) and SystemVerilog assert... more Modern assertion languages such as property specification language (PSL) and SystemVerilog assertions include many language constructs. By far, the most economical way to process the full languages in automated tools is to rewrite the majority of operators to a small set of base cases, which are then processed in an efficient way. Since recent rewrite attempts in the literature have shown that the rules could be quite involved, sometimes counterintuitive, and that they can make a significant difference in the complexity of interpreting assertions, ensuring that the rewrite rules are correct is a major contribution toward ensuring that the tools are correct, and even that the semantics of the assertion languages are well founded. This paper outlines the methodology for computer-assisted proofs of several publicly known rewrite rules for PSL properties. We first present the ways to express the PSL syntax and semantics in the prototype verification system (PVS) theorem prover, and then prove or disprove the correctness of over 50 rewrite rules published without proofs in various sources in the literature. In doing so, we also demonstrate how to circumvent known issues with PSL semantics regarding the never and eventually! operators, and offer our proposals on assertion language semantics.

In this paper, we present a methodology to use assertions in network-based designs to facilitate ... more In this paper, we present a methodology to use assertions in network-based designs to facilitate debugging and monitoring of SoCs. We rely on our assertion-checker generator (MBAC) to produce efficient RTL-level checkers from high-level temporal assertions, with optional debugging features. We further have built tools to encapsulate the source design with assertion checkers generated by MBAC and to coordinate the sending of management flits. Further details of the debug infrastructure are presented as well.

2008 IEEE International High Level Design Validation and Test Workshop, 2008

Modern assertion languages, such as PSL and SVA, include many constructs that are best handled by... more Modern assertion languages, such as PSL and SVA, include many constructs that are best handled by rewriting to a small set of base cases. Since previous rewrite attempts have shown that the rules could be quite involved, sometimes counterintuitive, and that they can make a significant difference in the complexity of interpreting assertions, workable procedures for proving the correctness of these rules must be established. In this paper, we outline the methodology for computer-assisted proofs of a set of previously published rewrite rules for PSL properties. We show how to express PSL's syntax and semantics in the PVS theorem prover, and proceed to prove the correctness of a set of thirty rewrite rules. In doing so, we also demonstrate how to circumvent issues with PSL semantics regarding the never and eventually! operators.

Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09, 2009

To assist in dynamic assertion-based verification, we present a method to automatically build a t... more To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monitors and generators, we have extended the monitor generator tool MBAC to produce synthesizable on-line generators. We have tested the resulting generators in simulation and by emulation on an FPGA. The combination of multiple generators provides an efficient way to model the environment of modules within a DUT, facilitating an equivalent of software "unit testing" under real conditions, early in the design flow.

IET Computers & Digital Techniques, 2007

Although assertions are a great tool for aiding debugging in the design and implementation verifi... more Although assertions are a great tool for aiding debugging in the design and implementation verification stages, their use in silicon debug has been limited so far. A set of techniques for debugging with the assertions in either pre-silicon or post-silicon scenarios are discussed. Presented are features such as assertion threading, activity monitors, assertion and cover counters and completion mode assertions. The common goal of these checker enhancements is to provide better and more diversified ways to achieve visibility within the assertion circuits, which, in turn, lead to more efficient circuit debugging. Experimental results show that such modifications can be done with modest checker hardware overhead.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

Modern assertion languages such as property specification language (PSL) and SystemVerilog assert... more Modern assertion languages such as property specification language (PSL) and SystemVerilog assertions include many language constructs. By far, the most economical way to process the full languages in automated tools is to rewrite the majority of operators to a small set of base cases, which are then processed in an efficient way. Since recent rewrite attempts in the literature have shown that the rules could be quite involved, sometimes counterintuitive, and that they can make a significant difference in the complexity of interpreting assertions, ensuring that the rewrite rules are correct is a major contribution toward ensuring that the tools are correct, and even that the semantics of the assertion languages are well founded. This paper outlines the methodology for computer-assisted proofs of several publicly known rewrite rules for PSL properties. We first present the ways to express the PSL syntax and semantics in the prototype verification system (PVS) theorem prover, and then prove or disprove the correctness of over 50 rewrite rules published without proofs in various sources in the literature. In doing so, we also demonstrate how to circumvent known issues with PSL semantics regarding the never and eventually! operators, and offer our proposals on assertion language semantics.

In this paper, we present a methodology to use assertions in network-based designs to facilitate ... more In this paper, we present a methodology to use assertions in network-based designs to facilitate debugging and monitoring of SoCs. We rely on our assertion-checker generator (MBAC) to produce efficient RTL-level checkers from high-level temporal assertions, with optional debugging features. We further have built tools to encapsulate the source design with assertion checkers generated by MBAC and to coordinate the sending of management flits. Further details of the debug infrastructure are presented as well.