M. Bourcerie - Academia.edu (original) (raw)

Papers by M. Bourcerie

Research paper thumbnail of Algebraically structured colored Petri nets to model sequential processes

IEEE Transactions on Systems, Man and Cybernetics, Part B (Cybernetics), 1997

Sequential processes can hardly be modeled with Colored Petri Nets (CPN). Their standard function... more Sequential processes can hardly be modeled with Colored Petri Nets (CPN). Their standard functions (such as "Succ" and "Prec") can only describe simple cases whereas modeling a complex sequence requires the definition of a function via a cumbersome and static table. In order to overcome these limitations, we first introduce a mixed structure based upon CPN and FIFO queues; then, we define an isomorphism between the set of colors and a finite field Z/pZ enabling symbolic calculation using polynomials associated with arcs instead of linear functions mapping sets into sets. Finally, several examples illustrate their modeling capabilities including failure recovery.

Research paper thumbnail of Relaxable damage in hot-carrier stressing of n-MOS transistors-oxide traps in the near interfacial region of the gate oxide

IEEE Transactions on Electron Devices, 1990

An examination of the relaxable hot-carrier stressing damage indicates that the relaxation is due... more An examination of the relaxable hot-carrier stressing damage indicates that the relaxation is due to charge trapped in the oxide located within tunneling distance of the Si-SiO2 interface, which charges during stressing and discharges by tunneling back out into the silicon. Both hole and electron traps are involved. The traps can be filled, either by injecting charge into the oxide

Research paper thumbnail of Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2<or=V/sub g/>or=V/sub d/) during hot-carrier stressing of n-MOS transistors

IEEE Transactions on Electron Devices, 1990

... 2 V&#x27;) During Hot-Carrier Stressing of n-MOS Transistors ... Dynamic stressing of MOS... more ... 2 V&#x27;) During Hot-Carrier Stressing of n-MOS Transistors ... Dynamic stressing of MOS transistors [33] has confirmed that interface state creation in MOS devices re-quires the injection of both electrons and holes together in the oxide. ...

Research paper thumbnail of Dynamic channel hot-carrier degradation of NMOS transistors by enhanced electron-hole injection into the oxide

IEEE Electron Device Letters, 2000

ABSTRACT Hot-carrier stressing has been carried out on NMOS transistors under dynamic stressing c... more ABSTRACT Hot-carrier stressing has been carried out on NMOS transistors under dynamic stressing conditions in which the drain voltage is kept constant and a square wave is applied to the gate such that electrons are injected into the oxide during the upper part of the cycle, while the lower part is varied so as to vary the oxide hole current. It is found that maximum degradation occurs when the hole current is maximum, indicating that the injection of both holes and electrons into the oxide is necessary for enhanced surface state generation, and supporting the model by which the trapping of holes and the subsequent neutralization by injected electrons leads to the formation of interface states.

Research paper thumbnail of Hot-carrier stressing damage in wide and narrow LDD NMOS transistors

IEEE Electron Device Letters, 2000

ABSTRACT Hot-carrier stressing has been carried out on LDD (lightly doped drain) NMOS transistors... more ABSTRACT Hot-carrier stressing has been carried out on LDD (lightly doped drain) NMOS transistors with gate width as a variable. It is found that the damage is qualitatively different between the wide and narrow devices. To investigate the poststress damage, use is made of a hole injection phase to neutralize any trapped charge. It is shown that the narrow devices degrade predominately by charge trapping, whereas the wider devices show interface-state creation. It is further shown that the localization of the hot-carrier damage is different, being extended towards the source for electron trapping in the narrow devices, whereas the wide devices show interface states localized at the drain junction edge. It is suggested that the mechanical constraints arising from the proximity of the bird&#39;s-beak structure are responsible for the electron-trapping behavior.&lt; &gt;

Research paper thumbnail of Validation by Petri net of a new approach for the one machine problem with temporal functions of polynomial type

IFAC Proceedings Volumes, 2009

Research paper thumbnail of Simultaneous stabilization using evolutionary programming and uniform design technique

2001 IEEE International Conference on Systems, Man and Cybernetics. e-Systems and e-Man for Cybernetics in Cyberspace (Cat.No.01CH37236), 2001

ABSTRACT The problem of simultaneous stabilization by a linear dynamic controller for a finite co... more ABSTRACT The problem of simultaneous stabilization by a linear dynamic controller for a finite collection of plants is important in the area of robust control. It is still an open problem. Most of the current research results are about the existence conditions of the controller, but the computation for the design of the controller is very complicated, thus it is difficult to use for practical problems, especially in the case of multiple systems. A new evolutionary programming method based on a uniform design technique is proposed to solve this problem. Simulation results show that it is an acceptable method for this kind of hard problem

Research paper thumbnail of Complex sequencing by methods of interpolation in Z/pZ colored Petri nets

Proceedings 1995 INRIA/IEEE Symposium on Emerging Technologies and Factory Automation. ETFA'95, 1995

ABSTRACT The notion of scheduling is a subject that characterizes many contemporary processes. Ne... more ABSTRACT The notion of scheduling is a subject that characterizes many contemporary processes. Nevertheless, Petri nets do not present tool satisfying to realize a complex sequencing. The originality of this study is mainly the replacement of the structure of set, associated with colors, by a structure of field Z /p Z allowing to process the succession of colors with mathematics. We introduce an algebraic structure of colors isomorphic with a finite field Z /p Z and a succession law of polynomial type polynomials nets that can be identified to colored Petri net (CPN), except that the arc weights are not predefined, specific or static functions but polynomial functions. This new tool of Petri nets can now be used as basis for ulterior studies on scheduling. We note that this method offers the advantage to operate on complex models, allows dynamic model evolution of PN, and leads to prediction of interesting solutions in scheduling problems and real-time systems

Research paper thumbnail of Extension of chaos anticontrol applied to the improvement of switch-mode power supply electromagnetic compatibility

2004 IEEE International Symposium on Industrial Electronics, 2004

Research paper thumbnail of Research strategy as the main catalyst for organizational development

IEMC '03 Proceedings. Managing Technologically Driven Organizations: The Human Side of Innovation and Change, 2003

Page 1. Research Strategy as the Main Catalyst for Organizational Development Radu Constantin Vla... more Page 1. Research Strategy as the Main Catalyst for Organizational Development Radu Constantin Vlad Jean-Yves Morel Marc Bourcerie Technical University of Cluj-Napoca University of Angers University of Angers Radu.Constantin ...

Research paper thumbnail of Effective management of large networks through the petri nets-discrete event simulation dualism

2004 IEEE International Conference on Systems, Man and Cybernetics (IEEE Cat. No.04CH37583), 2004

Page 1. 2004 IEEE International Conference on Systems, Man and Cybernetics Effective Management o... more Page 1. 2004 IEEE International Conference on Systems, Man and Cybernetics Effective Management of Large Networks Through the Petri Nets-Discrete Event Simulation Dualism * Radu C. Wad Management and Systems ...

Research paper thumbnail of Electrical and Optical Spectroscopic Characterization of Oxide Traps Induced by Hot Hole Injection

ESSDERC ’89, 1989

ABSTRACT For a better understanding of defects induced by hot carrier stressing in NMOS transisto... more ABSTRACT For a better understanding of defects induced by hot carrier stressing in NMOS transistors, the effect of emission enhanced by electric field (Poole-Frenkel effect) and the photodepopulation spectroscopy are used to characterize the traps in the thin gate oxide.

Research paper thumbnail of Z/pZ Petri nets model with application to an electroplating line

2001 IEEE International Conference on Systems, Man and Cybernetics. e-Systems and e-Man for Cybernetics in Cyberspace (Cat.No.01CH37236), 2001

The notion of scheduling is a subject that characterizes many contemporary processes. However, Pe... more The notion of scheduling is a subject that characterizes many contemporary processes. However, Petri nets do not represent a tool to realize a complex sequencing. The originality of this study is mainly the replacement of the structure, associated with colors, by a structure of field Z/pZ that allows the processing of colors succession with mathematics. We propose in this paper

Research paper thumbnail of The Voltage Dependence of Degradation in nMOS Transistors

Science & Sports - SCI SPORT, 1987

Hot carrier stressing has been carried out on silicon n-MOS devices as a function of gate voltage... more Hot carrier stressing has been carried out on silicon n-MOS devices as a function of gate voltage, at fixed drain voltages. It is found that a maximum of degradation occurs not only at Vq=Vd/2, but also at Vq=Vd. It is further found that the time power law for threshold voltage shift changes according to the voltage ratio. It is suggested that while the first peak is due to interface state degradation, the second is due to another process, possibly electron trapping in the oxide.

Research paper thumbnail of Improvement of Power Supply Electromagnetic Compatibility by Extension of Chaos Anticontrol

Journal of Circuits, Systems and Computers, 2005

ABSTRACT Switch-mode power supplies usually emit electromagnetic interferences at the switching f... more ABSTRACT Switch-mode power supplies usually emit electromagnetic interferences at the switching frequency and its harmonics. Inducing chaos in these systems has recently been suggested as a means of reducing these spectral emissions, yet at the expense of aggravating the overall magnitude of the ripple in the output voltage. We propose here a new nonlinear feedback control method, which induces chaos, and which is able at the same time to achieve low spectral emission and to maintain a small ripple in the output. The feasibility and usefulness of this new and simple method is shown here with a numerical example, which includes a comparison with the previous control method.

Research paper thumbnail of Relaxable damage in hot-carrier stressing of n-MOS transistors-oxide traps in the near interfacial region of the gate oxide

IEEE Transactions on Electron Devices, 1990

An examination of the relaxable hot-carrier stressing damage indicates that the relaxation is due... more An examination of the relaxable hot-carrier stressing damage indicates that the relaxation is due to charge trapped in the oxide located within tunneling distance of the Si-SiO2 interface, which charges during stressing and discharges by tunneling back out into the silicon. Both hole and electron traps are involved. The traps can be filled, either by injecting charge into the oxide

Research paper thumbnail of Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2<or=V/sub g/>or=V/sub d/) during hot-carrier stressing of n-MOS transistors

IEEE Transactions on Electron Devices, 1990

... 2 V&#x27;) During Hot-Carrier Stressing of n-MOS Transistors ... Dynamic stressing of MOS... more ... 2 V&#x27;) During Hot-Carrier Stressing of n-MOS Transistors ... Dynamic stressing of MOS transistors [33] has confirmed that interface state creation in MOS devices re-quires the injection of both electrons and holes together in the oxide. ...

Research paper thumbnail of Dynamic channel hot-carrier degradation of NMOS transistors by enhanced electron-hole injection into the oxide

IEEE Electron Device Letters, 2000

ABSTRACT Hot-carrier stressing has been carried out on NMOS transistors under dynamic stressing c... more ABSTRACT Hot-carrier stressing has been carried out on NMOS transistors under dynamic stressing conditions in which the drain voltage is kept constant and a square wave is applied to the gate such that electrons are injected into the oxide during the upper part of the cycle, while the lower part is varied so as to vary the oxide hole current. It is found that maximum degradation occurs when the hole current is maximum, indicating that the injection of both holes and electrons into the oxide is necessary for enhanced surface state generation, and supporting the model by which the trapping of holes and the subsequent neutralization by injected electrons leads to the formation of interface states.

Research paper thumbnail of Relaxation effects in NMOS transistors after hot-carrier stressing

IEEE Electron Device Letters, 2000

ABSTRACT Aging studies on NMOS transistors with dry oxides at room temperature have revealed that... more ABSTRACT Aging studies on NMOS transistors with dry oxides at room temperature have revealed that the creation of interface traps and the trapping of positive charge in the oxide associated with hot-electron effects are not permanent, but can be reversed to some extent if the transistor drain is grounded and left for some time. The relaxation is a substantial fraction of the original degradation at low degradation values and suggests that there is an annealing of some of the traps created by stressing. This annealing follows first-order kinetics for both created interface traps and trapped oxide charge, and is characterized by relaxation times τ r of 600-900 s.

Research paper thumbnail of Application of the floating-gate technique to the study of the n-MOSFET gate current evolution due to hot-carrier aging

IEEE Electron Device Letters, 2000

The evolution of the gate current-voltage (Ig- Vgs) characteristics of n-MOSFETs induced by DC st... more The evolution of the gate current-voltage (Ig- Vgs) characteristics of n-MOSFETs induced by DC stresses at different gate voltage over drain voltage (Vds ) ratios is studied by the floating-gate (FG) measurement technique. It is shown that the Ig-Vgs curves are always lowered after aging, and that the kinetics are dependent on the aging conditions. A time power law is

Research paper thumbnail of Algebraically structured colored Petri nets to model sequential processes

IEEE Transactions on Systems, Man and Cybernetics, Part B (Cybernetics), 1997

Sequential processes can hardly be modeled with Colored Petri Nets (CPN). Their standard function... more Sequential processes can hardly be modeled with Colored Petri Nets (CPN). Their standard functions (such as &quot;Succ&quot; and &quot;Prec&quot;) can only describe simple cases whereas modeling a complex sequence requires the definition of a function via a cumbersome and static table. In order to overcome these limitations, we first introduce a mixed structure based upon CPN and FIFO queues; then, we define an isomorphism between the set of colors and a finite field Z/pZ enabling symbolic calculation using polynomials associated with arcs instead of linear functions mapping sets into sets. Finally, several examples illustrate their modeling capabilities including failure recovery.

Research paper thumbnail of Relaxable damage in hot-carrier stressing of n-MOS transistors-oxide traps in the near interfacial region of the gate oxide

IEEE Transactions on Electron Devices, 1990

An examination of the relaxable hot-carrier stressing damage indicates that the relaxation is due... more An examination of the relaxable hot-carrier stressing damage indicates that the relaxation is due to charge trapped in the oxide located within tunneling distance of the Si-SiO2 interface, which charges during stressing and discharges by tunneling back out into the silicon. Both hole and electron traps are involved. The traps can be filled, either by injecting charge into the oxide

Research paper thumbnail of Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2<or=V/sub g/>or=V/sub d/) during hot-carrier stressing of n-MOS transistors

IEEE Transactions on Electron Devices, 1990

... 2 V&#x27;) During Hot-Carrier Stressing of n-MOS Transistors ... Dynamic stressing of MOS... more ... 2 V&#x27;) During Hot-Carrier Stressing of n-MOS Transistors ... Dynamic stressing of MOS transistors [33] has confirmed that interface state creation in MOS devices re-quires the injection of both electrons and holes together in the oxide. ...

Research paper thumbnail of Dynamic channel hot-carrier degradation of NMOS transistors by enhanced electron-hole injection into the oxide

IEEE Electron Device Letters, 2000

ABSTRACT Hot-carrier stressing has been carried out on NMOS transistors under dynamic stressing c... more ABSTRACT Hot-carrier stressing has been carried out on NMOS transistors under dynamic stressing conditions in which the drain voltage is kept constant and a square wave is applied to the gate such that electrons are injected into the oxide during the upper part of the cycle, while the lower part is varied so as to vary the oxide hole current. It is found that maximum degradation occurs when the hole current is maximum, indicating that the injection of both holes and electrons into the oxide is necessary for enhanced surface state generation, and supporting the model by which the trapping of holes and the subsequent neutralization by injected electrons leads to the formation of interface states.

Research paper thumbnail of Hot-carrier stressing damage in wide and narrow LDD NMOS transistors

IEEE Electron Device Letters, 2000

ABSTRACT Hot-carrier stressing has been carried out on LDD (lightly doped drain) NMOS transistors... more ABSTRACT Hot-carrier stressing has been carried out on LDD (lightly doped drain) NMOS transistors with gate width as a variable. It is found that the damage is qualitatively different between the wide and narrow devices. To investigate the poststress damage, use is made of a hole injection phase to neutralize any trapped charge. It is shown that the narrow devices degrade predominately by charge trapping, whereas the wider devices show interface-state creation. It is further shown that the localization of the hot-carrier damage is different, being extended towards the source for electron trapping in the narrow devices, whereas the wide devices show interface states localized at the drain junction edge. It is suggested that the mechanical constraints arising from the proximity of the bird&#39;s-beak structure are responsible for the electron-trapping behavior.&lt; &gt;

Research paper thumbnail of Validation by Petri net of a new approach for the one machine problem with temporal functions of polynomial type

IFAC Proceedings Volumes, 2009

Research paper thumbnail of Simultaneous stabilization using evolutionary programming and uniform design technique

2001 IEEE International Conference on Systems, Man and Cybernetics. e-Systems and e-Man for Cybernetics in Cyberspace (Cat.No.01CH37236), 2001

ABSTRACT The problem of simultaneous stabilization by a linear dynamic controller for a finite co... more ABSTRACT The problem of simultaneous stabilization by a linear dynamic controller for a finite collection of plants is important in the area of robust control. It is still an open problem. Most of the current research results are about the existence conditions of the controller, but the computation for the design of the controller is very complicated, thus it is difficult to use for practical problems, especially in the case of multiple systems. A new evolutionary programming method based on a uniform design technique is proposed to solve this problem. Simulation results show that it is an acceptable method for this kind of hard problem

Research paper thumbnail of Complex sequencing by methods of interpolation in Z/pZ colored Petri nets

Proceedings 1995 INRIA/IEEE Symposium on Emerging Technologies and Factory Automation. ETFA'95, 1995

ABSTRACT The notion of scheduling is a subject that characterizes many contemporary processes. Ne... more ABSTRACT The notion of scheduling is a subject that characterizes many contemporary processes. Nevertheless, Petri nets do not present tool satisfying to realize a complex sequencing. The originality of this study is mainly the replacement of the structure of set, associated with colors, by a structure of field Z /p Z allowing to process the succession of colors with mathematics. We introduce an algebraic structure of colors isomorphic with a finite field Z /p Z and a succession law of polynomial type polynomials nets that can be identified to colored Petri net (CPN), except that the arc weights are not predefined, specific or static functions but polynomial functions. This new tool of Petri nets can now be used as basis for ulterior studies on scheduling. We note that this method offers the advantage to operate on complex models, allows dynamic model evolution of PN, and leads to prediction of interesting solutions in scheduling problems and real-time systems

Research paper thumbnail of Extension of chaos anticontrol applied to the improvement of switch-mode power supply electromagnetic compatibility

2004 IEEE International Symposium on Industrial Electronics, 2004

Research paper thumbnail of Research strategy as the main catalyst for organizational development

IEMC '03 Proceedings. Managing Technologically Driven Organizations: The Human Side of Innovation and Change, 2003

Page 1. Research Strategy as the Main Catalyst for Organizational Development Radu Constantin Vla... more Page 1. Research Strategy as the Main Catalyst for Organizational Development Radu Constantin Vlad Jean-Yves Morel Marc Bourcerie Technical University of Cluj-Napoca University of Angers University of Angers Radu.Constantin ...

Research paper thumbnail of Effective management of large networks through the petri nets-discrete event simulation dualism

2004 IEEE International Conference on Systems, Man and Cybernetics (IEEE Cat. No.04CH37583), 2004

Page 1. 2004 IEEE International Conference on Systems, Man and Cybernetics Effective Management o... more Page 1. 2004 IEEE International Conference on Systems, Man and Cybernetics Effective Management of Large Networks Through the Petri Nets-Discrete Event Simulation Dualism * Radu C. Wad Management and Systems ...

Research paper thumbnail of Electrical and Optical Spectroscopic Characterization of Oxide Traps Induced by Hot Hole Injection

ESSDERC ’89, 1989

ABSTRACT For a better understanding of defects induced by hot carrier stressing in NMOS transisto... more ABSTRACT For a better understanding of defects induced by hot carrier stressing in NMOS transistors, the effect of emission enhanced by electric field (Poole-Frenkel effect) and the photodepopulation spectroscopy are used to characterize the traps in the thin gate oxide.

Research paper thumbnail of Z/pZ Petri nets model with application to an electroplating line

2001 IEEE International Conference on Systems, Man and Cybernetics. e-Systems and e-Man for Cybernetics in Cyberspace (Cat.No.01CH37236), 2001

The notion of scheduling is a subject that characterizes many contemporary processes. However, Pe... more The notion of scheduling is a subject that characterizes many contemporary processes. However, Petri nets do not represent a tool to realize a complex sequencing. The originality of this study is mainly the replacement of the structure, associated with colors, by a structure of field Z/pZ that allows the processing of colors succession with mathematics. We propose in this paper

Research paper thumbnail of The Voltage Dependence of Degradation in nMOS Transistors

Science & Sports - SCI SPORT, 1987

Hot carrier stressing has been carried out on silicon n-MOS devices as a function of gate voltage... more Hot carrier stressing has been carried out on silicon n-MOS devices as a function of gate voltage, at fixed drain voltages. It is found that a maximum of degradation occurs not only at Vq=Vd/2, but also at Vq=Vd. It is further found that the time power law for threshold voltage shift changes according to the voltage ratio. It is suggested that while the first peak is due to interface state degradation, the second is due to another process, possibly electron trapping in the oxide.

Research paper thumbnail of Improvement of Power Supply Electromagnetic Compatibility by Extension of Chaos Anticontrol

Journal of Circuits, Systems and Computers, 2005

ABSTRACT Switch-mode power supplies usually emit electromagnetic interferences at the switching f... more ABSTRACT Switch-mode power supplies usually emit electromagnetic interferences at the switching frequency and its harmonics. Inducing chaos in these systems has recently been suggested as a means of reducing these spectral emissions, yet at the expense of aggravating the overall magnitude of the ripple in the output voltage. We propose here a new nonlinear feedback control method, which induces chaos, and which is able at the same time to achieve low spectral emission and to maintain a small ripple in the output. The feasibility and usefulness of this new and simple method is shown here with a numerical example, which includes a comparison with the previous control method.

Research paper thumbnail of Relaxable damage in hot-carrier stressing of n-MOS transistors-oxide traps in the near interfacial region of the gate oxide

IEEE Transactions on Electron Devices, 1990

An examination of the relaxable hot-carrier stressing damage indicates that the relaxation is due... more An examination of the relaxable hot-carrier stressing damage indicates that the relaxation is due to charge trapped in the oxide located within tunneling distance of the Si-SiO2 interface, which charges during stressing and discharges by tunneling back out into the silicon. Both hole and electron traps are involved. The traps can be filled, either by injecting charge into the oxide

Research paper thumbnail of Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2<or=V/sub g/>or=V/sub d/) during hot-carrier stressing of n-MOS transistors

IEEE Transactions on Electron Devices, 1990

... 2 V&#x27;) During Hot-Carrier Stressing of n-MOS Transistors ... Dynamic stressing of MOS... more ... 2 V&#x27;) During Hot-Carrier Stressing of n-MOS Transistors ... Dynamic stressing of MOS transistors [33] has confirmed that interface state creation in MOS devices re-quires the injection of both electrons and holes together in the oxide. ...

Research paper thumbnail of Dynamic channel hot-carrier degradation of NMOS transistors by enhanced electron-hole injection into the oxide

IEEE Electron Device Letters, 2000

ABSTRACT Hot-carrier stressing has been carried out on NMOS transistors under dynamic stressing c... more ABSTRACT Hot-carrier stressing has been carried out on NMOS transistors under dynamic stressing conditions in which the drain voltage is kept constant and a square wave is applied to the gate such that electrons are injected into the oxide during the upper part of the cycle, while the lower part is varied so as to vary the oxide hole current. It is found that maximum degradation occurs when the hole current is maximum, indicating that the injection of both holes and electrons into the oxide is necessary for enhanced surface state generation, and supporting the model by which the trapping of holes and the subsequent neutralization by injected electrons leads to the formation of interface states.

Research paper thumbnail of Relaxation effects in NMOS transistors after hot-carrier stressing

IEEE Electron Device Letters, 2000

ABSTRACT Aging studies on NMOS transistors with dry oxides at room temperature have revealed that... more ABSTRACT Aging studies on NMOS transistors with dry oxides at room temperature have revealed that the creation of interface traps and the trapping of positive charge in the oxide associated with hot-electron effects are not permanent, but can be reversed to some extent if the transistor drain is grounded and left for some time. The relaxation is a substantial fraction of the original degradation at low degradation values and suggests that there is an annealing of some of the traps created by stressing. This annealing follows first-order kinetics for both created interface traps and trapped oxide charge, and is characterized by relaxation times τ r of 600-900 s.

Research paper thumbnail of Application of the floating-gate technique to the study of the n-MOSFET gate current evolution due to hot-carrier aging

IEEE Electron Device Letters, 2000

The evolution of the gate current-voltage (Ig- Vgs) characteristics of n-MOSFETs induced by DC st... more The evolution of the gate current-voltage (Ig- Vgs) characteristics of n-MOSFETs induced by DC stresses at different gate voltage over drain voltage (Vds ) ratios is studied by the floating-gate (FG) measurement technique. It is shown that the Ig-Vgs curves are always lowered after aging, and that the kinetics are dependent on the aging conditions. A time power law is