M. Houssa - Academia.edu (original) (raw)

Papers by M. Houssa

Research paper thumbnail of Buckled two-dimensional Xene sheets

Silicene, germanene and stanene are part of a monoelemental class of two-dimensional (2D) crystal... more Silicene, germanene and stanene are part of a monoelemental class of two-dimensional (2D) crystals termed 2D-Xenes (X = Si, Ge, Sn and so on) which, together with their ligand-functionalized derivatives referred to as Xanes, are comprised of group IVA atoms arranged in a honeycomb lattice — similar to graphene but with varying degrees of buckling. Their electronic structure ranges from trivial insulators, to semiconductors with tunable gaps, to semi-metallic, depending on the substrate, chemical functionalization and strain. More than a dozen different topological insulator states are predicted to emerge, including the quantum spin Hall state at room temperature, which, if realized, would enable new classes of nanoelectronic and spintronic devices, such as the topological field-effect transistor. The electronic structure can be tuned, for example, by changing the group IVA element, the degree of spin–orbit coupling, the functionalization chemistry or the substrate, making the 2D-Xene systems promising multifunctional 2D materials for nanotechnology. This Perspective highlights the current state of the art and future opportunities in the manipulation and stability of these materials, their functions and applications, and novel device concepts.

Research paper thumbnail of Model for NBTI in p-MOSFETs with ultra thin nitrided gated oxides

IEEE International Integrated Reliability Workshop Final Report, 2002., 2002

Negative bias temperature instability (NBTI) in p-MOSFETs is known as a major reliability issue f... more Negative bias temperature instability (NBTI) in p-MOSFETs is known as a major reliability issue for microelectronic devices. It has been suggested that NBTI is related to the generation of defects at the Si/SiO2 interface during the electrical stress. In this work, the degradation of the threshold voltage, mobility and the drain current of p-MOSFET's with ultrathin nitrided gate oxides during NBTI stress is modelled providing a physical basis as to why nitridation of oxides increases NBTI. This model includes a gaussian spread of activation energies of the Si3≡Si· centers (so called Pb0 centres), as well as the field dependence of the mean activation energy.

Research paper thumbnail of Adsorption of molecular oxygen on the reconstructed β2(2×4)-GaAs(001) surface: A first-principles study

Surface Science, 2009

ABSTRACT In this work, first-principles modeling techniques are used to investigate the mechanism... more ABSTRACT In this work, first-principles modeling techniques are used to investigate the mechanism(s) of adsorption of molecular oxygen on the GaAs(0 0 1)-(2 × 4) surface. The reaction of adsorption was modeled using ab-initio molecular dynamics at constant temperature for two thermal regimes, i.e. 300 K and 680 K, respectively. The resulting adsorbate configurations were relaxed using density functional theory and the adsorption energies were subsequently computed. Our results suggest a dominant mechanism of adsorption described by molecular dissociation, followed by oxygen insertion in the Ga–As bonds, bridging Ga–O–As chemical bonds. The electronic properties of the clean reconstructed GaAs(0 0 1) surface and the ones obtained after O2 adsorption were computed. It is found that for the most stable adsorbate configuration, where oxygen is incorporated in a Ga–O–As unit, the associated density of electronic states is free of defect levels within the GaAs band gap region.

Research paper thumbnail of Effect of extreme surface roughness on the electrical characteristics of ultra-thin gate oxides

Solid-State Electronics, 1999

The eect of extreme surface roughness on the electrical characteristics and gate oxide integrity ... more The eect of extreme surface roughness on the electrical characteristics and gate oxide integrity of MOS (metal± oxide±semiconductor) capacitors with ultra-thin SiO 2 layers is reported. The Si surface roughness is increased by NH 4 OH dips prior to gate oxidation. The Si and SiO 2 surfaces are then characterized by lightscattering Haze and AFM measurements. Electrical measurements are undertaken on MOS capacitors with a 6.4 and 4.2 nm gate oxide. Results are compared for wafers with RMS roughness of respectively 0.09 and 9 nm. It is shown that the tunneling current is increased in case of extreme Si surface roughness and does not follow the simple Fowler±Nordheim expression. Quantum oscillations in 4.2 nm oxides are also shown to be much damped by Si/SiO 2 interface roughness. The eect of surface roughness on gate oxide reliability is investigated through charge-to-breakdown Q BD measurements performed at constant current and constant voltage stress. It is shown that intrinsic Q BD values determined by constant current stressing are higher for oxides on rough surfaces in case of substrate injection while the opposite trend is observed in case of gate injection. All results can be consistently explained by considering the eect of a distribution of oxide thicknesses on the gate oxide properties. # 1998 Elsevier Science Ltd. All rights reserved.

Research paper thumbnail of Soft breakdown in very thin Ta2O5 gate dielectric layers

Solid-State Electronics, 2000

The time-dependent dielectric breakdown of metal-oxide-semiconductor capacitors with 6 nm and 8 n... more The time-dependent dielectric breakdown of metal-oxide-semiconductor capacitors with 6 nm and 8 nm Ta 2 O 5 gate dielectric layers is investigated. During constant voltage stress of the capacitors, a small increase in the timedependent gate current is observed, followed by the occurrence of erratic¯uctuations. After the occurrence of such a small jump, the current±voltage characteristics reveal increased gate current in the low gate voltage region, as compared to the current±voltage characteristics of fresh (unstressed) devices. In addition the gate current is shown to behave like a power law of the applied gate voltage. All above features are characteristics of the so-called soft breakdown event which has been previously reported for ultra-thin SiO 2 layers. #

Research paper thumbnail of Electron transport through high-κ dielectric barriers: A non-equilibrium Green’s function (NEGF) study

Journal of Non-Crystalline Solids, 2009

We present a simulation study of the coherent transport of electrons through high permittivity (h... more We present a simulation study of the coherent transport of electrons through high permittivity (high-κ) dielectric barriers using the non-equilibrium Green’s function (NEGF) formalism. Calculation and useful formula are established for a one-dimensional grid using a finite-difference scheme and an effective-mass depending on the position along the grid. A numerical simulation code is used to investigate the tunneling properties and the transmission coefficient of different metal–insulator–metal structures with stacked dielectrics and to compare single- or two-layer high-κ dielectric stacks in terms of tunneling transmission coefficient and local density-of-states. We particularly highlight the influence of wave-function reflections against barrier discontinuity on the transmission coefficient, especially in two-layer high-κ dielectric stacks.

Research paper thumbnail of A simulation analysis of FIBL in decananometer Double-Gate MOSFETs with high-κ gate dielectrics

Journal of Non-Crystalline Solids, 2005

ABSTRACT In this work, the degradation of electrical performances of Double-Gate MOSFET due to th... more ABSTRACT In this work, the degradation of electrical performances of Double-Gate MOSFET due to the fringing induced barrier lowering (FIBL) effect induced by high-κ gate dielectrics is investigated using a two-dimensional quantum-mechanical simulation code. Our numerical results show that all electrical parameters, such as the threshold voltage (VT), device immunity to short-channel effects, off-state current (Ioff), and subthreshold slope (S) are degraded when κ increases (3.9 < κ < 100). This degradation is both function of the channel length and the gate dielectric stack composition (number of layers, κ value). In particular, it is shown that the introduction of a thin (<1 nm thick) interfacial oxide layer can reduce or even completely suppress the FIBL for a given equivalent oxide thickness of the gate dielectric stack.

Research paper thumbnail of Model for the charge trapping in high permittivity gate dielectric stacks

Journal of Applied Physics, 2001

The generation of traps in and gate dielectric stacks during gate voltage stress of metal-oxide-s... more The generation of traps in and gate dielectric stacks during gate voltage stress of metal-oxide-semiconductor capacitors is investigated. The voltage and temperature dependence of the trap generation rate is extracted from the analysis of the gate current increase ...

Research paper thumbnail of Physics and Technology of High-k Materials 8: ECS Transactions: Volume 33

... AN Nazarov, PK Hurley, K. Cherkaoui, S. Monaghan, H. Gottlob, M. Schmidt, J. Schubert, J. Lop... more ... AN Nazarov, PK Hurley, K. Cherkaoui, S. Monaghan, H. Gottlob, M. Schmidt, J. Schubert, J. Lopes, and O ... System PK Hurley, R. Long, T. O'Regan, E. O'Connor, S. Monaghan, V. Djara, M. Negara, A ... Characteristics 473 C. Chang, T. Shie, Y. Lin, K. Kakushima, H. Iwai, P. Lu, T. Lin ...

Research paper thumbnail of Can silicon behave like graphene? A first-principles study

Applied Physics Letters, 2010

The electronic properties of two-dimensional hexagonal silicon ͑silicene͒ are investigated using ... more The electronic properties of two-dimensional hexagonal silicon ͑silicene͒ are investigated using first-principles simulations. Though silicene is predicted to be a gapless semiconductor, due to the sp 2 -hybridization of its atomic orbitals, the weak overlapping between 3p z orbitals of neighbor Si atoms leads to a very reactive surface, resulting in a more energetically stable semiconducting surface upon the adsorption of foreign chemical species. It is predicted that silicene inserted into a graphitelike lattice, like ultrathin AlN stacks, preserves its sp 2 -hydridization, and hence its graphenelike electronic properties.

Research paper thumbnail of Charge trapping in very thin high-permittivity gate dielectric layers

Applied Physics Letters, 2000

The trapping of charge carriers in very thin and gate dielectric stacks during constant gate volt... more The trapping of charge carriers in very thin and gate dielectric stacks during constant gate voltage stress of metal–oxide–semiconductor capacitors has been investigated. The increase of the gate current density observed during the gate voltage stress has been ...

Research paper thumbnail of Buckled two-dimensional Xene sheets

Silicene, germanene and stanene are part of a monoelemental class of two-dimensional (2D) crystal... more Silicene, germanene and stanene are part of a monoelemental class of two-dimensional (2D) crystals termed 2D-Xenes (X = Si, Ge, Sn and so on) which, together with their ligand-functionalized derivatives referred to as Xanes, are comprised of group IVA atoms arranged in a honeycomb lattice — similar to graphene but with varying degrees of buckling. Their electronic structure ranges from trivial insulators, to semiconductors with tunable gaps, to semi-metallic, depending on the substrate, chemical functionalization and strain. More than a dozen different topological insulator states are predicted to emerge, including the quantum spin Hall state at room temperature, which, if realized, would enable new classes of nanoelectronic and spintronic devices, such as the topological field-effect transistor. The electronic structure can be tuned, for example, by changing the group IVA element, the degree of spin–orbit coupling, the functionalization chemistry or the substrate, making the 2D-Xene systems promising multifunctional 2D materials for nanotechnology. This Perspective highlights the current state of the art and future opportunities in the manipulation and stability of these materials, their functions and applications, and novel device concepts.

Research paper thumbnail of Model for NBTI in p-MOSFETs with ultra thin nitrided gated oxides

IEEE International Integrated Reliability Workshop Final Report, 2002., 2002

Negative bias temperature instability (NBTI) in p-MOSFETs is known as a major reliability issue f... more Negative bias temperature instability (NBTI) in p-MOSFETs is known as a major reliability issue for microelectronic devices. It has been suggested that NBTI is related to the generation of defects at the Si/SiO2 interface during the electrical stress. In this work, the degradation of the threshold voltage, mobility and the drain current of p-MOSFET's with ultrathin nitrided gate oxides during NBTI stress is modelled providing a physical basis as to why nitridation of oxides increases NBTI. This model includes a gaussian spread of activation energies of the Si3≡Si· centers (so called Pb0 centres), as well as the field dependence of the mean activation energy.

Research paper thumbnail of Adsorption of molecular oxygen on the reconstructed β2(2×4)-GaAs(001) surface: A first-principles study

Surface Science, 2009

ABSTRACT In this work, first-principles modeling techniques are used to investigate the mechanism... more ABSTRACT In this work, first-principles modeling techniques are used to investigate the mechanism(s) of adsorption of molecular oxygen on the GaAs(0 0 1)-(2 × 4) surface. The reaction of adsorption was modeled using ab-initio molecular dynamics at constant temperature for two thermal regimes, i.e. 300 K and 680 K, respectively. The resulting adsorbate configurations were relaxed using density functional theory and the adsorption energies were subsequently computed. Our results suggest a dominant mechanism of adsorption described by molecular dissociation, followed by oxygen insertion in the Ga–As bonds, bridging Ga–O–As chemical bonds. The electronic properties of the clean reconstructed GaAs(0 0 1) surface and the ones obtained after O2 adsorption were computed. It is found that for the most stable adsorbate configuration, where oxygen is incorporated in a Ga–O–As unit, the associated density of electronic states is free of defect levels within the GaAs band gap region.

Research paper thumbnail of Effect of extreme surface roughness on the electrical characteristics of ultra-thin gate oxides

Solid-State Electronics, 1999

The eect of extreme surface roughness on the electrical characteristics and gate oxide integrity ... more The eect of extreme surface roughness on the electrical characteristics and gate oxide integrity of MOS (metal± oxide±semiconductor) capacitors with ultra-thin SiO 2 layers is reported. The Si surface roughness is increased by NH 4 OH dips prior to gate oxidation. The Si and SiO 2 surfaces are then characterized by lightscattering Haze and AFM measurements. Electrical measurements are undertaken on MOS capacitors with a 6.4 and 4.2 nm gate oxide. Results are compared for wafers with RMS roughness of respectively 0.09 and 9 nm. It is shown that the tunneling current is increased in case of extreme Si surface roughness and does not follow the simple Fowler±Nordheim expression. Quantum oscillations in 4.2 nm oxides are also shown to be much damped by Si/SiO 2 interface roughness. The eect of surface roughness on gate oxide reliability is investigated through charge-to-breakdown Q BD measurements performed at constant current and constant voltage stress. It is shown that intrinsic Q BD values determined by constant current stressing are higher for oxides on rough surfaces in case of substrate injection while the opposite trend is observed in case of gate injection. All results can be consistently explained by considering the eect of a distribution of oxide thicknesses on the gate oxide properties. # 1998 Elsevier Science Ltd. All rights reserved.

Research paper thumbnail of Soft breakdown in very thin Ta2O5 gate dielectric layers

Solid-State Electronics, 2000

The time-dependent dielectric breakdown of metal-oxide-semiconductor capacitors with 6 nm and 8 n... more The time-dependent dielectric breakdown of metal-oxide-semiconductor capacitors with 6 nm and 8 nm Ta 2 O 5 gate dielectric layers is investigated. During constant voltage stress of the capacitors, a small increase in the timedependent gate current is observed, followed by the occurrence of erratic¯uctuations. After the occurrence of such a small jump, the current±voltage characteristics reveal increased gate current in the low gate voltage region, as compared to the current±voltage characteristics of fresh (unstressed) devices. In addition the gate current is shown to behave like a power law of the applied gate voltage. All above features are characteristics of the so-called soft breakdown event which has been previously reported for ultra-thin SiO 2 layers. #

Research paper thumbnail of Electron transport through high-κ dielectric barriers: A non-equilibrium Green’s function (NEGF) study

Journal of Non-Crystalline Solids, 2009

We present a simulation study of the coherent transport of electrons through high permittivity (h... more We present a simulation study of the coherent transport of electrons through high permittivity (high-κ) dielectric barriers using the non-equilibrium Green’s function (NEGF) formalism. Calculation and useful formula are established for a one-dimensional grid using a finite-difference scheme and an effective-mass depending on the position along the grid. A numerical simulation code is used to investigate the tunneling properties and the transmission coefficient of different metal–insulator–metal structures with stacked dielectrics and to compare single- or two-layer high-κ dielectric stacks in terms of tunneling transmission coefficient and local density-of-states. We particularly highlight the influence of wave-function reflections against barrier discontinuity on the transmission coefficient, especially in two-layer high-κ dielectric stacks.

Research paper thumbnail of A simulation analysis of FIBL in decananometer Double-Gate MOSFETs with high-κ gate dielectrics

Journal of Non-Crystalline Solids, 2005

ABSTRACT In this work, the degradation of electrical performances of Double-Gate MOSFET due to th... more ABSTRACT In this work, the degradation of electrical performances of Double-Gate MOSFET due to the fringing induced barrier lowering (FIBL) effect induced by high-κ gate dielectrics is investigated using a two-dimensional quantum-mechanical simulation code. Our numerical results show that all electrical parameters, such as the threshold voltage (VT), device immunity to short-channel effects, off-state current (Ioff), and subthreshold slope (S) are degraded when κ increases (3.9 < κ < 100). This degradation is both function of the channel length and the gate dielectric stack composition (number of layers, κ value). In particular, it is shown that the introduction of a thin (<1 nm thick) interfacial oxide layer can reduce or even completely suppress the FIBL for a given equivalent oxide thickness of the gate dielectric stack.

Research paper thumbnail of Model for the charge trapping in high permittivity gate dielectric stacks

Journal of Applied Physics, 2001

The generation of traps in and gate dielectric stacks during gate voltage stress of metal-oxide-s... more The generation of traps in and gate dielectric stacks during gate voltage stress of metal-oxide-semiconductor capacitors is investigated. The voltage and temperature dependence of the trap generation rate is extracted from the analysis of the gate current increase ...

Research paper thumbnail of Physics and Technology of High-k Materials 8: ECS Transactions: Volume 33

... AN Nazarov, PK Hurley, K. Cherkaoui, S. Monaghan, H. Gottlob, M. Schmidt, J. Schubert, J. Lop... more ... AN Nazarov, PK Hurley, K. Cherkaoui, S. Monaghan, H. Gottlob, M. Schmidt, J. Schubert, J. Lopes, and O ... System PK Hurley, R. Long, T. O'Regan, E. O'Connor, S. Monaghan, V. Djara, M. Negara, A ... Characteristics 473 C. Chang, T. Shie, Y. Lin, K. Kakushima, H. Iwai, P. Lu, T. Lin ...

Research paper thumbnail of Can silicon behave like graphene? A first-principles study

Applied Physics Letters, 2010

The electronic properties of two-dimensional hexagonal silicon ͑silicene͒ are investigated using ... more The electronic properties of two-dimensional hexagonal silicon ͑silicene͒ are investigated using first-principles simulations. Though silicene is predicted to be a gapless semiconductor, due to the sp 2 -hybridization of its atomic orbitals, the weak overlapping between 3p z orbitals of neighbor Si atoms leads to a very reactive surface, resulting in a more energetically stable semiconducting surface upon the adsorption of foreign chemical species. It is predicted that silicene inserted into a graphitelike lattice, like ultrathin AlN stacks, preserves its sp 2 -hydridization, and hence its graphenelike electronic properties.

Research paper thumbnail of Charge trapping in very thin high-permittivity gate dielectric layers

Applied Physics Letters, 2000

The trapping of charge carriers in very thin and gate dielectric stacks during constant gate volt... more The trapping of charge carriers in very thin and gate dielectric stacks during constant gate voltage stress of metal–oxide–semiconductor capacitors has been investigated. The increase of the gate current density observed during the gate voltage stress has been ...