M. Jimarez - Academia.edu (original) (raw)

Papers by M. Jimarez

2012 IEEE 62nd Electronic Components and Technology Conference, 2012

ABSTRACT Recently, technologies related to Fine Pitch Flip Chip or FPFC have been great achieveme... more ABSTRACT Recently, technologies related to Fine Pitch Flip Chip or FPFC have been great achievements for various next generation devices, allowing a significant increase in the number of signal I/O and achieving low form factor packages. Consequently, fine pitch Cu pillar flip chip Chip Scale Package (CSP) with small sized die, with package dimension of less than 16×16mm, is already under high volume production using the Thermal-Compression Bonding with Non-conductive Paste (TCNCP) technology [1-2]. In the case of Flip Chip Ball Grid Array (FCBGA), there is a growing need for FPFC technology with Cu pillar in supporting next generation silicon node. However, there will be a high possibility of yield drop issue in conventional mass-reflow process and potential reliability due to the highly concerned tensile stress between low k die and substrate by CTE mismatch especially at the edge of the die. This can be a critical quality issue for fine pitch devices compared to normal pitch (i.e., 150um) flip chip BGA. Therefore, TCNCP bonding as an alternative should be studied on fine pitch Cu pillar flip chip BGA. This paper will discuss fine pitch flip chip assembly technology for large sized flip chip BGA. Two kinds of assembly method, mass reflow bonding versus thermal compression bonding, for the flip chip bonding will be compared for the large FPFCBGA package. Meanwhile, the advantage of TC bonding with pre-applied underfill process will be described. For robust interconnection between die and substrate for large FPFCBGA, the result of the bonding test will be described with several surface finishes such as ENEPIG, Direct Immersion Gold (DIG), Immersion Tin (IT), and Solder Coating on substrate. Interestingly, one of selected surface finishes has shown excellent reliability test results. Finally, this paper will discuss an effective approach for fine pitch devices from an assembly perspective.

2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2008

In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die, cop... more In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die, copper heat spreader and packaging substrate induces concentrated stress field around the edges and corners of silicon die during assembly, testing and services. The concentrated stresses result in delamination on various interfaces involving a range of length scales from hundreds of nanometers to millimeters. Among these failures underfill delamination is a dominant failure mode. In this paper, a full parametric 3D model of flip chip package with heat spreader is developed with the capability of explicit modeling of 3D cracks. The crack driving force is computed as the functions of underfill properties including coefficient of thermal expansion and Young's modulus, as well as underfill fillet dimensions. The impact of different shapes of crack front is also investigated. The results show that underfill properties need to be optimized to minimize the occurrence of underfill delamination at the die corner. The results also show that there exists an optimal range of underfill fillet height to balance the manufacturability and reliability.

IEEE Transactions on Advanced Packaging, 1999

Flip-chip (FC) packaging is gaining acceptance in the electronics packaging arena. More sources o... more Flip-chip (FC) packaging is gaining acceptance in the electronics packaging arena. More sources of bumped die and high density printed wiring boards (PWBs) laminates become available every day. Also, known good die (KGD) issues are being resolved by several companies, and design tools to perform FC packaging designs are becoming more available. This is the infrastructure FC packaging requires to

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206), 1998

ABSTRACT Technical evaluation and reliability assessment have been performed for a near chip scal... more ABSTRACT Technical evaluation and reliability assessment have been performed for a near chip scale size package that utilizes microvias and the Flip Chip-Plastic Ball Grid Array technology. The microvias were photolithographically patterned in a build-up, Surface Laminar Circuit TM (SLC) interposer layers. The package accommodated a 12 mm×14 mm die with 700 controlled collapse chip connections (C4). The carrier dimensions were 21 mm×21 mm, 1.27 mm pitch with 255 EGA interconnections. The dimensions of the package, for which the target application was microprocessors, conformed to the JEDEC standards. It has been determined that this novel packaging construction is manufacturable and can satisfy the standard reliability requirements

2012 IEEE 62nd Electronic Components and Technology Conference, 2012

ABSTRACT Recently, technologies related to Fine Pitch Flip Chip or FPFC have been great achieveme... more ABSTRACT Recently, technologies related to Fine Pitch Flip Chip or FPFC have been great achievements for various next generation devices, allowing a significant increase in the number of signal I/O and achieving low form factor packages. Consequently, fine pitch Cu pillar flip chip Chip Scale Package (CSP) with small sized die, with package dimension of less than 16×16mm, is already under high volume production using the Thermal-Compression Bonding with Non-conductive Paste (TCNCP) technology [1-2]. In the case of Flip Chip Ball Grid Array (FCBGA), there is a growing need for FPFC technology with Cu pillar in supporting next generation silicon node. However, there will be a high possibility of yield drop issue in conventional mass-reflow process and potential reliability due to the highly concerned tensile stress between low k die and substrate by CTE mismatch especially at the edge of the die. This can be a critical quality issue for fine pitch devices compared to normal pitch (i.e., 150um) flip chip BGA. Therefore, TCNCP bonding as an alternative should be studied on fine pitch Cu pillar flip chip BGA. This paper will discuss fine pitch flip chip assembly technology for large sized flip chip BGA. Two kinds of assembly method, mass reflow bonding versus thermal compression bonding, for the flip chip bonding will be compared for the large FPFCBGA package. Meanwhile, the advantage of TC bonding with pre-applied underfill process will be described. For robust interconnection between die and substrate for large FPFCBGA, the result of the bonding test will be described with several surface finishes such as ENEPIG, Direct Immersion Gold (DIG), Immersion Tin (IT), and Solder Coating on substrate. Interestingly, one of selected surface finishes has shown excellent reliability test results. Finally, this paper will discuss an effective approach for fine pitch devices from an assembly perspective.

2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2008

In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die, cop... more In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die, copper heat spreader and packaging substrate induces concentrated stress field around the edges and corners of silicon die during assembly, testing and services. The concentrated stresses result in delamination on various interfaces involving a range of length scales from hundreds of nanometers to millimeters. Among these failures underfill delamination is a dominant failure mode. In this paper, a full parametric 3D model of flip chip package with heat spreader is developed with the capability of explicit modeling of 3D cracks. The crack driving force is computed as the functions of underfill properties including coefficient of thermal expansion and Young's modulus, as well as underfill fillet dimensions. The impact of different shapes of crack front is also investigated. The results show that underfill properties need to be optimized to minimize the occurrence of underfill delamination at the die corner. The results also show that there exists an optimal range of underfill fillet height to balance the manufacturability and reliability.

IEEE Transactions on Advanced Packaging, 1999

Flip-chip (FC) packaging is gaining acceptance in the electronics packaging arena. More sources o... more Flip-chip (FC) packaging is gaining acceptance in the electronics packaging arena. More sources of bumped die and high density printed wiring boards (PWBs) laminates become available every day. Also, known good die (KGD) issues are being resolved by several companies, and design tools to perform FC packaging designs are becoming more available. This is the infrastructure FC packaging requires to

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206), 1998

ABSTRACT Technical evaluation and reliability assessment have been performed for a near chip scal... more ABSTRACT Technical evaluation and reliability assessment have been performed for a near chip scale size package that utilizes microvias and the Flip Chip-Plastic Ball Grid Array technology. The microvias were photolithographically patterned in a build-up, Surface Laminar Circuit TM (SLC) interposer layers. The package accommodated a 12 mm×14 mm die with 700 controlled collapse chip connections (C4). The carrier dimensions were 21 mm×21 mm, 1.27 mm pitch with 255 EGA interconnections. The dimensions of the package, for which the target application was microprocessors, conformed to the JEDEC standards. It has been determined that this novel packaging construction is manufacturable and can satisfy the standard reliability requirements