M. Van Hove - Academia.edu (original) (raw)

Papers by M. Van Hove

Research paper thumbnail of Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuits

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 2005

... Marc Demuynck, Steven Delvaux, Christie Lauwers, Anne Baerts, Christina Beckx, Stephan Boulla... more ... Marc Demuynck, Steven Delvaux, Christie Lauwers, Anne Baerts, Christina Beckx, Stephan Boullart, Werner Brus, Stephan Degroote, Bart ... David Leray, Philippe Locorotondo, Sabrina Maenhoudt, Mireille Moelants, Myriam Pollentier, Ivan Ronse, Kurt Rooyackers, Rita Van Aelst ...

Research paper thumbnail of Low-k properties and integration processes enabling reliable interconnect scaling to the 32 nm technology node

Corresponding author: Atsushi Ikeda email: ikeda@imec.be Tel: +32-16-28-8696 - Fax: +32-16-28-121... more Corresponding author: Atsushi Ikeda email: ikeda@imec.be Tel: +32-16-28-8696 - Fax: +32-16-28-1214 Abstract Single damascene (SD) Cu/Aurora® ULK interconnects with a minimum spacing of 50nm are achieved by using a metal hard mask (MHM) integration scheme, ...

Research paper thumbnail of Physical behaviour of pseudomorphic HEMTs at low temperatures

Membrane Technology, 1993

The analysis of high frequency parameters of pseudomorphic HEMTs (PM-HEMT) at cryogenic temperatu... more The analysis of high frequency parameters of pseudomorphic HEMTs (PM-HEMT) at cryogenic temperatures and different gate lengths 0.1¿m to 0.7¿m, compared to existing modeling data, points out the improvement of average carrier velocity transport at low temperatures, the larger relative importance of certain parasitic effects (lateral diffusion under the gate, fringe effects, electrostatic capacitances) when the temperature decreases while other parasitic elements decrease (access and gate resistances) and also the influence of DX type centers.

Research paper thumbnail of Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuits

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 2005

... Marc Demuynck, Steven Delvaux, Christie Lauwers, Anne Baerts, Christina Beckx, Stephan Boulla... more ... Marc Demuynck, Steven Delvaux, Christie Lauwers, Anne Baerts, Christina Beckx, Stephan Boullart, Werner Brus, Stephan Degroote, Bart ... David Leray, Philippe Locorotondo, Sabrina Maenhoudt, Mireille Moelants, Myriam Pollentier, Ivan Ronse, Kurt Rooyackers, Rita Van Aelst ...

Research paper thumbnail of Integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond using 193 nm optical lithography with dipole illumination

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695), 2003

This paper describes the integration of Single Damascene 85/85 nm L/S copper trenches in Black Di... more This paper describes the integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond (Applied Materials) dielectric (k=2.85). Optical lithography (193 nm) with off-axis illumination was used to print the trenches. Integration issues are discussed, and resistance and RC delay data are presented. The method is applied to study the resistivity for sub 100 nm copper lines.

Research paper thumbnail of AlGaN/GaN/AlGaN Double Heterostructures on Silicon Substrates for High Breakdown Voltage Field-Effect Transistors with low On-Resistance

Japanese Journal of Applied Physics, 2009

Research paper thumbnail of GaN-on-Si power field effect transistors

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, 2010

Research paper thumbnail of High breakdown voltage in AlGaN/GaN/AlGaN double heterostructures grown on 4 inch Si substrates

physica status solidi (c), 2009

Research paper thumbnail of Optoelectronic switch with low holding power

Electronics Letters, 1990

A double heterostructure NpnP optoelectronic switching device with low holding power has been fab... more A double heterostructure NpnP optoelectronic switching device with low holding power has been fabricated. In the static regime a holding power of 20 nW for a device area of 200 micron x 100 micron was obtained. This value represents a reduction of four orders of magnitude in holding power compared to previous reported PnpN or PnN structures with equivalent device

Research paper thumbnail of Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuits

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 2005

... Marc Demuynck, Steven Delvaux, Christie Lauwers, Anne Baerts, Christina Beckx, Stephan Boulla... more ... Marc Demuynck, Steven Delvaux, Christie Lauwers, Anne Baerts, Christina Beckx, Stephan Boullart, Werner Brus, Stephan Degroote, Bart ... David Leray, Philippe Locorotondo, Sabrina Maenhoudt, Mireille Moelants, Myriam Pollentier, Ivan Ronse, Kurt Rooyackers, Rita Van Aelst ...

Research paper thumbnail of Low-k properties and integration processes enabling reliable interconnect scaling to the 32 nm technology node

Corresponding author: Atsushi Ikeda email: ikeda@imec.be Tel: +32-16-28-8696 - Fax: +32-16-28-121... more Corresponding author: Atsushi Ikeda email: ikeda@imec.be Tel: +32-16-28-8696 - Fax: +32-16-28-1214 Abstract Single damascene (SD) Cu/Aurora® ULK interconnects with a minimum spacing of 50nm are achieved by using a metal hard mask (MHM) integration scheme, ...

Research paper thumbnail of Physical behaviour of pseudomorphic HEMTs at low temperatures

Membrane Technology, 1993

The analysis of high frequency parameters of pseudomorphic HEMTs (PM-HEMT) at cryogenic temperatu... more The analysis of high frequency parameters of pseudomorphic HEMTs (PM-HEMT) at cryogenic temperatures and different gate lengths 0.1¿m to 0.7¿m, compared to existing modeling data, points out the improvement of average carrier velocity transport at low temperatures, the larger relative importance of certain parasitic effects (lateral diffusion under the gate, fringe effects, electrostatic capacitances) when the temperature decreases while other parasitic elements decrease (access and gate resistances) and also the influence of DX type centers.

Research paper thumbnail of Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuits

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 2005

... Marc Demuynck, Steven Delvaux, Christie Lauwers, Anne Baerts, Christina Beckx, Stephan Boulla... more ... Marc Demuynck, Steven Delvaux, Christie Lauwers, Anne Baerts, Christina Beckx, Stephan Boullart, Werner Brus, Stephan Degroote, Bart ... David Leray, Philippe Locorotondo, Sabrina Maenhoudt, Mireille Moelants, Myriam Pollentier, Ivan Ronse, Kurt Rooyackers, Rita Van Aelst ...

Research paper thumbnail of Integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond using 193 nm optical lithography with dipole illumination

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695), 2003

This paper describes the integration of Single Damascene 85/85 nm L/S copper trenches in Black Di... more This paper describes the integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond (Applied Materials) dielectric (k=2.85). Optical lithography (193 nm) with off-axis illumination was used to print the trenches. Integration issues are discussed, and resistance and RC delay data are presented. The method is applied to study the resistivity for sub 100 nm copper lines.

Research paper thumbnail of AlGaN/GaN/AlGaN Double Heterostructures on Silicon Substrates for High Breakdown Voltage Field-Effect Transistors with low On-Resistance

Japanese Journal of Applied Physics, 2009

Research paper thumbnail of GaN-on-Si power field effect transistors

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, 2010

Research paper thumbnail of High breakdown voltage in AlGaN/GaN/AlGaN double heterostructures grown on 4 inch Si substrates

physica status solidi (c), 2009

Research paper thumbnail of Optoelectronic switch with low holding power

Electronics Letters, 1990

A double heterostructure NpnP optoelectronic switching device with low holding power has been fab... more A double heterostructure NpnP optoelectronic switching device with low holding power has been fabricated. In the static regime a holding power of 20 nW for a device area of 200 micron x 100 micron was obtained. This value represents a reduction of four orders of magnitude in holding power compared to previous reported PnpN or PnN structures with equivalent device