Heranmoy Maity - Academia.edu (original) (raw)

Papers by Heranmoy Maity

Research paper thumbnail of Quantum Cost Optimized Design of Reversible 2's Complement Code Converter

2018 IEEE Electron Devices Kolkata Conference (EDKCON), 2018

In this paper, we have proposed a quantum cost optimized reversible 2's complement code conve... more In this paper, we have proposed a quantum cost optimized reversible 2's complement code converter (2SCCC) circuit using existing reversible logic gate. First, we have design a reversible controlled inverter using Feynman gate and then we have design the proposed code converter (2SCCC) circuit using Feynman gate and Peres gate. Finally, we have proposed the design of quantum cost optimized reversible 2's complement code converter. The quantum cost (QC), garbage output (GO), delay and constant input (CI) of the proposed 2's complement code converter circuits are 11, 1, 7 and 1 which is better w. r. t. previously reported results. The improvement % of quantum cost, garbage outputs, delay and constant inputs are 26.66 - 60.71 %, 0 - 92.3 %, 25 - 57.14 % and 0 - 83.33 %.

Research paper thumbnail of The Quantum Cost, Garbage Outputs and Constant Input Optimized Implementation of 2:4 Decoder Using Peres Gate

2019 Devices for Integrated Circuit (DevIC), 2019

This paper presents the quantum cost (QC), garbage output (GO) and constant input (CI) optimized ... more This paper presents the quantum cost (QC), garbage output (GO) and constant input (CI) optimized 2:4 decoder using reversible logic gate. The proposed reversible circuit is design using existing reversible logic gate, such as reversible NOT gate, Feynman gate and Peres gate. The proposed decoder can be design using one Peres gate, one NOT gate and four Feynman gate. The QC, GO and CI of the proposed 2:4 decoder is 9, 0 and 2. Which is better w.r.t previously reported work. This is the first reversible 2:4 decoder circuit, which has ‘0’ garbage output. The improvement % of QC, GO and CI are 0 – 74.28 %, 100 % and 33.33 – 75 %.

Research paper thumbnail of Design of 4-Bit Reversible Johnson Counter with Optimized Quantum Cost, Delay, and Number of Gate

Advances in Computer, Communication and Control, 2019

In this paper, we have proposed the design quantum cost, delay, and number of reversible logic ga... more In this paper, we have proposed the design quantum cost, delay, and number of reversible logic gate optimized 4-bit Johnson counter using existing reversible logic gate. The proposed work is designed using HNF gate and Feynman gate. The proposed work is derived with quantum cost (QC), delay (D), constant inputs (CI), garbage output (GO), and number of gates (GC). The QC, D, and GC of the proposed Johnson counter are 21, 5, and 5, respectively. The percentage (%) of improvement is 12.5, 37.5, and 37.5% w.r.t. latest reported result.

Research paper thumbnail of Design of quantum cost efficient 4-bit reversible universal shift register

2017 Devices for Integrated Circuit (DevIC), 2017

This paper proposed the design of quantum cost efficient 4-bit reversible universal shift registe... more This paper proposed the design of quantum cost efficient 4-bit reversible universal shift register(RUSR) using existing reversible logic gates. The proposed design is very useful in quantum computing due to its low quantum cost, less no. of reversible logic gate and low garbage outputs. The quantum cost(QC), garbage output(GO), number of gates are respectively 68, 20 and 16 for proposed work.

Research paper thumbnail of Design of quantum cost efficient MOD-8 synchronous UP/DOWN counter using reversible logic gate

Research paper thumbnail of Design of Quantum Cost and Delay Optimized Code Converter Using New Reversible Quantum Circuit Block (QCB)

Micro and Nanosystems, 2021

Background: In this article, we have proposed a new reversible quantum circuit block along with t... more Background: In this article, we have proposed a new reversible quantum circuit block along with the quantum cost (QC), constant input (CI), garbage output (GO) and delay optimized code converterusing quantum circuit block. Method: Initially, new quantum circuit block has been designed and later reversible code converter circuits have been implemented using it. The proposed new quantum blockused to design 2’s complement code converter (2SCCC), cost efficient BCD to Excess-3 code converter (BECC) and can also be used to implement different logic functions. The QC of proposed quantum circuit block is 8. The QC and delay of the proposed 2SCCC is 8 and 1 respectively. Similarly, the QC and delay of the proposed BECC is 11 and 2 respectively. The proposed cost efficient BECC is designed using two NOT gate, one Feynman gate and one new quantum circuit block with QC is 11. Results: The improvement of QC for 2SCCC and BECC are 27.27 % and 21.43% respectively. The improvement of delay for 2SC...

Research paper thumbnail of The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block

Micro and Nanosystems, 2019

Aim and Objective: This paper presents the quantum cost, garbage output, constant input and numbe... more Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

Research paper thumbnail of Design of Reversible Shift Register Using Reduced Number of Logic Gates

Micro and Nanosystems, 2020

Background: Over the last few decades, reversible logic system/circuits have received considerabl... more Background: Over the last few decades, reversible logic system/circuits have received considerable attention in the diversified fields such as nanotechnology, quantum computing, cryptography, optical computing and low power design of VLSI circuits due to their low power dissipation characteristics. Methods: In this paper, we proposed the design of reversible shift register (SR) i.e. serial-in-serial out (SISO), serial-in-parallel out (SIPO), parallel-in-serial out (PISO) and parallel-in-parallel out (PIPO) SR using a reduced number of reversible logic gates and garbage output. Results: As compared to previously reported results, the improvement in our proposed model of SISO, SIPO, PISO and PIPO was found to be 50 – 66.66 %, 42.85 – 66.66 %, 12.5 – 53.33 % and 50 – 66.66 % respectively, in terms of the number of reversible logic gates.

Research paper thumbnail of Design of Reversible Combinational Circuits Using New Reversible Logic Gate

Journal of Engineering Science and Technology Review, 2018

In this paper the authors have proposed a new 3×3 reversible gate and also proposed the reversibl... more In this paper the authors have proposed a new 3×3 reversible gate and also proposed the reversible combinational logic circuits with better optimized quantum cost, garbage outputs and delay. The proposed new reversible logic gate is used to design of reversible 1-bit comparator circuit and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed new reversible logic gate is represented by quantum implementation. The quantum cost of proposed gate is 4. The quantum cost, garbage output and delay of proposed reversible 1-bit comparator circuit are 6 which is better w. r. t. previously reported results.

Research paper thumbnail of Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate

International Journal of Quantum Information, 2018

In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible log... more In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.

Research paper thumbnail of Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

International Journal of Quantum Information, 2018

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible univer... more In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

Research paper thumbnail of Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

Journal of Circuits, Systems and Computers, 2018

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), ... more In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Research paper thumbnail of A Novel Design of MOD-8 Synchronous UP/DOWN Counter Using Reversible Gate

International Journal of Scientific Research and Education, Sep 27, 2014

The Reversible logic synthesis techniques will definitely be a necessary part of the long-term fu... more The Reversible logic synthesis techniques will definitely be a necessary part of the long-term future of computing due to its low power dissipating characteristic. Today, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, and low power design of circuits. In this paper we proposed the design of MOD-8 synchronous up/down counter which uses existing reversible gates and derived quantum cost, constant inputs and number of gates to implement it.

Research paper thumbnail of Design and Development of 4-Bit Gray Code Counter Circuit Using Reversible Logic Gate

Micro and Nanosystems, 2021

Aim: This paper proposed the design and development of 4-Bit Gray Code Counter Circuit Using Reve... more Aim: This paper proposed the design and development of 4-Bit Gray Code Counter Circuit Using Reversible Logic Gate. Methods: The 4-Bit Gray Code Counter Circuit can be design using SAM gate, Feynman gate (FG), double Feynman gate (DFG) and NOT gate. The proposed circuit is the combined application of 4-bit binary asynchronous counter and 4-bit binary to gray code converter circuit. Results: The proposed gray code counter is designed using four no. of SAM gate, three no. of DFG, one FG and seven reversible NOT gate. The QC, GO and CI of proposed circuit are correspondingly 30, 4 and 7. Conclusion: The novel reversible gray code counter have been designed using existing reversible logic gate. The proposed gray code counter is designed using four no. of SAM gate, three no. of DFG, one FG and seven reversible NOT gate. The QC, GO and CI of proposed circuit are correspondingly 30, 4 and 7.

Research paper thumbnail of Quantum Cost Optimized Design of Reversible 2's Complement Code Converter

2018 IEEE Electron Devices Kolkata Conference (EDKCON), 2018

In this paper, we have proposed a quantum cost optimized reversible 2's complement code conve... more In this paper, we have proposed a quantum cost optimized reversible 2's complement code converter (2SCCC) circuit using existing reversible logic gate. First, we have design a reversible controlled inverter using Feynman gate and then we have design the proposed code converter (2SCCC) circuit using Feynman gate and Peres gate. Finally, we have proposed the design of quantum cost optimized reversible 2's complement code converter. The quantum cost (QC), garbage output (GO), delay and constant input (CI) of the proposed 2's complement code converter circuits are 11, 1, 7 and 1 which is better w. r. t. previously reported results. The improvement % of quantum cost, garbage outputs, delay and constant inputs are 26.66 - 60.71 %, 0 - 92.3 %, 25 - 57.14 % and 0 - 83.33 %.

Research paper thumbnail of The Quantum Cost, Garbage Outputs and Constant Input Optimized Implementation of 2:4 Decoder Using Peres Gate

2019 Devices for Integrated Circuit (DevIC), 2019

This paper presents the quantum cost (QC), garbage output (GO) and constant input (CI) optimized ... more This paper presents the quantum cost (QC), garbage output (GO) and constant input (CI) optimized 2:4 decoder using reversible logic gate. The proposed reversible circuit is design using existing reversible logic gate, such as reversible NOT gate, Feynman gate and Peres gate. The proposed decoder can be design using one Peres gate, one NOT gate and four Feynman gate. The QC, GO and CI of the proposed 2:4 decoder is 9, 0 and 2. Which is better w.r.t previously reported work. This is the first reversible 2:4 decoder circuit, which has ‘0’ garbage output. The improvement % of QC, GO and CI are 0 – 74.28 %, 100 % and 33.33 – 75 %.

Research paper thumbnail of Design of 4-Bit Reversible Johnson Counter with Optimized Quantum Cost, Delay, and Number of Gate

Advances in Computer, Communication and Control, 2019

In this paper, we have proposed the design quantum cost, delay, and number of reversible logic ga... more In this paper, we have proposed the design quantum cost, delay, and number of reversible logic gate optimized 4-bit Johnson counter using existing reversible logic gate. The proposed work is designed using HNF gate and Feynman gate. The proposed work is derived with quantum cost (QC), delay (D), constant inputs (CI), garbage output (GO), and number of gates (GC). The QC, D, and GC of the proposed Johnson counter are 21, 5, and 5, respectively. The percentage (%) of improvement is 12.5, 37.5, and 37.5% w.r.t. latest reported result.

Research paper thumbnail of Design of quantum cost efficient 4-bit reversible universal shift register

2017 Devices for Integrated Circuit (DevIC), 2017

This paper proposed the design of quantum cost efficient 4-bit reversible universal shift registe... more This paper proposed the design of quantum cost efficient 4-bit reversible universal shift register(RUSR) using existing reversible logic gates. The proposed design is very useful in quantum computing due to its low quantum cost, less no. of reversible logic gate and low garbage outputs. The quantum cost(QC), garbage output(GO), number of gates are respectively 68, 20 and 16 for proposed work.

Research paper thumbnail of Design of quantum cost efficient MOD-8 synchronous UP/DOWN counter using reversible logic gate

Research paper thumbnail of Design of Quantum Cost and Delay Optimized Code Converter Using New Reversible Quantum Circuit Block (QCB)

Micro and Nanosystems, 2021

Background: In this article, we have proposed a new reversible quantum circuit block along with t... more Background: In this article, we have proposed a new reversible quantum circuit block along with the quantum cost (QC), constant input (CI), garbage output (GO) and delay optimized code converterusing quantum circuit block. Method: Initially, new quantum circuit block has been designed and later reversible code converter circuits have been implemented using it. The proposed new quantum blockused to design 2’s complement code converter (2SCCC), cost efficient BCD to Excess-3 code converter (BECC) and can also be used to implement different logic functions. The QC of proposed quantum circuit block is 8. The QC and delay of the proposed 2SCCC is 8 and 1 respectively. Similarly, the QC and delay of the proposed BECC is 11 and 2 respectively. The proposed cost efficient BECC is designed using two NOT gate, one Feynman gate and one new quantum circuit block with QC is 11. Results: The improvement of QC for 2SCCC and BECC are 27.27 % and 21.43% respectively. The improvement of delay for 2SC...

Research paper thumbnail of The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block

Micro and Nanosystems, 2019

Aim and Objective: This paper presents the quantum cost, garbage output, constant input and numbe... more Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

Research paper thumbnail of Design of Reversible Shift Register Using Reduced Number of Logic Gates

Micro and Nanosystems, 2020

Background: Over the last few decades, reversible logic system/circuits have received considerabl... more Background: Over the last few decades, reversible logic system/circuits have received considerable attention in the diversified fields such as nanotechnology, quantum computing, cryptography, optical computing and low power design of VLSI circuits due to their low power dissipation characteristics. Methods: In this paper, we proposed the design of reversible shift register (SR) i.e. serial-in-serial out (SISO), serial-in-parallel out (SIPO), parallel-in-serial out (PISO) and parallel-in-parallel out (PIPO) SR using a reduced number of reversible logic gates and garbage output. Results: As compared to previously reported results, the improvement in our proposed model of SISO, SIPO, PISO and PIPO was found to be 50 – 66.66 %, 42.85 – 66.66 %, 12.5 – 53.33 % and 50 – 66.66 % respectively, in terms of the number of reversible logic gates.

Research paper thumbnail of Design of Reversible Combinational Circuits Using New Reversible Logic Gate

Journal of Engineering Science and Technology Review, 2018

In this paper the authors have proposed a new 3×3 reversible gate and also proposed the reversibl... more In this paper the authors have proposed a new 3×3 reversible gate and also proposed the reversible combinational logic circuits with better optimized quantum cost, garbage outputs and delay. The proposed new reversible logic gate is used to design of reversible 1-bit comparator circuit and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed new reversible logic gate is represented by quantum implementation. The quantum cost of proposed gate is 4. The quantum cost, garbage output and delay of proposed reversible 1-bit comparator circuit are 6 which is better w. r. t. previously reported results.

Research paper thumbnail of Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate

International Journal of Quantum Information, 2018

In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible log... more In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.

Research paper thumbnail of Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

International Journal of Quantum Information, 2018

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible univer... more In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

Research paper thumbnail of Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

Journal of Circuits, Systems and Computers, 2018

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), ... more In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Research paper thumbnail of A Novel Design of MOD-8 Synchronous UP/DOWN Counter Using Reversible Gate

International Journal of Scientific Research and Education, Sep 27, 2014

The Reversible logic synthesis techniques will definitely be a necessary part of the long-term fu... more The Reversible logic synthesis techniques will definitely be a necessary part of the long-term future of computing due to its low power dissipating characteristic. Today, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, and low power design of circuits. In this paper we proposed the design of MOD-8 synchronous up/down counter which uses existing reversible gates and derived quantum cost, constant inputs and number of gates to implement it.

Research paper thumbnail of Design and Development of 4-Bit Gray Code Counter Circuit Using Reversible Logic Gate

Micro and Nanosystems, 2021

Aim: This paper proposed the design and development of 4-Bit Gray Code Counter Circuit Using Reve... more Aim: This paper proposed the design and development of 4-Bit Gray Code Counter Circuit Using Reversible Logic Gate. Methods: The 4-Bit Gray Code Counter Circuit can be design using SAM gate, Feynman gate (FG), double Feynman gate (DFG) and NOT gate. The proposed circuit is the combined application of 4-bit binary asynchronous counter and 4-bit binary to gray code converter circuit. Results: The proposed gray code counter is designed using four no. of SAM gate, three no. of DFG, one FG and seven reversible NOT gate. The QC, GO and CI of proposed circuit are correspondingly 30, 4 and 7. Conclusion: The novel reversible gray code counter have been designed using existing reversible logic gate. The proposed gray code counter is designed using four no. of SAM gate, three no. of DFG, one FG and seven reversible NOT gate. The QC, GO and CI of proposed circuit are correspondingly 30, 4 and 7.