Malek Souilem - Academia.edu (original) (raw)

Papers by Malek Souilem

Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Mestrado em Engenharia e Gestão IndustrialNowadays, the globalized economy leads the emergence of... more Mestrado em Engenharia e Gestão IndustrialNowadays, the globalized economy leads the emergence of highly competitive companies. Many companies are competing not only to keep track and boost their customer’s satisfaction but also to look for other potential resources, to increase their market share regarding other competitors. The companies have to organize their business and internal processes in order to maximize efficiency and therefore achieve their objectives and maintain their growth and expansion in a very struggling economy constrained by austerity. For these reasons, the companies need to manage their industrial production/business process towards reducing the cost while maintaining high quality products or services to maintain and attract more customers. This seems clearly a conflicting situation, however, it is possible for the companies to balance these tradeoffs by implementing the methodologies of continuous quality improvement, waste minimization, and cost reduction si...

Nowadays, the globalized economy leads the emergence of highly competitive companies. Many compan... more Nowadays, the globalized economy leads the emergence of highly competitive companies. Many companies are competing not only to keep track and boost their customer's satisfaction but also to look for other potential resources, to increase their market share regarding other competitors. The companies have to organize their business and internal processes in order to maximize efficiency and therefore achieve their objectives and maintain their growth and expansion in a very struggling economy constrained by austerity.

Sensors, Aug 30, 2022

This article is an open access article distributed under the terms and conditions of the Creative... more This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY

I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO)

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)

This paper presents an assessment of jitter induced by power and ground (P/G) voltage variations.... more This paper presents an assessment of jitter induced by power and ground (P/G) voltage variations. The assessment is based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output buffers. The implemented large signal equivalent-circuit model is validated under different test conditions having different P/G voltage variations for predicting the output signal distortions. The associated jitter analysis by predicting the eye diagram under the noise conditions is performed. The maximum prediction error for the peak to peak values of eye jitter and eye height are 7.06% and 2.59%, respectively.

Wirelessly Powered Unmanned Aerial Vehicles (UAVs) in Smart City

Connected and Autonomous Vehicles in Smart Cities, 2020

Dynamic Clustering for Power Effective Small Cell Deployment in HetNet 5G Networks

ICC 2020 - 2020 IEEE International Conference on Communications (ICC), 2020

This paper presents an improved algorithm for small cell (SCs) deployment in the heterogeneous ne... more This paper presents an improved algorithm for small cell (SCs) deployment in the heterogeneous network (HetNet) future generations of mobile networks. The sequential and fixed number of the SCs deployment is formulated as ajoint optimization of load balancing and interference (JOLBI) minimization over the number and locations of the distributed user equipment (UE) forming a hotspot (HS). Then, the SCs are adaptively powered ON or OFF according to outcomes of the proposed clustering algorithms applied to the UEs’ distribution. The conceived integrated solution of the JOBLI and clustering algorithm does not only satisfy the coverage constraint and maximize the minimum user throughput of the HetNet, but also enables an energy effective SCs deployment. The simulation results show that this JOLBI and clustering algorithm enables a power saving of the whole network by 35% when HS of UEs are considered in the network simulations.

Wireless Power Transfer and Data Communication Cognitive Radio through Two-Coil Inductive Channel

2019 IEEE Global Communications Conference (GLOBECOM), 2019

This paper investigates two-coil inductive channel for an efficient Wireless Power Transfer (WPT)... more This paper investigates two-coil inductive channel for an efficient Wireless Power Transfer (WPT), while intelligently enabling high-data rate communication. The analysis is based on the power efficiency and channel capacity performance, which are determined based on the multiport scattering (S)-parameters numerical simulation results, using a lumped equivalent circuit model. Different access points and configuration scenarios, along with the decoupling filters design consideration of power and data links, were compared in order to cognitively share the two-coil inductive channel, for handling both high-power signal and low-power modulated high- frequency data signal. The performance of the transmission and isolation between the power and data link is evaluated. The theoretical channel capacity of the proposed two-coil circuit is calculated, as a function of the coupling coefficient k12, as well as in the presence of an additive white Gaussian noise and signal to noise ratio. This paper adds to the intelligence and cognition of the radio, to efficiently use the limited available spectrum for broadband communications, in addition to power transmission, simultaneously.

Pre-driver Modeling and Jitter Estimation under Power Supply Noise

2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021

This paper presents the development of nonlinear dynamic behavioral model of the IO buffer circui... more This paper presents the development of nonlinear dynamic behavioral model of the IO buffer circuits' pre-driver stage. A time delay neural network structure is developed to model the electrical circuit behavior of pre-driver in order to identify the mathematical relationship between the input voltage and output switching timing signals under power supply voltage variation. Therefore, the pre-driver model is combined with the last-stage output buffer model to illustrate the improved accuracy of the proposed modelling for capturing the supply variation induced jitter. For instance, the proposed modeling approach presents jitter peak-to-peak error about 9.84% while IBIS like model presents 88% when compared to reference transistor level model.

A Study on an IBIS-like Model to Ensure Signal/Power Integrity for I/O Drivers

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN), 2021

This paper presents a study on non-linear modeling, reported in the state-of-the-art in the last ... more This paper presents a study on non-linear modeling, reported in the state-of-the-art in the last decade for I/O drivers. The study includes the IBIS-like modeling techniques including package parasitics. The IBIS-like model has been analyzed mathematically and validated using 28 nm CMOS technology of TSMC foundry. For validation purposes, the predriver circuit and the I/O buffers have been simulated with 0.9 V of VDD. The IBIS-like nonlinear models have been created using Simulink® and the results have been compared with the Electronic Design Automation (EDA) tools. The Simulink® results show a Normalized Mean Square Error (NMSE) of - 51.91 dB with 1.63 sec of CPU time for the case of pull-up current, -49.42 dB with 474.34 msec of CPU time for the case of pulldown current response. In the case of output voltage response, the NMSE is - 48.33 dB and 2.12 sec of CPU time.

Sensors, 2021

This paper presents a neural-network based nonlinear behavioral modelling of I/O buffer that acco... more This paper presents a neural-network based nonlinear behavioral modelling of I/O buffer that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variations. Model structure and I/O device characterization along with extraction procedure were described. The last stage of the I/O buffer is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The mathematical model structure of the predriver was derived from the analysis of the large-signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure was considered in this work. Timing series data which reflects the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, were used to train the NN model. The proposed model was implemented ...

Mathematical Problems in Engineering, 2018

This paper presents the development and evaluation of a large-signal equivalent circuit model tha... more This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good pred...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018

This paper addresses the development of a behavioral modeling abstraction methodology that reduce... more This paper addresses the development of a behavioral modeling abstraction methodology that reduces the model order complexity of the transistor level physical model describing the input-output (I/O) buffers that interface the digital (i.e., discrete) and the analog world in the high-speed digital communication I/O links. In fact, the proposed high-level hybrid automaton behavioral model (HABM) is analyzed as a mixedsignal modeling approach that combines both discrete and continuous abstractions. The modeling framework investigates the quantization of the on-off nonreturn-to-zero input signal to analyze the mixed signal behavior of the predriver and the analog dynamics of the I/O buffer's last stage for easing the model's extraction and running complexities while accurately predicting the I/O buffer's nonlinear switching behavior under normal and overclocking conditions. The time decomposition of the input and state variables enables the approximation of the predriver's nonlinear dynamic by means of digitally controlled linear dynamic filters. The filter's outputs are multiplexed and integrated with the continuous-time nonlinear dynamic model of driver's last stage output admittances. The implemented mixedsignal HABM presents more accurate transient simulation results than the I/O buffer information specification algorithm when assessing the signal integrity performance while alleviating the computational cost under overclocking operation.

2019 IEEE 23rd Workshop on Signal and Power Integrity (SPI), 2019