Margrit Krug - Academia.edu (original) (raw)
Papers by Margrit Krug
O projeto, seja ele de software ou hardware, envolve uma série de atividades que, apesar das técn... more O projeto, seja ele de software ou hardware, envolve uma série de atividades que, apesar das técnicas, ferramentas e métodos empregados, não estão livres de erros que podem levar ao mau funcionamento do produto final. Estes erros podem ocorrer durante a especificação do projeto, como também em estágios finais do desenvolvimento ou no processo de manufatura. A fim de minimizar prejuízos é necessário garantir a qualidade do sistema a partir da verificação do projeto, da validação de protótipo e do teste de fabricação. Por muito tempo o teste de hardware e o teste de software foram estudados como disciplinas completamente independentes. Porém, similaridades entre o desenvolvimento de software e o projeto de hardware já foram exploradas com sucesso em adaptações de técnicas originalmente desenvolvidas para um sendo utilizadas por outro. Um exemplo é a cobertura de código, que foi inicialmente desenvolvida para o teste de software, e agora é comumente utilizada na verificação de hardware...
O estudo de sistemas embarcados de tempo real e dos diferentes algoritmos de escalonamento aprese... more O estudo de sistemas embarcados de tempo real e dos diferentes algoritmos de escalonamento apresenta um elevado grau de complexidade. O estudo teorico de sistemas de tempo real nao possibilita aos estudantes o trato com problemas praticos relacionados a area, necessarios a fixacao e aprofundamento dos conteudos estudados em sala de aula. Grande parte do estudo pratico dos sistemas embarcados e de tempo real se limita ao uso de sistemas prontos que nao apresentam falhas, impedindo que o aluno aprenda o processo de construcao do software de tempo real. Para resolver este problema, o Grupo de Pesquisa em Sistemas Embarcados da UERGS em Guaiba definiu e implementou o RT-NKE, um nanokernel de tempo real escrito em linguagem C para microprocessadores ARM. O sistema possui cerca de 2600 linhas de codigo e conta com uma estrutura modular, o que possibilita aos estudantes uma experiencia pratica com sistemas operacionais de tempo real. O objetivo desse trabalho foi o de implementar e avalia...
This work presents the study and preliminary results of the high level implementation of a self-c... more This work presents the study and preliminary results of the high level implementation of a self-checking Profibus slave. From an existing VHDL description of the device, a test strategy was studied and implemented, so that the whole circuit has embedded test structures capable to perform at-speed test of the slave. In this paper, we show the used test strategies and implementation results achieved from a synthesis process in a FPGA environment.
2006 IFIP International Conference on Very Large Scale Integration, 2006
ABSTRACT Current hardware design flows include test pattern generation as a single step to be per... more ABSTRACT Current hardware design flows include test pattern generation as a single step to be performed only after logical synthesis. However, early generation of few high level test patterns can provide higher test quality and reduce ATPG effort. In this work, the authors apply a software engineering technique for control flow based path testing, to extract test vectors from the behavioral HDL description of digital circuits. The authors show how one can adapt this software testing approach to test hardware devices. Experimental results show that combining high level generated test vectors with gate level ATPG can improve test quality, either increasing fault coverage and/or reducing test set size
Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06, 2006
Scan design has been widely used to ease test generation process for digital circuits. Although f... more Scan design has been widely used to ease test generation process for digital circuits. Although full scan approach results in high fault coverage while reducing ATPG effort, it introduces area and performance overheads that are most times unacceptable. Hence, partial scan is a commonly used technique to improve testability of sequential circuits while respecting design constraints. In this paper, we
Matching the results achieved during circuit simulation with those extracted from circuit functio... more Matching the results achieved during circuit simulation with those extracted from circuit functioning is a common verification process. A large number of current verification techniques use the input / output vectors produced during functional simulation as the test vectors applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes a solution for verifying digital designs implemented in currently commercial available CPLDs. All internal flip-flops are included in a scan-chain accessible through the BST infrastructure (using a user-defined optional instruction), while the BS cells are used to apply the input test vectors and capture the circuit responses. These BS cells can either belong to the device-under-test or to other devices, the first controlled through the optional INTEST instruction and the second controlled through the mandatory EXTEST instruction. To speed up the verification process, the test program is automatically generated from information that encompasses the design & development phase.
Matching the results obtained from circuit simulation with those extracted from circuit functioni... more Matching the results obtained from circuit simulation with those extracted from circuit functioning is a common stage of the final verification process. Many current verification techniques use the I/O vectors produced during functional and/or timing simulation, for creating the test vectors to be applied/compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes such a solution for ...
administradores.com.br
... david.fabiano@gmail.com, margrit.senac@gmail.com ... 2 Daniela Camarinha é Administradora de ... more ... david.fabiano@gmail.com, margrit.senac@gmail.com ... 2 Daniela Camarinha é Administradora de Empresas, Pós-graduanda em Gestão Empresarial pelo Instituto Trevisan e em curso de MBA em Marketing de Serviços e Comunicação. ...
The teaching and learning of operating systems are hampered due to the complex nature of concepts... more The teaching and learning of operating systems are hampered due to the complex nature of concepts involved. It is necessary not only theoretical studies, but importantly the laboratory practices, which are not always possible due to the lack of appropriate software instruments. This paper presents the NKE, a Nanokernel-based OS developed for ARM microprocessors and oriented to the teaching support for practical activities in operating systems classes. The NKE is developed in C language and has been successfully used in laboratory practices as part of OS and embedded systems classes. The results obtained so far are very exciting, given that the NKE promoted richer teaching and learning experiences, providing to the students a real environment for embedded OS development.
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387), 1999
This work presents the preliminary results obtained for the high level implementation of a self-t... more This work presents the preliminary results obtained for the high level implementation of a self-testing 8051 microprocessor. From an existing VHDL description of the microprocessor, six main blocks were identified: a state generation block, a control unit, a validation block, ...
O projeto, seja ele de software ou hardware, envolve uma série de atividades que, apesar das técn... more O projeto, seja ele de software ou hardware, envolve uma série de atividades que, apesar das técnicas, ferramentas e métodos empregados, não estão livres de erros que podem levar ao mau funcionamento do produto final. Estes erros podem ocorrer durante a especificação do projeto, como também em estágios finais do desenvolvimento ou no processo de manufatura. A fim de minimizar prejuízos é necessário garantir a qualidade do sistema a partir da verificação do projeto, da validação de protótipo e do teste de fabricação. Por muito tempo o teste de hardware e o teste de software foram estudados como disciplinas completamente independentes. Porém, similaridades entre o desenvolvimento de software e o projeto de hardware já foram exploradas com sucesso em adaptações de técnicas originalmente desenvolvidas para um sendo utilizadas por outro. Um exemplo é a cobertura de código, que foi inicialmente desenvolvida para o teste de software, e agora é comumente utilizada na verificação de hardware...
O estudo de sistemas embarcados de tempo real e dos diferentes algoritmos de escalonamento aprese... more O estudo de sistemas embarcados de tempo real e dos diferentes algoritmos de escalonamento apresenta um elevado grau de complexidade. O estudo teorico de sistemas de tempo real nao possibilita aos estudantes o trato com problemas praticos relacionados a area, necessarios a fixacao e aprofundamento dos conteudos estudados em sala de aula. Grande parte do estudo pratico dos sistemas embarcados e de tempo real se limita ao uso de sistemas prontos que nao apresentam falhas, impedindo que o aluno aprenda o processo de construcao do software de tempo real. Para resolver este problema, o Grupo de Pesquisa em Sistemas Embarcados da UERGS em Guaiba definiu e implementou o RT-NKE, um nanokernel de tempo real escrito em linguagem C para microprocessadores ARM. O sistema possui cerca de 2600 linhas de codigo e conta com uma estrutura modular, o que possibilita aos estudantes uma experiencia pratica com sistemas operacionais de tempo real. O objetivo desse trabalho foi o de implementar e avalia...
This work presents the study and preliminary results of the high level implementation of a self-c... more This work presents the study and preliminary results of the high level implementation of a self-checking Profibus slave. From an existing VHDL description of the device, a test strategy was studied and implemented, so that the whole circuit has embedded test structures capable to perform at-speed test of the slave. In this paper, we show the used test strategies and implementation results achieved from a synthesis process in a FPGA environment.
2006 IFIP International Conference on Very Large Scale Integration, 2006
ABSTRACT Current hardware design flows include test pattern generation as a single step to be per... more ABSTRACT Current hardware design flows include test pattern generation as a single step to be performed only after logical synthesis. However, early generation of few high level test patterns can provide higher test quality and reduce ATPG effort. In this work, the authors apply a software engineering technique for control flow based path testing, to extract test vectors from the behavioral HDL description of digital circuits. The authors show how one can adapt this software testing approach to test hardware devices. Experimental results show that combining high level generated test vectors with gate level ATPG can improve test quality, either increasing fault coverage and/or reducing test set size
Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06, 2006
Scan design has been widely used to ease test generation process for digital circuits. Although f... more Scan design has been widely used to ease test generation process for digital circuits. Although full scan approach results in high fault coverage while reducing ATPG effort, it introduces area and performance overheads that are most times unacceptable. Hence, partial scan is a commonly used technique to improve testability of sequential circuits while respecting design constraints. In this paper, we
Matching the results achieved during circuit simulation with those extracted from circuit functio... more Matching the results achieved during circuit simulation with those extracted from circuit functioning is a common verification process. A large number of current verification techniques use the input / output vectors produced during functional simulation as the test vectors applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes a solution for verifying digital designs implemented in currently commercial available CPLDs. All internal flip-flops are included in a scan-chain accessible through the BST infrastructure (using a user-defined optional instruction), while the BS cells are used to apply the input test vectors and capture the circuit responses. These BS cells can either belong to the device-under-test or to other devices, the first controlled through the optional INTEST instruction and the second controlled through the mandatory EXTEST instruction. To speed up the verification process, the test program is automatically generated from information that encompasses the design & development phase.
Matching the results obtained from circuit simulation with those extracted from circuit functioni... more Matching the results obtained from circuit simulation with those extracted from circuit functioning is a common stage of the final verification process. Many current verification techniques use the I/O vectors produced during functional and/or timing simulation, for creating the test vectors to be applied/compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes such a solution for ...
administradores.com.br
... david.fabiano@gmail.com, margrit.senac@gmail.com ... 2 Daniela Camarinha é Administradora de ... more ... david.fabiano@gmail.com, margrit.senac@gmail.com ... 2 Daniela Camarinha é Administradora de Empresas, Pós-graduanda em Gestão Empresarial pelo Instituto Trevisan e em curso de MBA em Marketing de Serviços e Comunicação. ...
The teaching and learning of operating systems are hampered due to the complex nature of concepts... more The teaching and learning of operating systems are hampered due to the complex nature of concepts involved. It is necessary not only theoretical studies, but importantly the laboratory practices, which are not always possible due to the lack of appropriate software instruments. This paper presents the NKE, a Nanokernel-based OS developed for ARM microprocessors and oriented to the teaching support for practical activities in operating systems classes. The NKE is developed in C language and has been successfully used in laboratory practices as part of OS and embedded systems classes. The results obtained so far are very exciting, given that the NKE promoted richer teaching and learning experiences, providing to the students a real environment for embedded OS development.
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387), 1999
This work presents the preliminary results obtained for the high level implementation of a self-t... more This work presents the preliminary results obtained for the high level implementation of a self-testing 8051 microprocessor. From an existing VHDL description of the microprocessor, six main blocks were identified: a state generation block, a control unit, a validation block, ...