Mark Gajda - Academia.edu (original) (raw)

Papers by Mark Gajda

IEEE Transactions on Electron Devices, Apr 1, 2018

Semiconductor Science and Technology, Aug 9, 2021

IEEE Transactions on Electron Devices, 2017

This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs su... more This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs submitted to high-voltage stress. The analysis was carried out on transistors with different lengths of the drain-side gatehead (LGH), corresponding to different levels of electric field across the SiN passivation. Based on dc measurements, 2-D simulations, and optical analysis, we demonstrate the following original results: 1) when submitted to high drain voltages (in the OFF-state), the transistors can show catastrophic failure; 2) electroluminescence microscopy indicates the presence of hot-spots on the drain-side of the gate; 2-D simulations support the hypothesis that failure occurs in correspondence of the gate-head, on the drainside edge, where the electric field in the silicon nitride passivation has its maximum; 3) this hypothesis is confirmed by the results of transmission electron microscope failure analysis that demonstrate the generation of a leakage path between the gate metal and the channel, 4) and by the dependence of the destructive voltage on the LGH value. 5) in addition, we propose and demonstrate an approach for improving the reliability of the devices, i.e., using a graded SiN passivation with increased thickness. The results described in this paper provide important information for the device optimization of Schottky-gated HEMTs.

IEEE Transactions on Electron Devices, Oct 1, 2018

IEEE Transactions on Electron Devices, Mar 1, 2020

Applied Physics Letters, Jun 30, 2014

IEEE Transactions on Electron Devices, 2017

The piezoelectric stress distribution induced in the GaN layer of AlGaN/GaN Schottky Barrier Diod... more The piezoelectric stress distribution induced in the GaN layer of AlGaN/GaN Schottky Barrier Diodes (SBDs) under a DC reverse voltage of -250 V is directly measured using micro-Raman spectroscopy. The highest piezoelectric stress measurable near the anode fieldplate edge is 380 ± 40 MPa, which is similar to the stress measured in an AlGaN/GaN SBD under reverse-bias cycling at -400 V in a high voltage DC-DC boost converter circuit. Continuous operation of the SBD under this stress cycling condition may lead to cracking of the GaN layer and in turn degradation of the device, which may pose a reliability concern in such boost converter circuits.

Semiconductor Science and Technology, 2021

In this paper, we investigate the charge trapping in power AlGaN/GaN high electron mobility trans... more In this paper, we investigate the charge trapping in power AlGaN/GaN high electron mobility transistors which occurs in ON-state operation (V DS = 40 V, V GS = 0 V, I DS = 0.18 A mm−1). By analysing the dynamic ON-resistance (R ON) after OFF-state and ON-state stress in devices with different SiN x passivation stoichiometries, we find that this charge trapping can be largely suppressed by a high Si concentration passivation. Both potential probe and electroluminescence (EL) measurements further confirm that the stress can induce negative charge trapping in the gate–drain access region. It is shown that EL is generated as expected under the field plates at the gate edge, but is obscured by the field plates and is actually emitted from the device near the drain edge; hence care is required when using EL alone as a guide to the location of the high field region in the device. From temperature-dependent dynamic R ON transient measurements, we determine that the apparent activation energ...

IEEE Transactions on Electron Devices, 2017

The interaction offabrication processes anddevice performance inRSO (Resurf Stepped Oxide) transi... more The interaction offabrication processes anddevice performance inRSO (Resurf Stepped Oxide) transistors is explored inthis paper.Critical process steps forachieving -l good control ofresurf behaviour aretheetching ofthedeep trenches, their refill withthick oxide andetch-back todefine theoxide step. Optimum conditions result intypical Rspec of 46mQ.mmaataBVdssof80Vanddefect densities less than 3CMI.Qgdvalues ofabout 9nC/MM2 limit thesingle-gate f polysilicon RSOstaructure tolowfrequency applications, such asswitching automotive loads. Simulation hasindicated that theintroduction ofa split-polysilico n RSO stdructure, with

IEEE Transactions on Electron Devices, 2017

This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs su... more This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs submitted to high-voltage stress. The analysis was carried out on transistors with different lengths of the drain-side gatehead (LGH), corresponding to different levels of electric field across the SiN passivation. Based on dc measurements, 2-D simulations, and optical analysis, we demonstrate the following original results: 1) when submitted to high drain voltages (in the OFF-state), the transistors can show catastrophic failure; 2) electroluminescence microscopy indicates the presence of hot-spots on the drain-side of the gate; 2-D simulations support the hypothesis that failure occurs in correspondence of the gate-head, on the drainside edge, where the electric field in the silicon nitride passivation has its maximum; 3) this hypothesis is confirmed by the results of transmission electron microscope failure analysis that demonstrate the generation of a leakage path between the gate metal and the channel, 4) and by the dependence of the destructive voltage on the LGH value. 5) in addition, we propose and demonstrate an approach for improving the reliability of the devices, i.e., using a graded SiN passivation with increased thickness. The results described in this paper provide important information for the device optimization of Schottky-gated HEMTs.

IEEE Transactions on Electron Devices, 2018

IEEE Transactions on Electron Devices, 2020

IEEE Transactions on Electron Devices, 2017

2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2016

The piezoelectric stress distribution induced in the GaN layer of AlGaN/GaN Schottky Barrier Diod... more The piezoelectric stress distribution induced in the GaN layer of AlGaN/GaN Schottky Barrier Diodes (SBDs) under a DC reverse voltage of -250 V is directly measured using micro-Raman spectroscopy. The highest piezoelectric stress measurable near the anode fieldplate edge is 380 ± 40 MPa, which is similar to the stress measured in an AlGaN/GaN SBD under reverse-bias cycling at -400 V in a high voltage DC-DC boost converter circuit. Continuous operation of the SBD under this stress cycling condition may lead to cracking of the GaN layer and in turn degradation of the device, which may pose a reliability concern in such boost converter circuits.

2006 IEEE International Symposium on Power Semiconductor Devices & IC's

The interaction of fabrication processes and device performance in RSO (resurf stepped oxide) tra... more The interaction of fabrication processes and device performance in RSO (resurf stepped oxide) transistors is explored in this paper. Critical process steps for achieving good control of resurf behaviour are the etching of the deep trenches, their refill with thick oxide and etch-back to define the oxide step. Optimum conditions result in typical Rspec of 46mOmega.mm2 at a BVdss of

IEEE Transactions on Electron Devices, Apr 1, 2018

Semiconductor Science and Technology, Aug 9, 2021

IEEE Transactions on Electron Devices, 2017

This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs su... more This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs submitted to high-voltage stress. The analysis was carried out on transistors with different lengths of the drain-side gatehead (LGH), corresponding to different levels of electric field across the SiN passivation. Based on dc measurements, 2-D simulations, and optical analysis, we demonstrate the following original results: 1) when submitted to high drain voltages (in the OFF-state), the transistors can show catastrophic failure; 2) electroluminescence microscopy indicates the presence of hot-spots on the drain-side of the gate; 2-D simulations support the hypothesis that failure occurs in correspondence of the gate-head, on the drainside edge, where the electric field in the silicon nitride passivation has its maximum; 3) this hypothesis is confirmed by the results of transmission electron microscope failure analysis that demonstrate the generation of a leakage path between the gate metal and the channel, 4) and by the dependence of the destructive voltage on the LGH value. 5) in addition, we propose and demonstrate an approach for improving the reliability of the devices, i.e., using a graded SiN passivation with increased thickness. The results described in this paper provide important information for the device optimization of Schottky-gated HEMTs.

IEEE Transactions on Electron Devices, Oct 1, 2018

IEEE Transactions on Electron Devices, Mar 1, 2020

Applied Physics Letters, Jun 30, 2014

IEEE Transactions on Electron Devices, 2017

The piezoelectric stress distribution induced in the GaN layer of AlGaN/GaN Schottky Barrier Diod... more The piezoelectric stress distribution induced in the GaN layer of AlGaN/GaN Schottky Barrier Diodes (SBDs) under a DC reverse voltage of -250 V is directly measured using micro-Raman spectroscopy. The highest piezoelectric stress measurable near the anode fieldplate edge is 380 ± 40 MPa, which is similar to the stress measured in an AlGaN/GaN SBD under reverse-bias cycling at -400 V in a high voltage DC-DC boost converter circuit. Continuous operation of the SBD under this stress cycling condition may lead to cracking of the GaN layer and in turn degradation of the device, which may pose a reliability concern in such boost converter circuits.

Semiconductor Science and Technology, 2021

In this paper, we investigate the charge trapping in power AlGaN/GaN high electron mobility trans... more In this paper, we investigate the charge trapping in power AlGaN/GaN high electron mobility transistors which occurs in ON-state operation (V DS = 40 V, V GS = 0 V, I DS = 0.18 A mm−1). By analysing the dynamic ON-resistance (R ON) after OFF-state and ON-state stress in devices with different SiN x passivation stoichiometries, we find that this charge trapping can be largely suppressed by a high Si concentration passivation. Both potential probe and electroluminescence (EL) measurements further confirm that the stress can induce negative charge trapping in the gate–drain access region. It is shown that EL is generated as expected under the field plates at the gate edge, but is obscured by the field plates and is actually emitted from the device near the drain edge; hence care is required when using EL alone as a guide to the location of the high field region in the device. From temperature-dependent dynamic R ON transient measurements, we determine that the apparent activation energ...

IEEE Transactions on Electron Devices, 2017

The interaction offabrication processes anddevice performance inRSO (Resurf Stepped Oxide) transi... more The interaction offabrication processes anddevice performance inRSO (Resurf Stepped Oxide) transistors is explored inthis paper.Critical process steps forachieving -l good control ofresurf behaviour aretheetching ofthedeep trenches, their refill withthick oxide andetch-back todefine theoxide step. Optimum conditions result intypical Rspec of 46mQ.mmaataBVdssof80Vanddefect densities less than 3CMI.Qgdvalues ofabout 9nC/MM2 limit thesingle-gate f polysilicon RSOstaructure tolowfrequency applications, such asswitching automotive loads. Simulation hasindicated that theintroduction ofa split-polysilico n RSO stdructure, with

IEEE Transactions on Electron Devices, 2017

This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs su... more This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs submitted to high-voltage stress. The analysis was carried out on transistors with different lengths of the drain-side gatehead (LGH), corresponding to different levels of electric field across the SiN passivation. Based on dc measurements, 2-D simulations, and optical analysis, we demonstrate the following original results: 1) when submitted to high drain voltages (in the OFF-state), the transistors can show catastrophic failure; 2) electroluminescence microscopy indicates the presence of hot-spots on the drain-side of the gate; 2-D simulations support the hypothesis that failure occurs in correspondence of the gate-head, on the drainside edge, where the electric field in the silicon nitride passivation has its maximum; 3) this hypothesis is confirmed by the results of transmission electron microscope failure analysis that demonstrate the generation of a leakage path between the gate metal and the channel, 4) and by the dependence of the destructive voltage on the LGH value. 5) in addition, we propose and demonstrate an approach for improving the reliability of the devices, i.e., using a graded SiN passivation with increased thickness. The results described in this paper provide important information for the device optimization of Schottky-gated HEMTs.

IEEE Transactions on Electron Devices, 2018

IEEE Transactions on Electron Devices, 2020

IEEE Transactions on Electron Devices, 2017

2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2016

The piezoelectric stress distribution induced in the GaN layer of AlGaN/GaN Schottky Barrier Diod... more The piezoelectric stress distribution induced in the GaN layer of AlGaN/GaN Schottky Barrier Diodes (SBDs) under a DC reverse voltage of -250 V is directly measured using micro-Raman spectroscopy. The highest piezoelectric stress measurable near the anode fieldplate edge is 380 ± 40 MPa, which is similar to the stress measured in an AlGaN/GaN SBD under reverse-bias cycling at -400 V in a high voltage DC-DC boost converter circuit. Continuous operation of the SBD under this stress cycling condition may lead to cracking of the GaN layer and in turn degradation of the device, which may pose a reliability concern in such boost converter circuits.

2006 IEEE International Symposium on Power Semiconductor Devices & IC's

The interaction of fabrication processes and device performance in RSO (resurf stepped oxide) tra... more The interaction of fabrication processes and device performance in RSO (resurf stepped oxide) transistors is explored in this paper. Critical process steps for achieving good control of resurf behaviour are the etching of the deep trenches, their refill with thick oxide and etch-back to define the oxide step. Optimum conditions result in typical Rspec of 46mOmega.mm2 at a BVdss of