Martin Schmatz - Academia.edu (original) (raw)

Papers by Martin Schmatz

Research paper thumbnail of Improvements on a MOSFET model for non-linear RF simulations

1997 IEEE MTT-S International Microwave Symposium Digest, 1997

As the gate lengths of silicon MOSFETs become smaller and smaller, these devices are usable to fr... more As the gate lengths of silicon MOSFETs become smaller and smaller, these devices are usable to frequencies in the GHz range. The non-linear MOSFET model presented in this paper is based on S-parameter measurements over a large bias range and has been implemented in a SPICE simulator. The improvements consist of new equations for the non-linear capacitances and output conductance

Research paper thumbnail of Optical links for printed circuit boards

The 16th Annual Meeting of the IEEE Lasers and Electro-Optics Society, 2003. LEOS 2003., 2003

Research paper thumbnail of Electrical and optical transceivers for short-range data communication, fabricated in VLSI 90-nm bulk and SOI CMOS technology

IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05., 2005

Research paper thumbnail of A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006

A DC-to-44GHz amplifier with 19dB differential gain in a standard 90nm CMOS technology is present... more A DC-to-44GHz amplifier with 19dB differential gain in a standard 90nm CMOS technology is presented. Capacitive bandwidth and group-delay enhancements are combined with series peaking in a shunt-peaking amplifier. The circuit occupies 0.02mm2 and dissipates 57mW at 1V

Research paper thumbnail of Effect of body contacts on high-speed circuits in 90 nm CMOS SOI technology

International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005., 2005

Page 1. Effect of Body Contacts on High-Speed Circuits in 90 nm CMOS SOI Technology Jonas RM Weis... more Page 1. Effect of Body Contacts on High-Speed Circuits in 90 nm CMOS SOI Technology Jonas RM Weiss', Christian Menolfi1, Thomas Morf1, Martin L. Schmatz1, Heinz Jaeckel2 1 IBM Zurich Research Laboratory, 8803 Rtlschlikon ...

Research paper thumbnail of When Virtual Meets Physical at the Edge

ACM SIGMETRICS Performance Evaluation Review, 2015

Research paper thumbnail of BiCMOS Variable Gain LNA at C-Band with Ultra Low Power Consumption for WLAN

Lecture Notes in Computer Science, 2004

Research paper thumbnail of High-Q inductors on digital VLSI CMOS substrate for analog RF applications

Proceedings of the 2003 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference - IMOC 2003. (Cat. No.03TH8678), 2003

Research paper thumbnail of <title>Challenges for the introduction of board-level optical interconnect technology into product development roadmaps</title>

Optoelectronic Integrated Circuits VIII, 2006

Optical interconnects have gradually replaced electrical interconnects in the long-distance telec... more Optical interconnects have gradually replaced electrical interconnects in the long-distance telecom, local-area, and rackto- rack link classes. We believe that this transition will also happen in the card-backplane-card datacom link class, both for bandwidth*length reasons and for density reasons. In analogy to the transition from individually wired boards to integrated printed circuit boards, we believe that eventually board-level optical interconnects

Research paper thumbnail of Member. /EEE, Christian Kromer

Research paper thumbnail of Technology independent degradation of minimum noise figure due to pad parasitics

1998 IEEE MTT-S International Microwave Symposium Digest (Cat. No.98CH36192), 1998

In order to investigate the influence of pad parasitics on device noise performance, noise parame... more In order to investigate the influence of pad parasitics on device noise performance, noise parameters on Si CMOS, GaAs MESFET and GaAs p-HEMT transistors were determined. Measurements of devices with various gate widths demonstrate that the parasitic losses of the pads substantially influence the noise performance independent of FET technology. To accurately separate the noise contribution of the pad and

Research paper thumbnail of A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

A 23 (22 data+1 clk) lane source-synchronous RX PHY for server systems is realized in 65 nm CMOS ... more A 23 (22 data+1 clk) lane source-synchronous RX PHY for server systems is realized in 65 nm CMOS supporting FB-DIMM 2 and QP11.0 multiple link protocols at 4.8-6.4 Gb/s. To minimize jitter, either a poly-phase filter or clean-up PLL can be selected for l/Q clock generation. Power consumption of 4.5 mW/Gb/s is achieved in the product-level design by a pulsed

Research paper thumbnail of A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

Research paper thumbnail of <title>Low-cost electro-optical package for use with PCB-embedded waveguides</title>

Active and Passive Optical Components for Communications VII, 2007

We present a novel approach for packaging high-speed opto-electronic 12x-array devices in a compa... more We present a novel approach for packaging high-speed opto-electronic 12x-array devices in a compact, low-cost package for waveguide-based intra-system links. In order to avoid optical signal loss and crosstalk, the mutual alignment between PCB-embedded multimode waveguides and the opto-electronic components needs to be in the order of 5-10 micrometer, which is an order of magnitude tighter than standard PCB manufacturing

Research paper thumbnail of A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006

A divide-by-4 circuit operates for input frequencies from 31 to 41 GHz at signal amplitudes &... more A divide-by-4 circuit operates for input frequencies from 31 to 41 GHz at signal amplitudes &amp;amp;amp;amp;amp;quot;0.5Vpp. The circuit consists of a dynamic followed by a static frequency divider. The dynamic and static frequency dividers consume 2mA and 1mA, respectively, from a 1.1V supply

Research paper thumbnail of ISSCC 2007/SESSION 24/MULTI-GB/s TRANSCEIVERS/24.6

Research paper thumbnail of TRANSACTIONS LETTERS-Synchronization-Low-Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components

Research paper thumbnail of Multiplexer and demultiplexer

Research paper thumbnail of Integrated line driver

Research paper thumbnail of Continuously tunable inductor and method to continuously tune an inductor

Research paper thumbnail of Improvements on a MOSFET model for non-linear RF simulations

1997 IEEE MTT-S International Microwave Symposium Digest, 1997

As the gate lengths of silicon MOSFETs become smaller and smaller, these devices are usable to fr... more As the gate lengths of silicon MOSFETs become smaller and smaller, these devices are usable to frequencies in the GHz range. The non-linear MOSFET model presented in this paper is based on S-parameter measurements over a large bias range and has been implemented in a SPICE simulator. The improvements consist of new equations for the non-linear capacitances and output conductance

Research paper thumbnail of Optical links for printed circuit boards

The 16th Annual Meeting of the IEEE Lasers and Electro-Optics Society, 2003. LEOS 2003., 2003

Research paper thumbnail of Electrical and optical transceivers for short-range data communication, fabricated in VLSI 90-nm bulk and SOI CMOS technology

IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05., 2005

Research paper thumbnail of A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006

A DC-to-44GHz amplifier with 19dB differential gain in a standard 90nm CMOS technology is present... more A DC-to-44GHz amplifier with 19dB differential gain in a standard 90nm CMOS technology is presented. Capacitive bandwidth and group-delay enhancements are combined with series peaking in a shunt-peaking amplifier. The circuit occupies 0.02mm2 and dissipates 57mW at 1V

Research paper thumbnail of Effect of body contacts on high-speed circuits in 90 nm CMOS SOI technology

International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005., 2005

Page 1. Effect of Body Contacts on High-Speed Circuits in 90 nm CMOS SOI Technology Jonas RM Weis... more Page 1. Effect of Body Contacts on High-Speed Circuits in 90 nm CMOS SOI Technology Jonas RM Weiss&amp;#39;, Christian Menolfi1, Thomas Morf1, Martin L. Schmatz1, Heinz Jaeckel2 1 IBM Zurich Research Laboratory, 8803 Rtlschlikon ...

Research paper thumbnail of When Virtual Meets Physical at the Edge

ACM SIGMETRICS Performance Evaluation Review, 2015

Research paper thumbnail of BiCMOS Variable Gain LNA at C-Band with Ultra Low Power Consumption for WLAN

Lecture Notes in Computer Science, 2004

Research paper thumbnail of High-Q inductors on digital VLSI CMOS substrate for analog RF applications

Proceedings of the 2003 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference - IMOC 2003. (Cat. No.03TH8678), 2003

Research paper thumbnail of <title>Challenges for the introduction of board-level optical interconnect technology into product development roadmaps</title>

Optoelectronic Integrated Circuits VIII, 2006

Optical interconnects have gradually replaced electrical interconnects in the long-distance telec... more Optical interconnects have gradually replaced electrical interconnects in the long-distance telecom, local-area, and rackto- rack link classes. We believe that this transition will also happen in the card-backplane-card datacom link class, both for bandwidth*length reasons and for density reasons. In analogy to the transition from individually wired boards to integrated printed circuit boards, we believe that eventually board-level optical interconnects

Research paper thumbnail of Member. /EEE, Christian Kromer

Research paper thumbnail of Technology independent degradation of minimum noise figure due to pad parasitics

1998 IEEE MTT-S International Microwave Symposium Digest (Cat. No.98CH36192), 1998

In order to investigate the influence of pad parasitics on device noise performance, noise parame... more In order to investigate the influence of pad parasitics on device noise performance, noise parameters on Si CMOS, GaAs MESFET and GaAs p-HEMT transistors were determined. Measurements of devices with various gate widths demonstrate that the parasitic losses of the pads substantially influence the noise performance independent of FET technology. To accurately separate the noise contribution of the pad and

Research paper thumbnail of A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

A 23 (22 data+1 clk) lane source-synchronous RX PHY for server systems is realized in 65 nm CMOS ... more A 23 (22 data+1 clk) lane source-synchronous RX PHY for server systems is realized in 65 nm CMOS supporting FB-DIMM 2 and QP11.0 multiple link protocols at 4.8-6.4 Gb/s. To minimize jitter, either a poly-phase filter or clean-up PLL can be selected for l/Q clock generation. Power consumption of 4.5 mW/Gb/s is achieved in the product-level design by a pulsed

Research paper thumbnail of A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

Research paper thumbnail of <title>Low-cost electro-optical package for use with PCB-embedded waveguides</title>

Active and Passive Optical Components for Communications VII, 2007

We present a novel approach for packaging high-speed opto-electronic 12x-array devices in a compa... more We present a novel approach for packaging high-speed opto-electronic 12x-array devices in a compact, low-cost package for waveguide-based intra-system links. In order to avoid optical signal loss and crosstalk, the mutual alignment between PCB-embedded multimode waveguides and the opto-electronic components needs to be in the order of 5-10 micrometer, which is an order of magnitude tighter than standard PCB manufacturing

Research paper thumbnail of A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006

A divide-by-4 circuit operates for input frequencies from 31 to 41 GHz at signal amplitudes &... more A divide-by-4 circuit operates for input frequencies from 31 to 41 GHz at signal amplitudes &amp;amp;amp;amp;amp;quot;0.5Vpp. The circuit consists of a dynamic followed by a static frequency divider. The dynamic and static frequency dividers consume 2mA and 1mA, respectively, from a 1.1V supply

Research paper thumbnail of ISSCC 2007/SESSION 24/MULTI-GB/s TRANSCEIVERS/24.6

Research paper thumbnail of TRANSACTIONS LETTERS-Synchronization-Low-Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components

Research paper thumbnail of Multiplexer and demultiplexer

Research paper thumbnail of Integrated line driver

Research paper thumbnail of Continuously tunable inductor and method to continuously tune an inductor