Masoud Babaie - Academia.edu (original) (raw)

Papers by Masoud Babaie

Research paper thumbnail of Artificial Neural Network Modelling for Cryo-CMOS Devices

2021 IEEE 14th Workshop on Low Temperature Electronics (WOLTE)

Research paper thumbnail of Cryo-CMOS Electronic Control for Scalable Quantum Computing

Proceedings of the 54th Annual Design Automation Conference 2017

Research paper thumbnail of 9.3 A680 μW Burst-Chirp UWB Radar Transceiver for Vital Signs and Occupancy Sensing up to 15m Distance

2019 IEEE International Solid- State Circuits Conference - (ISSCC)

Research paper thumbnail of A Low-Jitter and Low-Spur Charge-Sampling PLL

IEEE Journal of Solid-State Circuits

Research paper thumbnail of 15.5 Cryo-CMOS circuits and systems for scalable quantum computing

2017 IEEE International Solid-State Circuits Conference (ISSCC)

Research paper thumbnail of CMOS-based cryogenic control of silicon quantum circuits

Research paper thumbnail of Cryo-CMOS for Analog/Mixed-Signal Circuits and Systems

2020 IEEE Custom Integrated Circuits Conference (CICC)

Research paper thumbnail of Analysis and Design of Power Supply Circuits for RF Oscillators

IEEE Transactions on Circuits and Systems I: Regular Papers

Research paper thumbnail of A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons

IEEE Journal of Solid-State Circuits

Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qu... more Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantumcomputing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits

Research paper thumbnail of A Switched-Capacitor DC-DC Converter Powering an LC Oscillator to Achieve 85% System Peak Power Efficiency and −65dBc Spurious Tones

IEEE Transactions on Circuits and Systems I: Regular Papers

In this paper, we propose a new scheme to directly power a 4.9-5.6 GHz LC oscillator from a recur... more In this paper, we propose a new scheme to directly power a 4.9-5.6 GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3-2.2 V and <2 mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is <1.5 nV/ √ Hz, which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65 dBc under the 30 mV pp ripple of the converter.

Research paper thumbnail of Characterization and Analysis of On-Chip Microwave Passive Components at Cryogenic Temperatures

IEEE Journal of the Electron Devices Society

This paper presents the characterization and modeling of microwave passive components in TSMC 40-... more This paper presents the characterization and modeling of microwave passive components in TSMC 40-nm bulk CMOS, including metal-oxide-metal (MoM) capacitors, transformers, and resonators, at deep cryogenic temperatures (4.2 K). To extract the parameters of the passive components, the pad parasitics were de-embedded from the test structures using an open fixture. The variations in capacitance, inductance and quality factor are explained in relation to the temperature dependence of the physical parameters, and the resulting insights on the modeling of passives at cryogenic temperatures are provided. Modeling the characteristics of on-chip passive components, presented for the first time down to 4.2 K, is essential in designing cryogenic CMOS radio-frequency integrated circuits, a promising candidate to build the electronic interface for scalable quantum computers.

Research paper thumbnail of A Wideband Low-Power Cryogenic CMOS Circulator for Quantum Applications

IEEE Journal of Solid-State Circuits

Quantum computers require classical electronics to ensure fault-tolerant operation. To address co... more Quantum computers require classical electronics to ensure fault-tolerant operation. To address compactness and scalability, it was proposed to implement such electronics as integrated circuits operating at cryogenic temperatures close to those at which quantum bits (qubits) operate. Circulators are among the most common blocks used in the qubit readout chain, but they are currently discrete devices with a bulky footprint, thus preventing large-scale system integration. For this reason, we present here a detailed description of the first fully integrated CMOS circulator operating from 300 K down to 4.2 K to be an integral part of cryogenic quantum computing platforms. At 300 K, the circuit's operating frequency is centered around 6.5 GHz with 28% fractional bandwidth, and it has 2.2-dB insertion loss, 2.4-dB noise figure, and 18-dB isolation while consuming 2.5-mW core power. These results are achieved thanks to a fully passive architecture based on LC all-pass filters, which allows achieving a 1.6× increase in fractional bandwidth and the lowest power consumption with respect to the state of the art while using only 0.45 mm 2 of core area. This allows miniaturization of circulators in power-constrained multi-qubit readout systems.

Research paper thumbnail of An Ultra-Low Power Burst-Chirp UWB Radar Transceiver for Indoor Vital Signs and Occupancy Sensing in 40nm CMOS

IEEE Solid-State Circuits Letters

Research paper thumbnail of A Cryogenic CMOS Parametric Amplifier

IEEE Solid-State Circuits Letters

Research paper thumbnail of RF CMOS Oscillators for Modern Wireless Applications

RF CMOS Oscillators for Modern Wireless Applications

Research paper thumbnail of A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS

IEEE Journal of Solid-State Circuits

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from ... more This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter "doubles" the supply voltage to all the digital circuitry and particularly regulates the time-to-digital converter (TDC) supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage, and temperature (PVT). The ADPLL supports a two-point modulation and forms a Bluetooth low-energy (BLE) transmitter realized in 28-nm CMOS. It maintains in-band PN of −106 dBc/Hz [figure of merit (FoM) of −239.2 dB] and rms jitter of 0.86 ps while dissipating only 1.6 mW at 40-MHz reference. The power consumption reduces to 0.8 mW during the BLE transmission when the DCO switches to open loop.

Research paper thumbnail of A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation

IEEE Journal of Solid-State Circuits

In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it ma... more In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc-dc converter generating fairly large ripples. A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator's tail current and thus its oscillating amplitude. The parasitic capacitance of the active devices and correspondingly the oscillation frequency are stabilized in turn. A calibration loop is also integrated on-chip to automatically set the optimum replication gain that minimizes the variation of the oscillation amplitude. A 4.9-5.6-GHz oscillator is realized in 40-nm CMOS and occupies 0.23 mm 2 while consuming 0.8-1.3 mW across the tuning range (TR). The supply pushing is improved to <1 MHz/V resulting in a low < −49-dBc spur due to 0.5-12-MHz sinusoidal supply ripples as large as 50 mV pp. We experimentally verify the effectiveness of the proposed technique also in face of saw-tooth, multi-tone, and modulated supply ripples.

Research paper thumbnail of An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

IEEE Transactions on Circuits and Systems I: Regular Papers

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, whic... more We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <−107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits −157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <−91 dBc, while fractional spurs are <−55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm 2. Index Terms-All-digital PLL (ADPLL), digitally controlled oscillator (DCO), time-to-digital converter (TDC), spurs, long-term evolution (LTE), 4G cellular. I. INTRODUCTION M OBILE phones enjoy the largest production volume of any consumer electronics product. However, the demands they place on monolithic local oscillators (LO), realized as RF PLLs, are particularly tough, especially on integration with digital processors, low area of silicon, low power consumption, low phase noise (PN), and virtually no spurious tones, while being robust against environmental changes. Moreover, as each wireless standard has its own set of specifications, the implementation of a multi-standard PLLs has become a challenging task. For instance, narrow bandwidth systems, such as GSM of 2G and enhanced data rate for WCDMA of 3G, put enormous stress on low out-of-band PN, while wide bandwidth systems, such as 4G/5G, demand Manuscript

Research paper thumbnail of Tuning Range Extension of a Transformer-Based Oscillator Through Common-Mode Colpitts Resonance

IEEE Transactions on Circuits and Systems I: Regular Papers

In this paper, we propose a method to broaden a tuning range of a CMOS LC-tank oscillator without... more In this paper, we propose a method to broaden a tuning range of a CMOS LC-tank oscillator without sacrificing its area. The extra tuning range is achieved by forcing a strongly coupled transformer-based tank into a common-mode resonance at a much higher frequency than in its main differential-mode oscillation. The oscillator employs separate active circuits to excite each mode but it shares the same tank, which largely dominates the core area but is on par with similar single-core designs. The tank is forced in common-mode oscillation by two injection locked Colpitts oscillators at the transformer's primary winding, while a two-port structure provides differential-mode oscillation. An analysis is also presented to compare the phase noise performance of the dual-core oscillator in common-mode and differential-mode excitations. A prototype implemented in digital 40-nm CMOS verifies the dual-mode oscillation and occupies only 0.12 mm 2 and measures 56% tuning range.

Research paper thumbnail of Cryo-CMOS Circuits and Systems for Quantum Computing Applications

IEEE Journal of Solid-State Circuits

A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet ver... more A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F 2,3 digitally controlled oscillator required to manipulate the state of qubits.

Research paper thumbnail of Artificial Neural Network Modelling for Cryo-CMOS Devices

2021 IEEE 14th Workshop on Low Temperature Electronics (WOLTE)

Research paper thumbnail of Cryo-CMOS Electronic Control for Scalable Quantum Computing

Proceedings of the 54th Annual Design Automation Conference 2017

Research paper thumbnail of 9.3 A680 μW Burst-Chirp UWB Radar Transceiver for Vital Signs and Occupancy Sensing up to 15m Distance

2019 IEEE International Solid- State Circuits Conference - (ISSCC)

Research paper thumbnail of A Low-Jitter and Low-Spur Charge-Sampling PLL

IEEE Journal of Solid-State Circuits

Research paper thumbnail of 15.5 Cryo-CMOS circuits and systems for scalable quantum computing

2017 IEEE International Solid-State Circuits Conference (ISSCC)

Research paper thumbnail of CMOS-based cryogenic control of silicon quantum circuits

Research paper thumbnail of Cryo-CMOS for Analog/Mixed-Signal Circuits and Systems

2020 IEEE Custom Integrated Circuits Conference (CICC)

Research paper thumbnail of Analysis and Design of Power Supply Circuits for RF Oscillators

IEEE Transactions on Circuits and Systems I: Regular Papers

Research paper thumbnail of A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons

IEEE Journal of Solid-State Circuits

Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qu... more Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantumcomputing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits

Research paper thumbnail of A Switched-Capacitor DC-DC Converter Powering an LC Oscillator to Achieve 85% System Peak Power Efficiency and −65dBc Spurious Tones

IEEE Transactions on Circuits and Systems I: Regular Papers

In this paper, we propose a new scheme to directly power a 4.9-5.6 GHz LC oscillator from a recur... more In this paper, we propose a new scheme to directly power a 4.9-5.6 GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3-2.2 V and <2 mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is <1.5 nV/ √ Hz, which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65 dBc under the 30 mV pp ripple of the converter.

Research paper thumbnail of Characterization and Analysis of On-Chip Microwave Passive Components at Cryogenic Temperatures

IEEE Journal of the Electron Devices Society

This paper presents the characterization and modeling of microwave passive components in TSMC 40-... more This paper presents the characterization and modeling of microwave passive components in TSMC 40-nm bulk CMOS, including metal-oxide-metal (MoM) capacitors, transformers, and resonators, at deep cryogenic temperatures (4.2 K). To extract the parameters of the passive components, the pad parasitics were de-embedded from the test structures using an open fixture. The variations in capacitance, inductance and quality factor are explained in relation to the temperature dependence of the physical parameters, and the resulting insights on the modeling of passives at cryogenic temperatures are provided. Modeling the characteristics of on-chip passive components, presented for the first time down to 4.2 K, is essential in designing cryogenic CMOS radio-frequency integrated circuits, a promising candidate to build the electronic interface for scalable quantum computers.

Research paper thumbnail of A Wideband Low-Power Cryogenic CMOS Circulator for Quantum Applications

IEEE Journal of Solid-State Circuits

Quantum computers require classical electronics to ensure fault-tolerant operation. To address co... more Quantum computers require classical electronics to ensure fault-tolerant operation. To address compactness and scalability, it was proposed to implement such electronics as integrated circuits operating at cryogenic temperatures close to those at which quantum bits (qubits) operate. Circulators are among the most common blocks used in the qubit readout chain, but they are currently discrete devices with a bulky footprint, thus preventing large-scale system integration. For this reason, we present here a detailed description of the first fully integrated CMOS circulator operating from 300 K down to 4.2 K to be an integral part of cryogenic quantum computing platforms. At 300 K, the circuit's operating frequency is centered around 6.5 GHz with 28% fractional bandwidth, and it has 2.2-dB insertion loss, 2.4-dB noise figure, and 18-dB isolation while consuming 2.5-mW core power. These results are achieved thanks to a fully passive architecture based on LC all-pass filters, which allows achieving a 1.6× increase in fractional bandwidth and the lowest power consumption with respect to the state of the art while using only 0.45 mm 2 of core area. This allows miniaturization of circulators in power-constrained multi-qubit readout systems.

Research paper thumbnail of An Ultra-Low Power Burst-Chirp UWB Radar Transceiver for Indoor Vital Signs and Occupancy Sensing in 40nm CMOS

IEEE Solid-State Circuits Letters

Research paper thumbnail of A Cryogenic CMOS Parametric Amplifier

IEEE Solid-State Circuits Letters

Research paper thumbnail of RF CMOS Oscillators for Modern Wireless Applications

RF CMOS Oscillators for Modern Wireless Applications

Research paper thumbnail of A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS

IEEE Journal of Solid-State Circuits

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from ... more This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter "doubles" the supply voltage to all the digital circuitry and particularly regulates the time-to-digital converter (TDC) supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage, and temperature (PVT). The ADPLL supports a two-point modulation and forms a Bluetooth low-energy (BLE) transmitter realized in 28-nm CMOS. It maintains in-band PN of −106 dBc/Hz [figure of merit (FoM) of −239.2 dB] and rms jitter of 0.86 ps while dissipating only 1.6 mW at 40-MHz reference. The power consumption reduces to 0.8 mW during the BLE transmission when the DCO switches to open loop.

Research paper thumbnail of A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation

IEEE Journal of Solid-State Circuits

In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it ma... more In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc-dc converter generating fairly large ripples. A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator's tail current and thus its oscillating amplitude. The parasitic capacitance of the active devices and correspondingly the oscillation frequency are stabilized in turn. A calibration loop is also integrated on-chip to automatically set the optimum replication gain that minimizes the variation of the oscillation amplitude. A 4.9-5.6-GHz oscillator is realized in 40-nm CMOS and occupies 0.23 mm 2 while consuming 0.8-1.3 mW across the tuning range (TR). The supply pushing is improved to <1 MHz/V resulting in a low < −49-dBc spur due to 0.5-12-MHz sinusoidal supply ripples as large as 50 mV pp. We experimentally verify the effectiveness of the proposed technique also in face of saw-tooth, multi-tone, and modulated supply ripples.

Research paper thumbnail of An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

IEEE Transactions on Circuits and Systems I: Regular Papers

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, whic... more We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <−107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits −157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <−91 dBc, while fractional spurs are <−55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm 2. Index Terms-All-digital PLL (ADPLL), digitally controlled oscillator (DCO), time-to-digital converter (TDC), spurs, long-term evolution (LTE), 4G cellular. I. INTRODUCTION M OBILE phones enjoy the largest production volume of any consumer electronics product. However, the demands they place on monolithic local oscillators (LO), realized as RF PLLs, are particularly tough, especially on integration with digital processors, low area of silicon, low power consumption, low phase noise (PN), and virtually no spurious tones, while being robust against environmental changes. Moreover, as each wireless standard has its own set of specifications, the implementation of a multi-standard PLLs has become a challenging task. For instance, narrow bandwidth systems, such as GSM of 2G and enhanced data rate for WCDMA of 3G, put enormous stress on low out-of-band PN, while wide bandwidth systems, such as 4G/5G, demand Manuscript

Research paper thumbnail of Tuning Range Extension of a Transformer-Based Oscillator Through Common-Mode Colpitts Resonance

IEEE Transactions on Circuits and Systems I: Regular Papers

In this paper, we propose a method to broaden a tuning range of a CMOS LC-tank oscillator without... more In this paper, we propose a method to broaden a tuning range of a CMOS LC-tank oscillator without sacrificing its area. The extra tuning range is achieved by forcing a strongly coupled transformer-based tank into a common-mode resonance at a much higher frequency than in its main differential-mode oscillation. The oscillator employs separate active circuits to excite each mode but it shares the same tank, which largely dominates the core area but is on par with similar single-core designs. The tank is forced in common-mode oscillation by two injection locked Colpitts oscillators at the transformer's primary winding, while a two-port structure provides differential-mode oscillation. An analysis is also presented to compare the phase noise performance of the dual-core oscillator in common-mode and differential-mode excitations. A prototype implemented in digital 40-nm CMOS verifies the dual-mode oscillation and occupies only 0.12 mm 2 and measures 56% tuning range.

Research paper thumbnail of Cryo-CMOS Circuits and Systems for Quantum Computing Applications

IEEE Journal of Solid-State Circuits

A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet ver... more A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F 2,3 digitally controlled oscillator required to manipulate the state of qubits.