Massimo Alioto - Academia.edu (original) (raw)

Papers by Massimo Alioto

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS), 2014

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design - SBCCI '14, 2014

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013

ABSTRACT A 346μm2 reference-free, asynchronous VCO-based sensor interface circuit is demonstrated... more ABSTRACT A 346μm2 reference-free, asynchronous VCO-based sensor interface circuit is demonstrated in 28nm LP CMOS. This design does not require high accuracy current sources, voltage sources, or low jitter timing references. It achieves wide resolution and voltage scalability, and consumes only ~1/100th the area of prior approaches. Resolution can be scaled from 2.8 to 11.7 bits and VDD from 500mV to 1.0V.

Abstract í an ultra-low-power active RFID tag chip with multiple power and clock domains has been... more Abstract í an ultra-low-power active RFID tag chip with multiple power and clock domains has been designed and verified. The chip employs a wake-up scheme to reduce its power consumption. It includes a wake-up analog regulator and oscillator as well as a digital ...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

ESSDERC 2007 - 37th European Solid State Device Research Conference, 2007

ABSTRACT This paper investigates with a mixed device/circuit simulation methodology the effective... more ABSTRACT This paper investigates with a mixed device/circuit simulation methodology the effectiveness of DG SOI MOSFETs compared to conventional bulk MOSFETs for the implementation of low standby power circuit techniques. Our results indicate that DG MOSFETs offer significant advantages essentially because of the larger V T sensitivity to back-biasing.

Lecture Notes in Computer Science, 2009

In this paper, FinFET stacks consisting of mixed three- (3T) and four-terminal (4T) devices are a... more In this paper, FinFET stacks consisting of mixed three- (3T) and four-terminal (4T) devices are analyzed in terms of leakage. A novel figure of merit is introduced, and closed-form leakage models are derived. Analytical results are used to derive simple design criteria to minimize the leakage by properly mixing 3T and 4T devices in transistor stacks. The comparison with a

2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014

ABSTRACT In this work the effectiveness of Leakage Power Analysis (LPA), a new class of side-chan... more ABSTRACT In this work the effectiveness of Leakage Power Analysis (LPA), a new class of side-channel attacks against cryptographic circuits, has been demonstrated on a case study. LPA attacks have been mounted against a bit slice implementation of the Serpent block cipher. After having measured the leakage contribution of a bit slice unit inside the processor, chosen as selection function for LPA attacks, an adequate power model has been identified. In order to consider the on-chip noise due to the static consumption of the other logics inside the processor, an estimation of the SNR has been provided according to the count of equivalent gates. The bit slice sub-block has been designed in a 65nm CMOS technology node for different logic styles, i.e. CMOS, WDDL, MDPL, and SABL. Simulations show that for each logic implementation the correct key of the algorithm has been recovered with a maximum of 50.000 measurements, demonstrating that LPA attack can be successfully carried out against a wide range of logic styles, even if they efficiently thwart standard DPA and CPA attacks. Static power is expected to become greater in downscaled technologies, and thus LPA must be considered a serious threat for the security of cryptographic VLSI circuits.

Lecture Notes in Computer Science, 2011

ABSTRACT In this paper, an extensive comparison of flip-flop (FF) topologies for high-speed appli... more ABSTRACT In this paper, an extensive comparison of flip-flop (FF) topologies for high-speed applications is carried out in a 65-nm CMOS technology. This work goes beyond previous analyses in that traditional rankings do not include layout parasitics, which strongly affect both speed and energy and lead to drastic changes in the optimum transistor sizing. For this reason, in this work layout parasitics are included in the circuit design loop by adopting a novel strategy. The obtained results show that the energy efficiency and the performance of FFs is mainly determined by the regularity of their topology and layout. Finally, the area-delay tradeoff is also analyzed for the first time. KeywordsEnergy Efficiency-Clocking-Flip-Flops-High Speed-Energy-Delay-Nanometer CMOS-Interconnects-Layout Impact

Lecture Notes in Computer Science, 2009

In this paper, the impact of intradie process variations on the delay of nanometer Domino logic i... more In this paper, the impact of intradie process variations on the delay of nanometer Domino logic is investigated. Analysis shows that Domino logic circuits suffer from a 2X higher variability compared to static CMOS logic, which translates into a greater speed penalty. The main variability sources of Domino gates at the circuit level are identified and analyzed by means of

2009 European Conference on Circuit Theory and Design, 2009

In this paper, the influence of the clock slope (i.e., rise/fall time) on the performance and the... more In this paper, the influence of the clock slope (i.e., rise/fall time) on the performance and the energy dissipation of Pulsed flip-flop (FF) topologies is investigated. Results show that the adoption of a greater clock slope leads to a slight flip-flop energy increase, as well as to a negligible speed penalty. This insensitivity of Pulsed FF performance on the clock

2009 European Conference on Circuit Theory and Design, 2009

This paper analyzes Monte Carlo simulation procedures to estimate the impact of process intradie ... more This paper analyzes Monte Carlo simulation procedures to estimate the impact of process intradie variations on the delay variability of digital circuits. The traditional approach based on the separate evaluation of intradie and interdie variations is shown to be incorrect. Indeed, Monte Carlo simulations on a 65-nm CMOS technology show that this approach can lead to underestimation by up to

2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Abstract In this paper, the effect of process variations on the delay of CMOS static logic circui... more Abstract In this paper, the effect of process variations on the delay of CMOS static logic circuits is discussed versus fan-in. In particular, the effect of process variations in stacked transistors (which determine the fan-in) is analytically evaluated. From circuit analysis, a ...

Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010

In this paper, an optimization strategy is proposed for Dual Edge-Triggered (DET) clock distribut... more In this paper, an optimization strategy is proposed for Dual Edge-Triggered (DET) clock distribution in clock domains, based on the proper choice of the clock slope. The suggested approach takes full advantage of the intrinsic features of DET Flip-Flops to achieve up to 50% energy-savings compared to traditional DET design approaches. The speed penalty, in terms of both FFs delay

2012 IEEE International Solid-State Circuits Conference, 2012

ABSTRACT Flip-flops (FFs) are key building blocks in the design of high-speed energy-efficient mi... more ABSTRACT Flip-flops (FFs) are key building blocks in the design of high-speed energy-efficient microprocessors, as their data-to-output delay (D-Q) and power dissipation strongly affect the processor's clock period and overall power [1]. From previous analyses [2], the Transmission-Gate Pulsed Latch (TGPL) [3] proved to be the most energy-efficient FF in a large portion of the design space, ranging from high speed (minimizing EDj products with j>1) to minimum ED product designs [2], while simple Master-Slave FFs (TGFF [1] and ACFF [4]) are the most energy-efficient in the low-power E-D space region. TGPL also has the lowest D-Q delay along with STFF [5]. However, the latter has considerably worse energy efficiency [2], hence, the TGPL is the best reference for a comparison. In this work, two new FFs are introduced, the Conditional Push-Pull Pulsed Latch (CP3L), and a version with a Shareable (CSP3L) Pulse Generator (PG). The adoption of a fast push-pull second stage, which requires a conditional PG, enables 50-to-100% delay improvements compared to TGPL, and absolute D-Q up to 0.7FO4. CP3L and CSP3L also exhibit superior energy efficiency to TGPL in terms of minimum ED3 and ED products. A test chip is fabricated in 65nm CMOS technology (VDD=1V) to measure delay and energy consumption of CP3L, CSP3L and TGPL in minimum ED and ED3 sizings. Different loadings are used in the minimum ED (16×) and the minimum ED3 (64×) cases.

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009), 2009

In this paper, the impact of clock slope specification on the energy consumption of a clock domai... more In this paper, the impact of clock slope specification on the energy consumption of a clock domain is analyzed. Results show that the clock slope requirement can be relaxed at the cost of a very small speed penalty and energy increase in the flip-flops (FFs). On the other hand, relaxing the clock slope specification allows for downsizing the local buffers

IEEE Transactions on Circuits and Systems I: Regular Papers, 2015

ABSTRACT In this paper, the impact of variations on single-edge triggered flip-flops (FFs) is eva... more ABSTRACT In this paper, the impact of variations on single-edge triggered flip-flops (FFs) is evaluated for a wide range of topologies. In particular, this Part II explicitly considers sources of variations such as voltage, temperature and variations induced by the clock network. The effect of variations on the energy and its tradeoff with performance is also investigated. This paper complements the previous Part I, which is focused on process variations and flip-flop timing. From a design perspective, the presented results provide well-defined guidelines for variation-aware selection of the flip-flop topologies, and for early budgeting of variations before detailed circuit design. Results are put into the technology scaling perspective through comparison of results at 65 and 28 nm. The results show that the technology scaling does not affect either the main findings of this analysis or the ranking of the considered topologies.