Pinaki Mazumder - Academia.edu (original) (raw)

Papers by Pinaki Mazumder

Public reporting burden lor this collection of information is estimated to average 1 .fcnur pe»' ... more Public reporting burden lor this collection of information is estimated to average 1 .fcnur pe»' response. Including the time for reviewing instruct data needed, and completing and reviewing this collection of information. Send comments regarding this burden estimate or any other asps? this burden to Department of Defense. Washington Headquarters Services. Directorate for Information Operations and Reports (0704-0188). 4302 Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty lor tailing to c valid OMB control number.

Integration, 2000

Performance in many very-large-scale-integrated (VLSI) systems such as digital signal processing ... more Performance in many very-large-scale-integrated (VLSI) systems such as digital signal processing (DSP) chips, is predominantly determined by the speed of arithmetic modules like adders and multipliers. Even though redundant arithmetic algorithms produce signi"cant improvements in performance through the elimination of carry propagation, e$cient circuit implementations of these algorithms have been traditionally di$cult to obtain. This work presents a survey of circuit implementations of redundant arithmetic algorithms. The described implementations are divided into three main groups: (1) conventional binary logic circuits, which encode the multivalued digits of redundant arithmetic into two or more binary digital signals; (2) current-mode multiple-valued logic circuits, which directly represent multivalued redundant digits using non-binary digital current signals; and (3) heterostructure and quantum electronic circuits, intended for very compact designs capable of operating at extremely high speeds. For each of the circuits, the operating principle is described and the main advantages and disadvantages of the approach are discussed and compared. 2000 Published by Elsevier Science B.V.

The ability of nonlinear oscillator networks to provide good heuristics for NP-hard optimization ... more The ability of nonlinear oscillator networks to provide good heuristics for NP-hard optimization problems attracts a significant attention to oscillator-based computing devices. Besides the case when such devices reproduce boolean logic, however, the origin of their computational capabilities remains largely unknown. We show that the dynamics of oscillator networks can be related to continuous relaxations of combinatorial optimization problems. This establishes a framework for classifying and evaluating the networks, outlining difficulties and further development perspectives. This also emphasizes the problem of rounding (reconstructing a binary Ising state). This problem remains underexplored, as the implemented dynamics force the network to collapse to a close-to-Ising state. We demonstrate, however, that such forcing may diminish the computational capabilities. This suggests that a consistent treatment of rounding may significantly improve various metrics of operation of already ...

Learning in Energy‐Efficient Neuromorphic Computing, 2019

For details of our global editorial offices, customer services, and more information about Wiley ... more For details of our global editorial offices, customer services, and more information about Wiley products visit us at www.wiley.com. Wiley also publishes its books in a variety of electronic formats and by print-on-demand. Some content that appears in standard print versions of this book may not be available in other formats.

IEEE Transactions on Neural Networks and Learning Systems, 2018

IEEE Transactions on Circuits and Systems I: Regular Papers, 2017

In energy-constrained applications, SRAM systems operating in the subthreshold region are often d... more In energy-constrained applications, SRAM systems operating in the subthreshold region are often deployed to reduce power consumption. Subthreshold SRAM designs, however, confront numerous challenges such as susceptibility to process variation and reduced on-off current ratio. Statistical modeling of the variation in cell stability is critical in SRAM design, especially for designs operating in the subthreshold region where the process and temperature variations are the most pronounced. In this paper, statistical models for estimating static noise margins (SNM) of SRAM cells are built from the perspective of a shifted voltage transfer characteristic. Read (Hold) SNM of a subthreshold 8T cell is analyzed. It is shown that the distribution of a single-sided Read SNM is a weighted sum of several normal distributions instead of a regular Gaussian distribution. The proposed statistical model is verified with simulation results in 65 nm technology. Furthermore, to mitigate performance and yield degradation, an adaptive body biasing circuit is developed. It is demonstrated through simulation that, with a negligible area and power overhead, the proposed circuit achieves a 15% improvement in the worst-case Read SNM.

IEEE Transactions on Communications, 2019

T HE inception of spoof surface plasmon polariton (SSPP) mode realized in planar, patterned condu... more T HE inception of spoof surface plasmon polariton (SSPP) mode realized in planar, patterned conductors to manage light beyond diffraction limit at a chosen frequency garnered significant attention of late. We show that, an SSPP channel can be chosen to act in two distinct ways: first, as a regular RC limited electrical interconnect at low frequencies; and second, as an exotic, beyond RC limit communication channel near its resonant frequency by binding the electromagnetic field on its surface to the elimination of capacitance C. A dynamic transformation between these two modes can constitute an energy economic, tera-scale inter-chip hybrid communication network. We have investigated theoretical limits on the information transfer capability of SSPP interconnects. We show that, a geometry dependent trade-off relation between crosstalk limited bandwidth density and information traveling length emerges in SSPP based communication networks. According to our analysis, a bandwidth density of 1 Gbps/µm is attainable in SSPP communication network with ∼ 10 mm information transfer distance, where each channel can carry ∼ 300 Gbps information with nominal cross-talk.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2017

In numerous memory and communication systems, Bose-Chaudhuri-Hocquenghem (BCH) codes are widely e... more In numerous memory and communication systems, Bose-Chaudhuri-Hocquenghem (BCH) codes are widely employed to enhance reliability. One-pass Chase soft-decision decoding algorithm for BCH code was previously proposed to achieve significant performance improvement over traditional harddecision decoding while not increasing too much computational complexity. The bottleneck in a conventional one-pass Chase decoding is the procedure of judging whether an obtained error locator polynomial is valid. In this paper, a novel algorithm that can efficiently verify eligibility of each generated error locator polynomial is proposed. The problem is first reformulated as a polynomial modulo problem, where repeated squaring can be employed for further simplification. In order to decrease the critical path delay and hardware complexity, an efficient polynomial division algorithm based on polynomial inversion is also proposed. In addition, a VLSI architecture for the proposed algorithm is presented. The implemented results show that the proposed eligibility checking algorithm reduces the gate counts to only 12% of a conventional polynomial selection algorithm without introducing any speed penalty. The projected area reduction achieved in a complete one-pass Chase decoder is approximately 75%. In addition, post-layout simulation shows that the proposed algorithm is 20 times more power-efficient than the conventional method.

IEEE Transactions on Terahertz Science and Technology, 2016

Propagation of THz wave utilizing spoof surface plasmon polariton (SSPP) earned a great deal of a... more Propagation of THz wave utilizing spoof surface plasmon polariton (SSPP) earned a great deal of attention due to the ability of SSPP modes to guide THz waves at very low dispersion. We present an investigation of the SSPP beam splitter, one of the key elements of many optical setups. In contrast with conventional free space implementations, in the case of the SSPP beam splitter one can no longer disregard scattering of incoming wave back into the input channels. Thus, SSPP implementations must take into consideration both the splitting ratio and the backscattering as important parameters characterizing the beam splitter. Three different designs representing different approaches to solving the problem of the relation between these parameters are investigated. The mathematical formalism to study the dispersion diagrams is proposed. The frequency dependence of splitting ratio, scattering parameters and backscattering for each beam splitter is investigated. Finally, by employing one of the proposed beam splitter a controllable filter is designed and analyzed.

Memristors promise higher device density and design flexibility. Besides utilizing memristors for... more Memristors promise higher device density and design flexibility. Besides utilizing memristors for digital memory, another promising avenue for adoption is the advancement of neural network circuits capable of learning. Neural network implementations with memristors have been proposed, including memristor synaptic training methodologies. This work highlights applications of a neural learning methodology inspired by Q-learning. Memristors are used as analog storage elements to store a large Q-table. The method is qualified with a maze problem in order to show that the proposed network can be used to learn to approximate an optimal path to solving the maze problem. Brief results highlighting the methodology on a maze problem and discussion on generating random keys are provided. This work combines model-free reinforcement learning with neural networks.

arXiv: Quantum Physics, 2019

We consider a general family of quantum key distribution (QKD) protocols utilizing displaced ther... more We consider a general family of quantum key distribution (QKD) protocols utilizing displaced thermal states with discretized modulations. Separating the effects of the Gaussian channel and the non-Gaussian distribution, we have studied the dependence of the secret key generation rate on the magnitude of modulations (the strength of the modulated signal). We show that in the limit of strong signal, QKD is impossible: from the perspective of an efficient eavesdropper, the ensemble of transmitted states is effectively classical. This constitutes a quantum correction to performance of finite-length QKD protocols. We demonstrate that two regimes must be distinguished: weak and strong thermal noise. In the case of strong noise, the security boundary is mostly determined by the weak-signal limit. When the noise is weak, however, QKD may become possible only when the signal strength exceeds some critical value.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

In this paper, we present a novel thermal analysis method for VLSI circuits based on the Green's ... more In this paper, we present a novel thermal analysis method for VLSI circuits based on the Green's function of heat conduction problem. Our approach can calculate the temperature distribution in the simulated chip very efficiently based on the proposed semi-analytical Green's function technique, which computes the Green's function online with only small overhead for building the Green's function library in prior for the given chip structure. Experimental results validate the accuracy of the semi-analytical Green's function. Our thermal analysis approach can adapt to the case that multi-layer heterogeneous heat conduction materials need be considered for the purpose of obtaining accurate thermal simulation results.

Proceedings of 7th International Conference on VLSI Design

Abstract In this paper a stochastic optimization algorithm called SAGA is presented, which is a g... more Abstract In this paper a stochastic optimization algorithm called SAGA is presented, which is a generalization of the ge-netic algorithm and the simulated annealing algorithm. Depending on the settings of its control parameters, SAGA executes as a genetic algorithm, a ...

2003 Design, Automation and Test in Europe Conference and Exhibition

Dynamic noise analysis is recently gaining more attention as a definitive method to overcome glar... more Dynamic noise analysis is recently gaining more attention as a definitive method to overcome glaring deficiencies of static noise analysis. Exact dynamic noise analysis requires modeling of both injected noise and propagated noise. In this paper, we have developed a strategy to study the noise propagation problem. An efficient analytical formula has been derived to accurately model the noise waveform transfer characteristic of dynamic CMOS logic gates. Experiments have shown that the maximum error in peak propagated noises of the proposed model is less than 10%.

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design

This paper introduces a new numerical approximation technique, called the Differential Quadrature... more This paper introduces a new numerical approximation technique, called the Differential Quadrature Method (DQM), in order to derive the rational ABCD matrix representing the high-speed interconnect. DQM is an efficient differential equation solver that can quickly compute the derivative of a smooth function by estimating a weighted linear sum of the function values at few mesh points in the domain of the function. Using DQM, the ×-domain Telegrapher's equations of interconnect are discretized as a set of easily solvable algebraic equations, which lead to the rational ABCD matrix. The entries of ABCD matrix take the form of rational approximations with respect to ×, rather than the conventional ABCD matrix whose entries are complex transcendental functions in ×. Although the rationalization result is comparable with Padé approximation of AWE, DQM does not require moment-generating or moment-matching. For both uniform and nonuniform interconnects, DQM-based rational ABCD matrices lead to high accuracy as well as high efficiency for transient analysis of high-speed interconnects.

IEEE Journal on Selected Areas in Communications

A well-known empirical rule for the demand of wireless communication systems is that of Edholm's ... more A well-known empirical rule for the demand of wireless communication systems is that of Edholm's law of bandwidth. It states that the demand for bandwidth in wireless short-range communications doubles every 18 months. With the growing demand for bandwidth and the decreasing cell size of wireless systems, terahertz (THz) communication systems are expected to become increasingly important in modern day applications. With this expectation comes the need for protecting users' privacy and security in the best way possible. With that in mind, we show that quantum key distribution can operate in the THz regime and we derive the relevant secret key rates against realistic collective attacks. In the extended THz range (from 0.1 to 50 THz), we find that below 1 THz, the main detrimental factor is thermal noise, while at higher frequencies it is atmospheric absorption. Our results show that high-rate THz quantum cryptography is possible over distances varying from a few meters using direct reconciliation, to about 220m via reverse reconciliation. We also give a specific example of the physical hardware and architecture that could be used to realize our THz quantum key distribution scheme.

IEEE Transactions on Terahertz Science and Technology

IEE Proceedings E Computers and Digital Techniques

The paper investigates the layout optimisation problem for processor-array networks. If an approp... more The paper investigates the layout optimisation problem for processor-array networks. If an appropriate shape geometry is selected for the processors, a specific interconnection network can be area-eficiently mapped on a VLSI/WSI chip to maximise the chip yield, operational reliability and circuit performance. A formal technique of cellular layout by polyomino tiles is proposed, with application to mapping a variety of processor geometries onto specific array networks. The layout algorithms are expressed in a new notational language, which is amenable to cellular layout in contrast to classical procedural languages. The layout technique is illustrated with both well known parallel-processing array networks and a new fault-tolerant square mesh with reconfigurable processors and interconnect. The square mesh with redundant processors provides high yield and operational reliability.